Download 11-ch13-io_systems - pnu-cs-os

Princess Nora University
Faculty of Computer & Information Systems
Computer science Department
Operating Systems
(CS 340 D)
Maram AlShablan
(Chapter-13)
I/O Systems
Chapter 13: I/O Systems
1. Overview of an operating system’s I/O subsystem structure.
2. I/O Hardware.
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OBJECTIVES:
 To describe the structure of an operating system’s I/O
subsystem.
 To discuss the principles and complexities of I/O hardware.
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Overview
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Overview
Management of I/O devices and I/O operations is a main
task for the operating system.
Challenges with I/O devices

I/O devices vary so widely in their function and speed.
Different categories:
Storage devices (disks, tapes), transmission devices (network connections, Bluetooth),
and human-interface devices (screen, keyboard, mouse, audio in and out).

Various methods to control them.
These methods form the I/O subsystem of the kernel, which separates the rest of the
kernel from the complexities of managing I/O devices.

New types of devices frequent.
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I/O Hardware
A device communicates with a computer system by sending signals
over a cable or even through the air.
The common concepts to understand how the devices are attached
and how the software can control the hardware are:
 Port – connection point for device, e.g. a serial or parallel
port.
 Bus – connecting multiple devices. It is a set of wires vary in
their signaling methods, speed, throughput, and connection
methods.
 Device Controller – is a collection of electronics that can
operate a port, a bus, or a device.
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A typical PC bus structure
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I/O Hardware (Cont.)
Buses
PCI bus – connects high-speed high-bandwidth devices
to the memory subsystem and the CPU.
Expansion bus – connects slower low-bandwidth
devices, which typically deliver data one character at a
time (with buffering), such as the keyboard and serial and
USB ports.
Small Computer System Interface (SCSI) - bus
plugged into a SCSI controller.



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I/O Hardware (Cont.)
Device Controller
 A general-purpose computer system consists of CPUs and
multiple device controllers that are connected through a
common bus (i.e. controller accepts commands from the
processor through buses)

Each device controller handles one type of device or small
class of them (e.g. SCSI).

Device controller maintains some local buffer storage and a
set of special-purpose registers.
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I/O Hardware (Cont.)
How does the processor actually talk to the device to
accomplish an I/O transfer?
The processor interacts with a Controller by reading and
writing bit patterns in its registers.
Regardless of the complexity of the connections and
buses, processor accesses registers in two ways:
1- I/O instructions
2- Memory mapped I/O
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1-
I/O instructions
One way of communicating with devices is through registers
associated with each port.

I/O instructions transfer of a byte or word to an I/O port
address.
An I/O port typically consists of four registers:
The data-in register - is read by the host to get input from the
device.
The data-out register is written by the host to send output.
The status register contains bits that can be read by the host.
These bits indicate states, such as idle, ready for input, busy, error,
transaction complete, etc.
The control register has bits written by the host to issue
commands or to change settings of the device, such as parity
checking. (A parity check is the process that ensures accurate data
1.
2.
3.
4.
transmission between nodes during communication)
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2-
Memory mapped I/O
Another way for communicating with devices is memory-mapped
I/O.

Used to avoid programmed I/O (one byte at a time) for large data
movement that would slow down the CPU

In this case the CPU executes I/O requests using the standard
data-transfer instructions to read and write the device-control
registers at their mapped locations in physical memory.

Memory-mapped I/O is suitable for devices which must move
large quantities of data quickly, such as graphics cards.
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I/O Hardware (Cont.)
The OS needs to know when:


The I/O device has completed an operation
The I/O operation has encountered an error
I/O Interrupt:
 The CPU hardware has a wire called the interrupt-request line that the
CPU senses after executing every instruction.
 When the CPU detects that a controller has asserted a signal on the
interrupt-request line, the CPU performs a state save and jumps to the
interrupt-handler routine.
Polling:
 The controller sets the busy bit when it is busy working on a command, and
clears the busy bit when it is ready to accept the next command.

Polling is a looping process, reading the status register over and over until
the busy bit of status register becomes clear.
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Thank you
End of
Chapter 13
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