Download Post CMOS Devices

Post CMOS Devices
George Bourianoff PhD
Intel Corporation
Semiconductor Research Corporation
Outline
1. In the beginning
2. The age of CMOS
1. Moore’s law
2. Trends
3. limits to CMOS?
3. Beyond CMOS
1. Memory devices
2. Logic devices
3. New architectures
4. Conclusions
SRC/File name/ 2
In the
beginning
u “Only one type of detector is now in use, the crystal”
(Manual of wireless telegraphy for the use of naval electricians, 1913)
u “The detectors now in general use are the crystal and the audion
[vacuum tube] “
(Manual of wireless telegraphy for the use of naval electricians, 1919)
u [vacuum tube] “replacing the crystal for all ordinary purposes”
(British Admiralty handbook of wireless telegraphy, 1925)
1940 - solid state devices completely forgotten and ‘rediscovered’ by
the literature survey
A brief look at the evolution of an
established technology
1924
1940
1953
SRC/File name/ 4
First disruptive technology
Vacuum tubes could not meet performance requirements
demanded by RADAR
1940 - Si, Ge diodes
as mixers/rectifiers in radars
‘reinvented’
•In 1948, the original
patent for the transistor
was issued
•Driver was size and
performance
•Within 10 years, solid
state devices had
overtaken vacuum tubes
1948 - 1st transistor
Moore’s Law and Silicon
Motivation:
→density
speed →
functionality →
• Moore’s law has been based on silicon
because it allows incremental changes in size
to produce integral improvements in
performance
SRC/File name/ 6
Approaching a “Red Brick Wall”
Challenges/Opportunities for Semiconductor R&D
Year of Production:
1999
2002
2005
2008
2011
2014
DRAM Half-Pitch [nm]:
180
130
100
70
50
35
Overlay Accuracy [nm]:
65
45
35
25
20
15
MPU Gate Length [nm]:
140
85-90
65
45
30-32
20-22
CD Control [nm]:
14
9
6
4
3
2
TOX (equivalent) [nm]:
1.9-2.5
1.5-1.9
1.0-1.5
0.8-1.2
0.6-0.8
0.5-0.6
Junction Depth [nm]:
42-70
25-43
20-33
16-26
11-19
8-13
Metal Cladding [nm]:
17
13
10
0
0
0
Inter-Metal Dielectric Κ:
3.5-4.0
2.7-3.5
1.6-2.2
1.5
*2001 ITRS roadmap
<1.5
<1.5
Which way to go?
Material Evolution in MOS
200
0’s
Al-Cu
90’
s
Al-Cu
W
Al-Cu
W
Cu
Al-Cu
W
Low K
ELK
Al-Si
Ti/TiN
Ti/TiN
Ti/TiN
Ti/TiN
Al
Poly
WSi2/Poly
TiSi2/Poly
TiSi2/Poly
CSi2/Poly
SiO2
SiO2
SiO2
SiO2
SiO2
SiO2/SiN
Silicon
Silicon
Silicon
Silicon
Silicon
Silicon
80’
70’
s
s
s
60’
Conventional structure+new materials
Perfection of existing planar
SiO2 based technology
New structure+conventional materials
Will continue until (δ cost) /(δ performance) > alternate technologies
SRC/File name/ 8
Limits of bulk CMOS?
• Will probably be after 2015
• Potential limiters are
• Lithography
• Device performance scaling
• Interconnect scaling
• Power dissipation
SRC/File name/ 9
Barriers Ahead to Current Roadmap:
LITHOGRAPHY IMPROVEMENTS
Cost of lithography tool ($M)
100
$100M litho tools
in ~3 generations
248
nm
10
next
generation
193
nm
i-line
Ix
1
Time
Scaling limits: Gate leakage and Short
Channel Effect
Short Channel
Tox equivalent (nm)
Long Channel
Gate Dielectric Scaling
(ITRS 1999)
2.4
1999
1.8
2001
2003
1.2
2005
0.6
2008
2011
0
2
4
6
8
Monolayers
12
Me
Me
Me
Gate leakage
SiO2
n++
n++
p-Si
Channel leakage
System performance vs.
device performance
100
Gate Delay
(Fan out 4)
Local
Relative Delay
(Scaled 50K Block Edge)
10
Global with Repeaters
(Scaled Die Edge)
Global w/o Repeaters
(Scaled Die Edge)
1
0.1
0.25
0.18
0.13
0.10
Process Technology Node (µ m)
0.07
0.05
0.035
Frequency will increase
Frequency (Mhz)
100000
30GHz
14GHz
6.5GHz
3 Ghz
10000
1000
100
10
486
P6
Pentium ® proc
386
8086 286
8080
8008
4004
8085
1
0.1
1970
1980
1990
Year
2000
2010
3 -- 30Ghz
30Ghz Frequency
Frequency
®
10
SRC/File name/ 13
Die size growth
Die size (mm)
100
10
8080
8008
4004
1
1970
8086
8085
1980
386
286
P6
Pentium
® proc
486
~7% growth per year
~2X growth in 10 years
1990
Year
2000
2010
Die
Die size
size grows
grows by
by 14%
14% every
every 22 years
years
®
5
SRC/File name/ 14
Following Moore’s Law...
10000
1.8B
Transistors (MT)
1000
900M
425M
200M
100
10
P6
Pentium
® proc
486
1
386
286
0.1
0.01
8086
8080
8008
4004
8085
0.001
1970
1980
1990
Year
2000
2010
200M--1.8B
200M--1.8B transistors
transistors on
on the
the Lead
Lead Microprocessor
Microprocessor
®
8
SRC/File name/ 15
Power density will increase
Power Density (W/cm2)
10000
1000
100
Rocket
Nozzle
Nuclear
Reactor
8086
10 4004
Hot Plate
P6
8008 8085
Pentium® proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Power
Power density
density too
too high
high to
to keep
keep junctions
junctions at
at low
low temp
temp
®
14
SRC/File name/ 16
Tech
Vectors
Emerging Technology Sequence
Defect
Tolerant
molecular
CNN
Quantum
computing
Architecture
QCA
3D
Integration
SET
RTD-FET
Magnetic RAM
RSFQ
QCA
Molecular
Logic
Phase Change
Nano FG
SET Mem
Molecular
Memory
Planar
dbl gate
Nonclassical
CMOS
FD SOI
Strained
Si
Vertical
TR
FinFET
Time
*2001 ITRS roadmap
SRC/File name/ 17
Device
Non-classical CMOS Devices
Source
Drain
Gate
Source
B O X
Band-engineered Tr
Ultra-Thin B ody
SOI
Concept
Fully depleted
SOI
Application/driver
Vertical Tr
Drain
Si
fin
-
Body!
FinFET
Double-Gate Tr
SiGe or Strained
Double-gate or surround-gate structure
[No specific temporal sequence for these 3 structures is intended]
Si channel; bulk
Si or SOI
Higher performance; Higher transistor density; Lower power dissipation
Maturity
Development
Advantages
- Improved
subthreshold
slope
-Vt controllability
better than PD
-Higher drive
current
- Compatible with
bulk and SOI
CMOS
- Higher drive
current
- Lithography
independent Lg
Scaling issues
- Si film thickness
- Gate stack
- Worse short
channel effect
than bulk CMOS
- High mobility
film thickness, in
case of SOI
- Gate stack
- Integration
Design challenges
- Device
characterization
- Compact model
and parameter
extraction
Near future
- Device
characterization
- Si film
- Gate alignment
thickness
- Si film thickness
- Gate stack
- Gate stack
- Integra bility
- Integra bility
-Process
- Process c omplexity
complexity
- TCAD including QM
- TCAD
effect
including QM
effect
- Device characterization
- PD vs. FD
- Compact model and parameter extraction
Timing
-Higher drive
current
-Improved
subthreshold
slope
- Improved short
channel effect
- Si film
thickness
- Gate stack
- Process
complexity
- TCAD
including QM
effect
-Higher drive current
-Improved
subthreshold slope
- Improved short
channel effect
- Stacked NAND
*2001 ITRS roadmap
SRC/File name/ 18
Emerging Research Logic Devices
Device
Resonant Tunneling
Diode – FET
Single Electron
Transistor
Rapid Single
Quantum Flux Logic
Quantum Cellular
Automata
Nanotube Devices
Molecular Devices
Maturity
Demonstrated
Demonstrated
Demonstrated
Demonstrated
Demonstrated
Demonstrated
Types
3-terminal
3-terminal
JJ + Inductance loop
-Electronic QCA
- Magnetic QCA
FET
2-terminal
3-terminal
Advantages
Density, Performance, RF
Density, Power,
Function
High Speed,
Potentially Robust,
(insensitive to timing
error)
High functional
Density, No
interconnects
Density, Power
Identity of individual
switches (e.g. Size,
Properties) on sub-nm
level. Potential
solution to
interconnect problem
Challenges
Matching of device
properties across wafer
New device & System.
Room temp operation
questionable. Noise
(offset charge). Lack
of drive current
Low Temperatures,
fabrication of complex,
dense circuitry
Limited fan out, low
tgemperature,
architecture
New device & system,
Difficult Route for
fabricatinjg complex
circuitry
Thermal &
environmental
stability: two terminal
devices: need for new
architectures
*2001 ITRS roadmap
SRC/File name/ 19
A Molecular Electronic Switch
(2-amino-4-ethyinylphenyl-4-ethylphenyl-5-nitro-1benzenethiolate)
Au
1000 Self Assembled
Molecules (SEM)
Current (pA)
Silicon Nitride
Au
IV Characteristics
1
1
(@T=60K)
0.00 0.50 1.00 1.50 2.00 2.50 3.00
Voltage (V)
Source: M.Reed & others,Yale Univ and Rice Univ
SRC/File name/ 20
Spin resonance devices for
quantum computation
R. Vrijen, E. Yablonovich, K. Wang et al. UCLA; D. DiVincenzo IBM, Phys. Rev. A 62
§Single electron/single nuclei manipulation
§Materials selection for QC
§Elimination of impurities with nonzero nuclear spin
§Non-traditional dopant impurities, e.g. S, Se, Te, Mg for Si.
§Alignment of the spin detector (e.g SET) to individual donor
§Precise positioning of dopant atoms (e.g. 10-20 nm from the interface)
SRC/File name/ 21
Nanotubes Exhibit Potential as Novel
Enabling Materials for Patterning, Metrology,
H. Dai et al./ Stanford, IBM
Value:
• Breakthrough materials technology with potential for enabling high
through put, maskless, direct write patterning;
• Creates a new class of robust probe tips for nanoscale metrology [w/ iSMT]
• Exhibits potential for nanoscale device applications.
Nanotube circuits recently
demonstrated
• P and N doping demonstrated
• Nanotubes used to construct a functioning inverter
circuit
Photos courtesy of IBM
SRC/File name/ 23
Emerging Research Memory Devices
Baseline 2002
Technologies
Storage
Mechanism
Device Types
Availability
Initial F Value
Cell size
Access time
Store time
Retention
E/W cycles
Maturity
General
Advantages
Challenges
Magnetic RAM
Phase
Change
Memory
Nano Floating
Gate Memory
Single/Few
Electron
Memories
Molecular Memory
Charged
Capacitor
DRAM
NOR
Flash
Magnetic
Tunnel
Junction
~2004
~2004
350 nm
130 nm
~40F2
20 to 40F2
4.9 µm2
0.68 µm2
2T
1T
<25 ns
<10 ns
<25 ns
<10 ns
>10 yrs
>10 yrs
>1E15
>1E13
development
PseudoSpin-Valve
2002
130 nm
150 nm
8F2
10F2
0.14 µm2 0.19 µm2
1T
1T
<20 ns
~80 ns
<20 ns
~1 ms
64 ms
>10 yrs
>1E5
∞
production
Density
Economy
Scaling
Nonvolatile
Scaling
OUM
-Engineered
Barrier
-PLED
SET
-Nanocrystal
~2004
100 nm
~6F2
0.06 µm2
1T
<100 ns
<100 ns
>10 yrs
>1E13
development
Nonvolatile, High
endurance, Fast read &
write, Rad Hard, NDRO
Nonvolatile,
Low Power,
NDRO
Rad Hard
Integration issues,
Material Quality, Control
magnetic properties for
write operations
New
materials &
integration
-Bistable switch
-Molecular NEMS
-Spin based molecular
devices
>2005
80 nm
4 to 10F2
0.04 µm2
>2007
65 nm
4 to 9F2
~0.04 µm2
>2010
45 nm
~2F2
~0.004 µm2
<10 ns
<10 ns
> 10 yrs
>1E6
demonstrated
<10 ns
<100 ns
Sec to minutes
>1E9
demonstrated
~10 ns
~10 ns
Days
>1E15
demonstrated
Nonvolatile,
Fast read &
write
Density
Power
Density, Power
Identical switches
large 1/0 difference
Opportunities for 3D
Easier to interconnect
Defect tolerant circuitry
Material
Quality
Dimension
control (Room
temp operation),
Background
charge
Volatile
Thermal stability
*2001 ITRS roadmap
SRC/File name/ 24
Magnetic RAM (MRAM)
NiFe
NiFe
Read
Memory storage
NiFe
Cu
Memory storage
GMR MRAM
Al2O3
Read
NiFe
MTJ MRAM
u MRAMs are based on two magnetoresistive effects: giant
magnetoresistance (GMR) and tunneling
magnetoresistance in magnetic tunnel junctions (MTJ)
u Data are stored by applying magnetic fields, and are read
by measuring resistance changes. The magnetic fields
are created by passing currents nearby or through the
magnetic structure.
SRC/File name/ 25
Tyler Lowrey, Energy Conversion Devices, Inc., http://www.ovonic.com
SRC/File name/ 26
Nanofloating gate memory
•Engineered tunnel barrier
•Nanocrystal
memory
node
gate
Gate
Engineered barrier
nanocrystals
s
SiO2
SiO2
gate
memory node
n+
gate
n+
Si
source
drain
Si channel
Si channel
Advantages: High speed
Challenges: Materials quality
Research needs: Chemistry and physics of
Interfaces; Non-lithographic patterning
SRC/File name/ 27
Single electron memory
Single electron transistor(SET)
•Electron movements are controlled with single electron precision
•Coulomb blockade effect
island
source
gate
drain
Advantages: high density, low power
Challenges: low operating temperature of 4.2-20 K
Research needs:
nanoelectronic devices, nonlithographic patterning
SRC/File name/ 28
Molecular Memory
u Using individual molecules as building block of memory cells
u Data are stored by applying external voltage that cause the
Current (pA)
transition of the molecule into one of two possible phase states.
Reading data is performed by measuring resistance changes in
the molecular cell
u It is possible to combine molecular components with existing
technology e.g. DRAM and floating gate memory
IV Characteristics
1
1
0.00 0.50 1.00 1.50 2.00 2.50 3.00
Voltage (V)
Source: M.Reed & others,Yale Univ and Rice
SRC/FileUniv
name/ 29
Emerging Research Architectures*
Architecture
Molecular
architecture
Defect
Tolerant
architecture
N2
O
H2
N
3-D Integration
Device
Implementation
CMOS with
dissimilar material
systems
Advantages
Less interconnect
delay
Enables mixed
technology solutions
Heat removal
No design tools
Difficult test and
measurement
Issues
Maturity
Demonstration
Quantum Cellular
Automata
Quantum Dots
Many self
assembled
nanodevices
Molecular
switches and
memories
High functional
density
No interconnects
Supports
imperfect
hardware
Supports
memory
based
computing
Limited fan out
Low temperatures
Requires precomputing test
Demonstration
Demonstration
Cellular Nonlinear
networks
Single electron array
architectures
Quantum Computing
Spin resonance transistors,
NMR devices
Single flux quantum devices
Exponential performance
scaling, enables unbreakable
cryptography
Limited
functionality
Enables utilization of
single electron devices
at room temperature,
memory based
computing
Subject to background
noise, tight tolerances
Concept
Concept
Concept
Extreme application
limitation, extreme
technology requirement s
*2001 ITRS roadmap
SRC/File name/ 30
Quantum Cellular Automata
CSR 1999 proposal on
Quantum Cellular Automata
(U. Notre Dame) was
continued in 2000 as a
Custom Funded Project with
Intel in circuit design
SRC/File name/ 31
Defect tolerant architecture
•
•
•
•
All-memory architecture
Defect tolerant
Potentially self-repairing and reconfigurable
3D
J. Heath, R. S. Williams
et al, UCLA and HP
• Success factor: Post manufacturing
testing/mapping processing. Test Challenge
SRC/File name/ 32
Quantum Computer architecture
A-Gate
J-Gate
- - -
A-Gate
+++
Barrier layer
28Si
31P
Selected technological
implementations
•Liquid-state NMR
•Linear ion trap
e31 P
•Coupled quantum dots
•Deterministically doped
semiconductor structures
SRC/File name/ 33
Nanotechnology for assisted
assembly
•Chemical self assembly
•DNA templating
•Collodial self assembly
•Hydrophilic and
hydrophobic structures
SRC/File name/ 34
Transistors as Small as DNA exist today*
30nm
10nm Gold particle attached to Z-DNA
Antibody [John Jackson & Inman. Gene
1989 84 221-226]
*Intel, 2000, 2001
20nm
SRC/File name/ 35
SRC/File name/ 36
Conclusions
1. Silicon based CMOS will be a major part of
microelectronics for the foreseeable future
2. Continued scaling along Moore’s Law will
continue on planar bluk CMOS for at least
15 years
3. Performance scaling beyond that will occur
by integrating novel information processing
devices on to silicon platforms
SRC/File name/ 37
Backup
SRC/File name/ 38
How did industry stay on Moore’s
law for 40 years?
• Scaling down device dimensions
and
• Introducing new materials
and
• Introducing improved processes
and
• Introducing improved geometries
SRC/File name/ 39
Material Evolution in MOS
’s
0
0
20
Al-Cu
90’
s
Al-Cu
W
Al-Cu
W
Cu
Al-Cu
W
Low K
ELK
Al-Si
Ti/TiN
Ti/TiN
Ti/TiN
Ti/TiN
Al
Poly
WSi2/Poly
TiSi2/Poly TiSi2/Poly
CSi2/Poly
SiO2
SiO2
SiO2
SiO2
SiO2
SiO2/SiN
Silicon
Silicon
Silicon
Silicon
Silicon
Silicon
80’
70’
60’
s
s
s
New Silicon Process Technologies for NonBulk CMOS
• Patterned epitaxial silicon growth
• Selective epitaxial growth
• (Vertical) Epitaxial lateral overgrowth (ELO &
VELO)
• Tunnel epitaxial growth
• Low temperature wafer bonding
• Silicon layer detachment using hydrogen implants
• Critical feature size definition by layer deposition
SRC/File name/ 41
Emerging Nanoscale Semiconductor
Physics Phenomena
1. √N effect
2. Single dopant effects
3. Surface /Interface dominance;
Interface-to interface interactions
4. Single particle transport phenomena
5. Tunneling
6. Quantum confinement
7. Single electron effects
SRC/File name/ 42
Devices will soon be on the
“molecular” or “atomistic” scale
1.00E+27
Atoms per Bit
1.00E+24
IC and Bio-based device
converge
ICdensity
and bio-based
device
densities converge
Molecular
Molecular
devices
Devices
1.00E+21
1.00E+18
1.00E+15
1.00E+12
1.00E+09
1.00E+06
1.00E+03
1.00E+00
-60
-50
-40
-30
-20
-10
0
Years from 2000
10
20
30
40
The √ N Rule of Physics
The physical parameters P of a system are inaccurate
within a probable relative error ∆P/P of the order
of n, where n is the number of atoms in a system
D, nm
1
2
3
4
5
6
7
8
9
10
n
26
209
707
1675
3271
5652
8975
13397
19076
261677
∆P, %
19.6
6.9
3.8
2.4
1.7
1.3
1.1
0.9
0.7
0.6
D
band gap
dielectric constant
conductivity
mobility
activation energy
etc
SRC/File name/ 44
fraction of surface atoms,
%
Everything's an interface
100
80
We are here
60
40
20
0
1
10
100
size, nm
1000
Under conditions of
surface dominance,
device properties depend
on the shape, geometry and
surface termination of the
nanostructure
STEM and EELS Analysis of
Si/SiOx Ny/Ta2O5/TiN/Al Gate Structure
(Wafer ID: NTA 300)
1.2
I1
Si
1
I2 I3
I4
L1 L2 L3
L4
I5
__
ADF (inverted)
0.8
0.6
0.4
O profile
N profile
Ti profile
Si profile
Al profile
0.2
Al
0
5
10
15
20
25
Position (nm)
SRC MPS 2000 Strategic Plan: DRAFT #2
D. Meyer[NCSU] and J. Silcox [Cornell] 2000
SRC/File name/ 45