Download Standards Project - Telecommunications Industry Association

Telecommunications Industry Association
TR41.9-13-05-006
Document Cover Sheet
Project Number
PN-3-4124 (Part 68 FAQs)
Document Title
ADSL Modem DC Resistance Requirement
Source
Cisco Systems
Contact
Tim Lawler
170 West Tasman Dr.
San Jose, CA 95134
Distribution
TR-41.9
Intended Purpose
of Document
(Select one)
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Phone: (408) 527-0681
Fax: (408) 853-3288
Email: [email protected]
For Incorporation Into TIA Publication
For Information
Other (describe) -
The document to which this cover statement is attached is submitted to a Formulating Group or
sub-element thereof of the Telecommunications Industry Association (TIA) in accordance with the
provisions of Sections 6.4.1–6.4.6 inclusive of the TIA Engineering Manual dated October 2009, all
of which provisions are hereby incorporated by reference.
Abstract
This contribution deals with a question that was referred from ACTA through Brian Scarpelli at TIA to
Steve Whitesell. The issue deals with measurement of on hook resistance for an ADSL modem. Based
on the email exchange that Steve Whitesell had with Sophia Li of BaclCorp (Bay Area Compliance
Laboratories), it appears the modem has some internally generated fluctuating low level signal (~1.2 V
and 3 µA) on its tip and ring port that is causing difficulty with the on-hook dc resistance measurements.
The question is whether it should be judged to fail the resistance requirements.
v1.0 – 20050426
Telecommunications Industry Association
TR41.9-13-05-006
An ADSL over POTS interface should not have any voltage at its tip & ring leads. Typically an ADSL
over POTS interface will have either a capacitor between the transformer windings towards the tip & ring
leads or two blocking capacitors, one in series between the tip lead and the transformer and one in series
between the ring lead and the transformer. This would block any DC coming in or going out the interface.
Having a voltage at tip & ring would cause the interface to fail the DC Resistance test.
Also if this interface does have capacitors to block DC, then the ADSL chip may not be shut down or in
the "quiet state". If the ADSL chip is not in the quiet state, then it will be sending training tones in the
band between 25 kHz to 138 kHz. These tones can also cause the interface to fail the on-hook impedance
tests. The ADSL over POTS interface needs to be in the "quiet state" when preforming all of the on-hook
impedance and Transverse Balance tests.
The low level signal on the tip and ring leads that is causing problems with the dc resistance
measurements may actually be the high frequency training tones.
I recommend that this issue be added to the Part 68 FAQs.
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