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Assembly Language for x86 Processors
Section 3
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What's Next
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•
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Internal microprocessor architecture
Registers
Assembly Language introduction
Assembly instructions
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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INTERNAL MICROPROCESSOR
ARCHITECTURE
• Before a program is written or instruction investigated,
internal configuration of the microprocessor must be
known.
• In a multiple core microprocessor each core contains
the same programming model.
• Each core runs a separate task or thread
simultaneously.
A thread consists of a program counter, a register set,
and a stack space.
A task shares with peer threads its code section, data
section, and operating system resources of your written
code will be described in the execution cycle
What stack space is!!
When a program starts executing, a certain contiguous section of
memory is set aside for the program called the stack.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Program Template
TITLE Program Template
;
;
;
;
;
(Template.asm)
Program Description:
Author:
Creation Date:
Revisions:
Date:
Modified by:
INCLUDE Irvine32.inc
.data
; (insert variables here)
.code
main PROC
; (insert executable instructions here)
exit
main ENDP
; (insert additional procedures here)
END main
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2007.
OS resources
Data section
Code section
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The Programming Model
• 8086 through Core2 considered program visible.
• registers are used during programming and are specified by the
instructions
• Other registers considered to be program invisible.
• not addressable directly during applications programming
• 80286 and above contain program-invisible registers to
control and operate protected memory.
• and other features of the microprocessor
What's Next
•
•
•
•
Internal processor architecture
Registers
Assembly Language introduction
Assembly instructions
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Basic Microcomputer Design
• Why we need registers!!! 
• clock synchronizes CPU
operations
• control unit (CU) coordinates
sequence of execution steps
• ALU performs arithmetic and
bitwise processing
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
data bus
registers
Central Processor Unit
(CPU)
ALU
CU
Memory Storage
Unit
I/O
Device
#1
I/O
Device
#2
clock
control bus
address bus
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General-Purpose Registers
Named storage locations inside the CPU, optimized for
speed.
32-bit General-Purpose Registers
EAX
EBP
EBX
ESP
ECX
ESI
EDX
EDI
16-bit Segment Registers
EFLAGS
EIP
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
CS
ES
SS
FS
DS
GS
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Accessing Parts of Registers
• Use 8-bit name, 16-bit name, or 32-bit name
• Applies to EAX, EBX, ECX, and EDX
8
8
AH
AL
AX
EAX
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
8 bits + 8 bits
16 bits
32 bits
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Index and Base Registers
• Some registers have only a 16-bit name for their
lower half:
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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programming model 8086 through Core2
microprocessor (1/5)
1. Multipurpose
Registers
including the 64-bit extensions
• RAX - a 64-bit register
(EAX), a 32-bit register
(accumulator) ,(AX) 16-bit
register (AX), or as either
of two 8-bit registers (AH
and AL).
• The accumulator is used
for instructions such as
multiplication, division, and
some of the adjustment
instructions.
programming model 8086 through Core2
microprocessor (2/5)
• RBX, addressable as RBX, EBX, BX, BH, BL.
• BX register (base index) sometimes holds offset address of a
location in the memory system in all versions of the
microprocessor
• RCX, as RCX, ECX, CX, CH, or CL.
• a (count) general-purpose register that also holds the count for
various instructions is used in looping
• RDX, as RDX, EDX, DX, DH, or DL.
• a (data) general-purpose register
• holds a part of the result from a multiplication
or part of dividend before a division
programming model 8086 through Core2
microprocessor (3/5)
Register Organization of 8086
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
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programming model 8086 through Core2
microprocessor (4/5)
• RBP, as RBP, EBP, or BP.
• points to a memory (base pointer) location
for memory data transfers
• RDI addressable as RDI, EDI, or DI.
• often addresses (destination index) string destination data for
the string instructions
• RSI used as RSI, ESI, or SI.
• the (source index) register addresses source string data for
the string instructions
• like RDI, RSI also functions as a generalpurpose register
programming model 8086 through Core2
microprocessor (5/5)
segment registers & special purpose registers
• Segment registers to address memory space
CS - points at the segment containing the current program code.
DS - generally points at segment where variables are defined.
ES - extra segment register, it's up to a coder to define its usage
(used by some string instructions to hold destination data).
SS - points at the segment containing the stack of memory
specified for the program/thread.
GS and FS - general purpose segments (for access by the
program)
•
special purpose registers
flags register - determines the current state of the
microprocessor.
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
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Status Flags (later)
• Carry
• unsigned arithmetic out of range
• Overflow
• signed arithmetic out of range
• Sign
• result is negative
• Zero
• result is zero
• Auxiliary Carry
• carry from bit 3 to bit 4
• Parity
• sum of 1 bits is an even number
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Floating-Point, MMX, XMM Registers
(later)
80-bit Data Registers
• Eight 80-bit floating-point data registers
ST(0)
• ST(0), ST(1), . . . , ST(7)
ST(1)
• arranged in a stack
ST(2)
• used for all floating-point
arithmetic
• Eight 64-bit MMX registers
• Eight 128-bit XMM registers for singleinstruction multiple-data (SIMD) operations
ST(3)
ST(4)
ST(5)
ST(6)
ST(7)
Opcode Register
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Summary of registers
• General-Purpose
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EAX – accumulator
ECX – loop counter
ESP – stack pointer
ESI, EDI – index registers
EBP – extended frame pointer (stack)
• Segment
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CS – code segment
DS – data segment
SS – stack segment
ES, FS, GS - additional segments
• EIP – instruction pointer
• EFLAGS
• status and control flags
• each flag is a single binary bit
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What's Next
•
•
•
•
Internal processor architecture
Registers
Assembly Language introduction
Assembly instructions
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Basic Elements of Assembly Language
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Integer constants
Integer expressions
Character and string constants
Reserved words and identifiers (later)
Directives and instructions (later)
Instruction format
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2007.
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Integer Constants
• Optional leading + or – sign
• binary, decimal, hexadecimal, or octal digits
• Common radix characters:
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h – hexadecimal
d – decimal
b – binary
r – encoded real
Examples: 30d, 6Ah, 42, 1101b
Hexadecimal beginning with letter: 0A5h
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2007.
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Integer Expressions
• Operators and precedence levels:
• Examples:
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2007.
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Character and String Constants
• Enclose character in single or double quotes
• 'A', "x"
• ASCII character = 1 byte
• Enclose strings in single or double quotes
• "ABC"
• 'xyz'
• Each character occupies a single byte
• Embedded quotes:
• 'Say "Goodnight," Gracie'
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2007.
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Instructions
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Assembled into machine code by assembler
Executed at runtime by the CPU
We use the Intel IA-32 instruction set
An instruction contains:
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Label
Mnemonic
Operand
Comment
(optional)
(required)
(depends on the instruction)
(optional)
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2007.
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Labels
• Act as place markers
• marks the address (offset) of code and data
• Follow identifer rules
• Data label
(when used in data area of program)
• must be unique within the source code file
• example: myArray
(not followed by colon)
• Code label
• target of jump and loop instructions
• example: L1:
(followed by colon)
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2007.
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Mnemonics and Operands
• Instruction Mnemonics
• memory aid
• examples: MOV, ADD, SUB, MUL, INC, DEC
• Operands
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constant
constant expression
register
memory (data label)
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2007.
Immediate values
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Comments
• Comments are good!
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explain the program's purpose
when it was written, and by whom
revision information
tricky coding techniques
application-specific explanations
• Single-line comments
• begin with semicolon (;)
• Multi-line comments
• begin with COMMENT directive and a programmerchosen character
• end with the same programmer-chosen character
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2007.
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What's Next
•
•
•
•
Internal processor architecture
Registers
Assembly Language introduction
Assembly instructions
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Instruction Set
• 80186 instruction set consists of the following
instructions:
• Data moving instructions.
• Arithmetic - add, subtract, increment, decrement,
convert byte/word and compare.
• Logic - AND, OR, exclusive OR, shift/rotate and test.
• String manipulation - load, store, move, compare and
scan for byte/word.
• Control transfer - conditional, unconditional, call
subroutine and return from subroutine.
• Input/Output instructions.
• Other - setting/clearing flag bits, stack operations,
software interrupts, etc
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
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MOV Instruction
• Move from source to destination. Syntax:
MOV destination, source
• Both operands must be the same size
• No more than one memory operand permitted
• CS, EIP, and IP cannot be the destination
• No immediate to segment moves
• No immediate as a destination
mov al,wVal
mov ax,count
mov eax,count
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
; error
; error
; error
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MOV Instruction
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
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MOV Instruction
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
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Your turn . . .
Explain why each of the following MOV statements are invalid:
..code
mov
mov
mov
mov
immediate move to DS not permitted nut
you could create label in thid memory
ds,45
segment
eip,dVal EIP cannot be the destination
25,bVal immediate value cannot be destination
bVal2,bVal memory-to-memory move not permitted
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
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Zero Extension
The destination must be a register.
When you copy a smaller value into a larger destination, the
MOVZX instruction fills (extends) the upper half of the destination
with zeros.
0
10001111
Source
00000000
10001111
Destination
mov bl,10001111b
movzx ax,bl
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
; zero-extension
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Zero Extension
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
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Sign Extension
The MOVSX instruction fills the upper half of the destination
with a copy of the source operand's sign bit.
11111111
10001111
Source
10001111
Destination
mov bl,10001111b
movsx ax,bl
; sign extension
The destination must be a register.
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
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XCHG Instruction
XCHG exchanges the values of two operands.
• At least one operand must be a register.
• No immediate operands are permitted.
• Two operands must have the same size
.data
var1 WORD 1000h
var2 WORD 2000h
.code
xchg ax,bx
xchg ah,al
xchg var1,bx
xchg eax,ebx
;
;
;
;
xchg var1,var2
; error: two memory operands
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
exchange
exchange
exchange
exchange
16-bit regs
8-bit regs
mem, reg
32-bit regs
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Arithmetic operations
Addition and Subtraction
• INC and DEC Instructions
• ADD and SUB Instructions
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
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INC and DEC Instructions
• Add 1, subtract 1 from destination operand
• operand may be register or memory
• INC destination
• Logic: destination  destination + 1
• DEC destination
• Logic: destination  destination – 1
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
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INC and DEC Examples
.data
myWord WORD 1000h
myDword DWORD 10000000h
.code
inc myWord
dec myWord
inc myDword
mov
inc
mov
inc
ax,00FFh
ax
ax,00FFh
al
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
; 1001h
; 1000h
; 10000001h
; AX = 0100h
; AX = 0000h
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ADD and SUB Instructions
• ADD destination, source
• Logic: destination  destination + source
• SUB destination, source
• Logic: destination  destination – source
• Same operand rules as for the MOV
instruction
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
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ADD and SUB Examples
.data
var1 DWORD 10000h
var2 DWORD 20000h
.code
mov eax,var1
add eax,var2
add ax,0FFFFh
add eax,1
sub ax,1
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
;
;
;
;
;
;
---EAX--00010000h
00030000h
0003FFFFh
00040000h
0004FFFFh
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Lets look at this example
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
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42 69 6E 61 72 79
What does this say?
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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