Download Saving and Restoring Registers

More MIPS
CICS 515: Part 1
Summer 2003
Modified from © Morgan Kauffman Pub.
1
Procedures (Subroutines) in Assembly:
Steps to call a procedure in MIPS (other processors slightly different):
1. Put input parameters in registers $a0 to $a3
2. Store address of current instruction + 4 (this is called the “return
address”) in register $ra and jump to subroutine
Can do this using the MIPS instruction:
jal ProcedureAddress
This puts the address of current instruction +4 into register $ra
and branches (unconditionally) to ProcedureAddress
Modified from © Morgan Kauffman Pub.
2
Saving and Restoring Registers:
3. The Subroutine executes, and computes its results
4. Return values are placed in registers $v0 and $v1
5. Jump back to instruction following the instruction that called the
procedure
To do this: use the instruction
jr $ra
(recall: $ra contains the return address)
Modified from © Morgan Kauffman Pub.
3
Procedures (Subroutines) in Assembly:
If we are going to use any registers within the procedure, we want to
- Save what is in these registers at the start of the procedure
- Restore these values at the end of the procedure
To do this, we use a stack.
A stack is a FIRST-IN LAST-OUT list.
- you PUSH items onto a stack
- you POP items off a stack
4
Modified from © Morgan Kauffman Pub.
Stacks:
In MIPS, stack is stored in memory
Register $SP contains the most recently pushed item on the stack
Stack grows downward in memory
10011
10011
10010
10010
10009
10009
$SP
10008
10008
10007
10007
10006
10006
10005
10004
10003
10002
Push 32 bit word
10005
(4 bytes) onto
10003
10001
$SP
10004
10002
10001
stack
Before
After
5
Modified from © Morgan Kauffman Pub.
Stacks continued...
Push another
32 bit word
10011
(4 bytes) onto
10010
10009
stack
10008
10007
10011
10010
10009
10008
10007
10006
10006
10005
$SP
10004
10005
10004
10003
10003
10002
10002
10001
10001
Before
$SP
After
Modified from © Morgan Kauffman Pub.
6
Stacks continued...
Pop a
32 bit word
10011
10011
10010
(4 bytes) from
10010
stack
10008
10009
10009
10008
10007
10007
10006
10006
10005
10005
10004
10004
10003
10003
10002
10002
10001
$SP
10001
$SP
Before
After
Modified from © Morgan Kauffman Pub.
7
Stacks continued...
Pop another
32 bit word
10011
10011
(4 bytes) from
10010
10009
stack
10008
10007
10010
10009
$SP
10008
10007
10006
10006
10005
10005
$SP
10004
10004
10003
10003
10002
10002
10001
10001
Before
After
Modified from © Morgan Kauffman Pub.
8
Stacks in MIPS:
To push $t1 onto the stack:
subi $sp, $sp, 4
sw $t1, 0($sp)
-- subtract 4 from SP (make room on stack)
To pop $t1 from stack later:
lw $t1, 0($sp)
addi $sp, $sp, 4
Exercise: Go through previous examples and make sure you know why these
instructions do what I say they do.
Modified from © Morgan Kauffman Pub.
9
Example:
Here is the C code:
int steve_was_here (int g, int h, int i, int j)
{
int f;
f = (g+h) - (i+j);
return(f);
}
Exercise: Write this in assembly code
Modified from © Morgan Kauffman Pub.
10
Example:
Your answer might look something like this:
steve_was_here:
subi $sp, $sp, 12
sw $t1, 8($sp)
sw $t0, 4($sp)
sw $s0,0($sp)
add $t0, $a0, $a1
add $t1, $a2, $a3
sub $s0, $t0, $t1
-- save t1, t0 and s0 since we are going to use
-- them in this procedure
-- main body of routine
Continued on next slide...
Modified from © Morgan Kauffman Pub.
11
Modified from © Morgan Kauffman Pub.
12
Example:
lw $s0, 0($sp)
lw $t0, 4($sp)
lw $t1, 8($sp)
add $sp, $sp, 12
-- restore registers
jr $ra
-- jump back to caller
Alternative Architectures
•
Design alternative:
– provide more powerful operations
– goal is to reduce number of instructions executed
– danger is a slower cycle time and/or a higher CPI
•
Sometimes referred to as “RISC vs. CISC”
– VAX: minimize code size, make assembly language easy
instructions from 1 to 54 bytes long!
•
We’ll look at PowerPC and 80x86
Modified from © Morgan Kauffman Pub.
13
PowerPC
•
Indexed addressing
– example:
lw $t1,$a0+$s3
#$t1=Memory[$a0+$s3]
– What do we have to do in MIPS?
•
•
Update addressing
– update a register as part of load (for marching through arrays)
– example: lwu $t0,4($s3) #$t0=Memory[$s3+4];$s3=$s3+4
– What do we have to do in MIPS?
Others:
– load multiple/store multiple
– a special counter register “bc Loop”
decrement counter, if not 0 goto loop
Modified from © Morgan Kauffman Pub.
14
80x86
•
•
•
•
•
•
1978: The Intel 8086 is announced (16 bit architecture)
1980: The 8087 floating point coprocessor is added
1982: The 80286 increases address space to 24 bits, +instructions
1985: The 80386 extends to 32 bits, new addressing modes
1989-1995: The 80486, Pentium, Pentium Pro add a few instructions
(mostly designed for higher performance)
1997: MMX is added
“This history illustrates the impact of the “golden handcuffs” of compatibility
“adding new features as someone might add clothing to a packed bag”
“an architecture that is difficult to explain and impossible to love”
Modified from © Morgan Kauffman Pub.
15
A dominant architecture: 80x86
•
•
Lots of books you can look at for more details
Complexity:
– Instructions from 1 to 17 bytes long
– one operand must act as both a source and destination
– one operand can come from memory
– complex addressing modes
e.g., “base or scaled index with 8 or 32 bit displacement”
Saving grace:
– the most frequently used instructions are not too difficult to build
– compilers avoid the portions of the architecture that are slow
•
“what the 80x86 lacks in style is made up in quantity,
making it beautiful from the right perspective”
Modified from © Morgan Kauffman Pub.
16
Pentium Bug Time line
•
•
•
•
•
June 1994: Intel discovers bug in Pentium: takes months to make
change, reverify, put into production: plans good chips in January
1995 - 4 to 5 million Pentiums produced with bug
Scientist suspects errors and posts on Internet in September 1994
Nov. 22 Intel Press release: “Can make errors in 9th digit ... Most
engineers and financial analysts need only 4 of 5 digits. Theoretical
mathematician should be concerned. ... So far only heard from
one.”
Intel claims happens once in 27,000 years for typical spread sheet
user:
– 1000 divides/day x error rate assuming numbers random
Dec 12: IBM claims happens once per 24 days: Bans Pentium sales
– 5000 divides/second x 15 minutes = 4,200,000 divides/day
– Intel said it regards IBM's decision to halt shipments of its
Pentium processor-based systems as unwarranted.
Modified from © Morgan Kauffman Pub.
17
Pentium jokes
•
Q: How many Pentium designers does it take to screw in a light bulb?
A: 1.99904274017, but that's close enough for non-technical people.
– Top Ten New INTEL Slogans For The Pentium
9.9999973251
8.9999163362
7.9999414610
6.9999831538
5.9999835137
4.9999999021
3.9998245917
2.9991523619
1.9999103517
0.9999999998
It's a FLAW, Dammit, not a Bug
It's Close Enough, We Say So
Nearly 300 Correct Opcodes
You Don't Need to Know What's Inside
Redefining the PC -- and Mathematics As Well
We Fixed It, Really
Division Considered Harmful
Why Do You Think They Call It *Floating*
Point?
We're Looking for a Few Good Flaws
The Errata Inside
Modified from © Morgan Kauffman Pub.
18
Dec. 21, 1994 $500M write-off
“To owners of Pentium processor-based computers and the PC community:
We at Intel wish to sincerely apologize for our handling of the recently
publicized Pentium processor flaw.
The Intel Inside symbol means that your computer has a microprocessor
second to none in quality and performance. Thousands of Intel employees work
very hard to ensure that this is true. But no microprocessor is ever perfect.
What Intel continues to believe is technically an extremely minor problem has
taken on a life of its own. Although Intel firmly stands behind the quality of the
current version of the Pentium processor, we recognize that many users have
concerns.
We want to resolve these concerns.
Intel will exchange the current version of the Pentium processor for an
updated version, in which this floating-point divide flaw is corrected, for
any owner who requests it, free of charge anytime during the life of their
computer. Just call 1-800-628-8686.”
Sincerely,
Andrew S. Grove
President /CEO
Craig R. Barrett
Gordon E. Moore
Executive Vice President Chairman of the Board
&COO
Modified from © Morgan Kauffman Pub.
19