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Synchronous Buck Converter Design for Digital Circuits
Yang wang
ECE 632 – Fall 2008
University of Virginia
[email protected]
ABSTRACT
In this paper, a synchronous buck DC-DC converter is developed
for sub-threshold operation of digitals circuits.
Constant
frequency pulse width modulation (PWM) switching has poor
light load efficiencies because of higher switching losses. Pulse
frequency modulation (PFM) control mode is more efficient at
light load. This paper presents the design and prototype results of
a 0.3–1.25V CMOS PFM buck DC-DC converter. And the largest
output voltage ripple is 24mV. The proposed control scheme
provides an accurate output voltage compare to reference voltage.
intersective method, which requires only a sawtooth or a triangle
waveform (easily generated using a simple oscillator) and a
comparator. When the value of the reference signal (the green sine
wave in figure 2) is more than the modulation waveform (blue),
the PWM signal (magenta) is in the high state 1, otherwise it is in
the low state 0.[3][4][5]
1. INTRODUCTION
The problem is always come out from the portable electrical
device, like mobile phone, PDA, small laptop and etc. These
equipments always have a wireless connection and some security
data transmission. So the power supplies to these devices are
critical parts. It should be reliable, powerful, accuracy and the size
is small enough. The energy efficiency of digital circuits continues
to be a major factor in determining the size and weight of battery
operated electronics. In present, Sub-threshold operation is a
technique which the circuits are operated at a VDD below the
threshold voltage of its device. MEP is a minimum energy point,
defined as the operating voltage at which the sum of switching
energy and leakage energy is lowest. However, the MEP of a
digital circuit is changing with inner and exterior environments,
so, to track the MEP point and deliver an adjustable voltage by a
DC-DC converter is significant. [1][2]
The buck converter shown in figure 1 is the most widely used
DC-DC converter topology in power management and
microprocessor voltage-regulator applications. Those applications
require fast load and line transient responses and high efficiency
over a wide load current range. They can convert a voltage source
into a lower regulated voltage.
Fig.1 Synchronous buck converter topology
For buck DC-DC converters, there are two operation modes,
One is PWM and the other is PFM. Pulse-width modulation
(PWM) of a signal or power source involves the modulation of its
duty cycle to control the amount of power sent to a load. Pulsewidth modulation uses a square wave whose pulse width is
modulated resulting in the variation of the average value of the
waveform. The simplest way to generate a PWM signal is the
Fig. 2 PWM operation mode
Pulse-Frequency Modulation (PFM) is a modulation method
for representing an analog signal using only digital levels (1 and
0). It is analogous to pulse-width modulation (PWM), as the
magnitude of an analog signal is encoded in the duty cycle of a
square wave. Unlike PWM, in which the width of square pulses is
varied at constant frequency, PFM is accomplished using fixedduration pulses and varying the repetition rate thereof.
For PWM operation, losses of a synchronous buck converter
can be grouped into two categories, dc losses and ac losses. The
dc losses are determined mainly by on-resistance (RDSON) in the
low-side and high-side MOSFETs, and by the series dc resistance
(DCR) of the inductor. The ac losses consist mainly of switching
losses, gate-drive losses of both FETs and dead-time losses. The
ac losses are proportional to the MOSFET switching frequency.
There are different approaches to improve the operating efficiency
for different load ranges. Normally, dc losses dominate at heavy
load, so lowering RDSON and DCR would effectively improve
efficiency at heavy loads. However, at light loads, conduction
losses become insignificant as the ac losses dominate, so
decreasing the switching frequency effectively improves
efficiency. Figure 3 shows the optimum transition point between
PWM and PFM modes in the figure 1 circuit is a function of input
voltage and load current. So, PFM is a better choice during the
light load. [6]
Fig.4 Steady-state PFM waveforms
Calculation for inductor
To support a maximum load current, Io(max):
Fig.3 The optimum transition point between PWM and PFM
modes in the Fig. 1 circuit is a function of input voltage and load
current.
Motivated by the concerns above, a high efficiency, low power
DC-DC converter that can delivery supply voltage from 0.3V to
1.25V with PFM mode is proposed in this paper.
2. System Design Considerations
2.1 Basic Converter Operation
Figure 4 shows the steady-state buck circuit waveforms under
PFM control. When the output voltage is lower than VREF, a burst
of charge is delivered, returning VOUT to a value above VREF. This
charge burst is delivered with high energy efficiency through the
inductor as follows: The PMOS device is turned on for a time
interval, Tpmos. Some of the energy removed from the input is
delivered to the output; the rest is stored in the inductor. During
this interval, the inductor current slews at a rate of:
(2)
The NMOS device is turned off when iLf decays to zero. At this
time, the circuit will idle with zero inductor current and the output
capacitor sourcing the load current.
The capacitor is selected to ensure that the peak-to-peak output
voltage ripple, ΔV, is maintained to a certain percentage of VOUT.
The worst-case output voltage ripple is calculated assuming that
all of the charge delivered through the inductor is absorbed by Cf:
(4)
2.2 PFM Controller
Figure 5 shows the detailed schematic of the PFM controller.
Output Voltage
Comparator 1
Vout
Vref
S
Delay
300ns
R
Zero inductor current
Comparator 2
S
+ -
And the current reaches its peak value of iLf = Ip at the conclusion
of the PMOS conduction interval. The PMOS device is then
turned off, and after a short dead-time, the NMOS device is turned
on to pick up the inductor current. During NMOS conduction,
the energy stored in the inductor is released to the output. The
inductor current slews from Ip to 0 at a rate of:
Calculation for capacitor
+ -
(1)
(3)
R
SET
CLR
SET
CLR
Q
PMOS
Q
Q
NMOS
Q
Fig. 5 PFM controller block diagram
When feedback voltage VFB, which is derived from the output
voltage, decreases below reference voltage VREF, comparator
COMP1’s output transitions from low to high. This event triggers
the state of SR latch’s complementary output Qb to transition from
high to low and consequently turn on PMOS transistor, which
causes the output voltage to rise. After a delay time, the SR latch
is reset and PMOS gate drive signal is therefore raised to the input
supply, ultimately turning the device off and turning NMOS on
and causing the output voltage to decrease again. The NMOS is
turned off by the inductor current comparator when iL has decayed
to zero. Then the load will be sourcing by the energy stored in
capacitor. After the output voltage decays below the reference
voltage, the cycle repeats.
Another design consideration when synchronous buck
converters operate at light loads is negative inductor current
during synchronous operation. When the load becomes smaller
and smaller, inductor current can change from positive to partially
negative. This negative inductor current discharges the output
capacitor and causes additional losses. Therefore, efficiency can
be further increased by operating the converter in a non
synchronous mode, in which a zero-crossing detection circuit
would turn off the low-side NMOS when the inductor current
goes negative.[7][8][9]
3. Simulation results and Discussions
3.1 Comparator
Fist, the comparator is simulated, and the waveforms show that it
works well. And the Comparator 2 is used to sense the zero
voltage. When the voltage decays below zero, the output voltage
of Comparator 2 will go to high, and set the SR latch. Figure 7(a)
shows the results of the comparator when one input is zero and
another is a pulse voltage. Figure 7(b) shows the results of the
comparator when one input is zero and another is a pulse voltage.
2.3 Comparator
Figure 6 shows a circuit schematic of the reference voltage and
output voltage comparator. It is a CMOS differential amplifier.
This self-biasing of the amplifier creates a negative feedback loop
that stabilizes the bias voltages. Any variations in processing
parameters or operating conditions that shift the bias voltages
away from their nominal values result in a shift in V BIAS that
corrects the bias voltages through negative feedback.[10]
Comparator 1 is used to compare the output voltage and the
reference voltage. Vin- is reference voltage and Vin+ is output
voltage. If output voltage is higher than reference voltage, the
output is 0, and the PMOS is off. Then the output voltage goes
down. If output voltage is lower than reference voltage, the
PMOS is on, and then the output voltage will increase.
(a)
Comparator 2 is used to sense the inductor current. When the
inductor current decays negative and the voltage of the node
between NMOS and PMOS is lower than zero, the output voltage
of the comparator will be high state 1. And the inductor current
increase to positive value, the comparator’s output voltage will be
low state 0.
M3
M1a
VH
Vin+
Vbias
VL
M2a
M1b
Vout
VinM2b
M4
Fig. 6 Comparator block diagram
(b)
Fig. 7 Simulated comparator waveforms (a) comparator 1
simulation result (b) comparator 2 simulation result
3.2 Buck DC-DC converter results
The buck DC-DC converter circuit is simulated using Cadence
Spectre simulation environment. The circuit is functional for
output voltage above 300mV. The largest ripple of the output
voltage is 30mV.
Comparator 1
+ -
Vref
3.3 Power efficiency
Vdd
S
Delay
300ns
Comparator 2
R
SET
CLR
Power efficiency of a buck converter changes with a change in the
load. Efficiency of a buck converter is affected by resistive
impedances of the circuit components.
Q
PMOS
Q
L
Driver
S
SET
NMOS
Q
C
Rload
Driver
+ -
R
CLR
Q
Fig. 7 Buck DC-DC converter block diagram
Figure 7 is the block diagram of the buck DC-DC converter and
the table 1 are the parameters used in the converter. The
parameters are all calculated carefully and modified through and
through with the simulation results.
Table 1. Buck converter parameters
4. Conclusions
A synchronous buck DC-DC converter is developed for subthreshold operation of digitals circuits in this paper. The coverter
applies pulse frequency modulation (PFM) control mode which is
more efficient at light load. This paper presents the design and
prototype results of a 0.3–1.25V CMOS PFM buck DC-DC
converter. And the largest output voltage ripple is 24mV. The
control scheme provides an accurate output voltage compare to
reference voltage.
5. ACKNOWLEDGMENTS
I would like to thank to the lecturer of VLSI 632, Prof. Ben
Calhoun and all my classmates.
Input Voltage
1.25V
Output Voltage
0.3V-1.25V
Output Current
60μA - 250μA
6. REFERENCES
Load Resistor
5kΩ
Inductor
10μH
Capacitor
20μF
[1] Yogesh Ramadass, Anantha P. Chandrakasan, "Minimum
Energy Tracking Loop with Embedded DC-DC Converter
Delivering Voltages Down to 250mV in 65nm CMOS,"
IEEE International Solid-State Circuits Conference
(ISSCC), pp. 64-65, February 2007.
[2] J.Xiao, et al., “A 4uA-Quiescent-Current Dual-Mode Buck
Converter IC for Cellular Phone Applications,” ISSCC Dig.
Tech. Papers, pp. 280-281, Feb.,2004.
[3] Rohit Modak and M. Shojaei Beghini, “Buck Converter”
VLSI Research Consortium, Indian Institute of Technology,
Bombay, Oct 18,2007
[4] “DC-DC converter Tutorial”, Maxim
[5] Jing dong Chen, “Determine Buck Converter Efficiency in
PFM Mode”, Staff Application Engineer, National
Semiconductor, Santa Clara, Calif.
[6] Master thesis by Muhammad Saad Rahman “Buck Converter
Design Issues”, Linköping University
[7] Anthony John Stratakos, “High-Efficiency Low-Voltage DCDC Conversion for Portable Applications”, University of
California, Berkeley
Fig. 8 Simulation results of buck converter of Figure 7
(Vref=0.6V is the reference voltage, and V out is the output voltage,
Iin and Iout are input and output current separately)
[8] Buck-Converter Design Demystified, By Donald Schelle and
Jorge Castorena, Technical Staff, Maxim Integrated
Products, Sunnyvale, Calif.
Figure 8 shows that the buck DC-DC converter provides an
accurate output voltage compare to reference voltage. And the
start time is 50μs.
[9] Biranchinath Sahu and Gabriel A. Rincón-Mora, “An
Accurate, Low Voltage, CMOS Switching Power Supply
with Adaptive On-Time Pulse-Frequency Modulation (PFM)
Control” IEEE Circuits and Systems I: Regular Papers
[10] Two Novel Fully Complementary Self-biased CMOS
Differential Amplifiers, Mel Bazes, IEEE Journal of Solid
State Circuits, Vol. 26, No.2 February 1991