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Dr.Faisal Alzyoud
5/10/2017
INSTRUCTION SET
ARCHITECTURE (ISA)
AND LANGUAGES
Dr.Faisal Alzyoud
5/10/2017
INSTRUCTION SET ARCHITECTURE
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Instruction Set Architecture (ISA) view of the machine and its
operations. It is All of the programmer-visible components and
operations of the computer.
• ISA serves as an interface between software and hardware.
• ISA provides a mechanism by which the software tells the
hardware what should be done.
High level language code : C, C++, Java, Fortran,
compiler
Assembly language code: architecture specific statements
assembler
Machine language code: architecture specific bit patterns
software
instruction set
hardware
Dr.Faisal Alzyoud
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5/10/2017
A compiler translates a high level language, which is
architecture independent, into assembly language,
which is architecture dependent.
An assembler translates assembly language programs
into executable binary codes.
For fully compiled languages like C and Fortran, the
binary codes are executed directly by the target
machine. Java stops the translation at the byte code
level. The Java virtual machine, which is at the
assembly language level, interprets the byte codes
(hardware implementations of the JVM also exist, in
which Java byte codes are executed directly.)
A compiled program is copied from a hard disk to the
memory. The CPU reads instructions and data from the
memory, executes the instructions,
Dr.Faisal Alzyoud
5/10/2017
COMMON SIZES FOR DATA TYPES
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A byte is composed of 8 bits. Two nibbles make up a
byte.
Half-words, words, double-words, and quad-words are
composed of bytes as shown below:
Dr.Faisal Alzyoud
5/10/2017
BIG-ENDIAN AND LITTLE-ENDIAN FORMATS
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In a byte-addressable machine, the smallest datum that can
be referenced in memory is the byte. Multi-byte words are
stored as a sequence of bytes, in which the address of the
multi-byte word is the same as the byte of the word that has
the lowest address.
When multi-byte words are used, two choices for the order
in which the bytes are stored in memory are: most
significant byte at lowest address, referred to as big-endian,
or least significant byte stored at lowest address, referred to
as little-endian.
Dr.Faisal Alzyoud
5/10/2017
INTERFACE DESIGN
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A good interface:
•
Lasts through
compatibility)
many
•
Is used in many different ways (generality)
•
Provides convenient functionality to higher levels
•
Permits an efficient implementation at lower levels
use
use
use
Interface
implementations
imp 1
imp 2
imp 3
(portability,
time
Dr.Faisal Alzyoud
5/10/2017
Overview: Instruction Set Architecture
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ISA
memory organization
 address space -- how may locations can be addressed?
 addressibility -- how many bits per location?
register set
 how many? what size? how are they used?
instruction set
 opcodes
 data types
 addressing modes
provides all information needed for someone that wants to
write a program in machine language (or translate from a high-level language to
machine language).
Memory
 address space: 216 locations (16-bit addresses)
 addressability: 16 bits
Dr.Faisal Alzyoud
5/10/2017
INSTRUCTION SET DESIGN ISSUES
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Instruction set design issues include:
 Where are operands stored?
 registers, memory, stack, accumulator
 How many explicit operands are there?
 0, 1, 2, or 3
 How is the operand location specified?
 register, immediate, indirect, . . .
 What type & size of operands are supported?
 byte, int, float, double, string, vector. . .
 What operations are supported?
 add, sub, mul, move, compare . . .
An operand is the part of a computer instruction that specifies data
that is to be operating on or manipulated and, by extension, the
data itself.
Dr.Faisal Alzyoud
5/10/2017
Registers
temporary storage, accessed in a single machine cycle
accessing memory generally takes longer than a single cycle
eight general-purpose registers: R0 - R7
each 16 bits wide
how many bits to uniquely identify a register?
other registers
not directly addressable, but used by (and affected by) instructions
PC (program counter), condition codes
Opcodes
15 opcodes
Operate instructions: ADD, AND, NOT
Data movement instructions: LD, LDI, LDR, LEA, ST, STR, STI
Control instructions: BR, JSR/JSRR, JMP, RTI, TRAP
some opcodes set/clear condition codes, based on result:
N = negative, Z = zero, P = positive (> 0)
Data Types
16-bit 2’s complement integer
Addressing Modes
How is the location of an operand specified?
non-memory addresses: immediate, register
memory addresses: PC-relative, indirect, base+offset
Dr.Faisal Alzyoud
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5/10/2017
What is ARC ?
ARC: (Additional architectural models) is a simplification of the
commercial SPARC architecture common to Sun computers.
ARC: A RISC Computer (where RISC: Reduced Instruction Set
Computer).
ARC is a subset of SPARC. (where SPARCis Scalable
Processor Architecture developed by Sun Microsystems in the
1980’s).
The ARC is a 32-bit machine with byte-addressable memory: it
can manipulate 32-bit data types, but all data is stored in memory
as bytes, and the address of a 32-bit word is the address of its byte
that has the lowest address.
The ARC has a 32-bit address space, in which our example
architecture is divided into distinct regions for use by the
operating system code, user program code, the system stack (used
to store temporary data), and input and output, (I/O).
Dr.Faisal Alzyoud
5/10/2017
ARC MEMORY
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The memory map differs from one implementation to another,
which is partly why programs compiled for the same type of
processor may not be compatible across systems.
The lower 211 = 2048 addresses of the memory map are
reserved for use by the operating system.
The user space is where a user’s assembled program is loaded, and
can grow during operation from location 2048 until it meets up
with the system stack.
The system stack starts at location 231 – 4 and grows toward lower
addresses. The portion of the address space between 231 and 232 –
1 is reserved for I/O devices. The memory map is thus not entirely
composed of real memory, and in fact there may be large gaps
where neither real memory nor I/O devices exist.
An address is a pointer to a memory location, which holds data.
Dr.Faisal Alzyoud
5/10/2017
MEMORY MAP FOR THE ARC
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Memory locations are arranged linearly in consecutive order. Each
numbered locations corresponds to an ARC word. The unique
number that identifies each word is referred to as its address.
Dr.Faisal Alzyoud
5/10/2017
ABSTRACT VIEW OF A CPU
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The CPU consists of a data section containing registers and an
ALU, and a control section, which interprets instructions and
effects register transfers. The data section is also known as the
datapath.
Dr.Faisal Alzyoud
5/10/2017
THE INSTRUCTION EXECUTION CYCLE
Dr.Faisal Alzyoud
5/10/2017
AN EXAMPLE DATAPATH
The ARC datapath is made up of a collection of registers
known as the register file and the arithmetic and logic unit
(ALU).
Dr.Faisal Alzyoud
5/10/2017
WHAT IS AN INSTRUCTION SET?
The complete collection of instructions that are
understood by a CPU.
 Machine Code
 Binary
 Usually represented by assembly codes
Elements of an Instruction
• Operation code (Op code)—Do this
• Source Operand reference —To this
• Result Operand reference —Put the answer here
• Next Instruction Reference —When you have done
that, do this…
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Dr.Faisal Alzyoud
KEY ISA DECISIONS
5/10/2017
Dr.Faisal Alzyoud
5/10/2017
INSTRUCTION CYCLE STATE DIAGRAM
Dr.Faisal Alzyoud
5/10/2017
INSTRUCTION REPRESENTATION
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In machine code each instruction has a unique bit pattern.
For human consumption (well, programmers anyway) a symbolic
representation is used
e.g. ADD, SUB, LOAD
Operands can also be represented in this way:
e.g. ADD A,B
Simple Instruction Format
Dr.Faisal Alzyoud
5/10/2017
NUMBER OF ADDRESSES (3, 2, 1 OR 0)
3 addresses
—Operand 1, Operand 2, Result
—a = b + c;
—May be a forth -next instruction (usually implicit)
—Not common
—Needs very long words to hold everything
 2 addresses
—One address doubles as operand and result
—a = a + b
—Reduces length of instruction
—Requires some extra work
–Temporary storage to hold some results
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Dr.Faisal Alzyoud
5/10/2017
NUMBER OF ADDRESSES (3, 2, 1 OR 0)….CONT.
1 address
—Implicit second address
—Usually a register (accumulator)
—Common on early machines
 0 (zero) addresses
—All addresses implicit
—Uses a stack
e.g. push a, push b, add, pop c,
in order to execute c = a + b
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Dr.Faisal Alzyoud
5/10/2017
HOW MANY ADDRESSES
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o
o
o
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o
o
o
More addresses
More complex (powerful?) instructions
More registers (Inter-register operations are quicker)
Fewer instructions per program
Fewer addresses
Less complex (powerful?) instructions
More instructions per program
Faster fetch/execution of instructions
Dr.Faisal Alzyoud
INSTRUCTION TYPES
Data processing
 Data storage (main memory)
 Data movement (I/O)
 Program flow control
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5/10/2017
Dr.Faisal Alzyoud
OPERATIONS (1)
5/10/2017
Dr.Faisal Alzyoud
OPERATIONS (2)
5/10/2017
Dr.Faisal Alzyoud
OPERATION (3)
5/10/2017
Dr.Faisal Alzyoud
OPERATION (4)
5/10/2017
Dr.Faisal Alzyoud
5/10/2017
DESIGN DECISIONS
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Operation repertoire
How many ops?
What can they do?
How complex are they?
Data types
Instruction formats
Length of op code field
Number of addresses
Registers
Number of CPU registers available
Which operations can be performed on which registers?
Addressing modes (later…)
RISC v CISC
Dr.Faisal Alzyoud
5/10/2017
TYPES OF OPERAND
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Addresses
Numbers
Integer/floating point
Characters
ASCII etc.
Logical Data
Bits or flags
(Aside: Is there any difference between numbers and
characters? Ask a C programmer!)
Dr.Faisal Alzyoud
5/10/2017
TYPES OF OPERATION
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Data Transfer
Arithmetic
Logical
Types of operations
Conversion
I/O
System Control
Transfer of Control
Dr.Faisal Alzyoud
DATA TRANSFER
5/10/2017
Specify
Source
Destination
Amount of data
May be different instructions for different movements
e.g. IBM 370
Or one instruction and different addresses
e.g. VAX (Variable-length instructions (Intel 80x86, VAX)
require multi-step fetch and decode, but allow for a much more
flexible and compact instruction set.
 Fixed-length instructions allow easy fetch and decode, and
simplify pipelining and parallelism.
 All MIPS instructions are 32 bits long.
 –this decision impacts every other ISA decision we make
because it makes instruction bits scarce.
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Dr.Faisal Alzyoud
Arithmetic
Add, Subtract, Multiply, Divide
Signed Integer
Floating point ?
May include
Increment (a++)
Decrement (a--)
Negate (-a)
 Logical
Bitwise operations
AND, OR, NOT
Conversion
E.g. Binary to Decimal
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5/10/2017
Dr.Faisal Alzyoud
5/10/2017
SHIFT AND ROTATE OPERATIONS
Dr.Faisal Alzyoud
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5/10/2017
Input/Output
May be specific instructions
May be done using data movement instructions (memory mapped)
May be done by a separate controller (DMA)
Systems Control
Privileged instructions
CPU needs to be in specific state
—Ring 0 on 80386+
—Kernel mode
For operating systems use
Dr.Faisal Alzyoud
Transfer of Control
Branch
—e.g. branch to x if result is zero
Skip
—e.g. increment and skip if zero
 —ISZ Register1
—Branch xxxx
—ADD A
Subroutine call
—c.f. interrupt call
(next slide)
5/10/2017
Dr.Faisal Alzyoud
5/10/2017
BRANCH INSTRUCTION
Dr.Faisal Alzyoud
5/10/2017
NESTED PROCEDURE CALL
Dr.Faisal Alzyoud
5/10/2017
EXAMPLE OF C DATA STRUCTURE
Dr.Faisal Alzyoud
5/10/2017
ALTERNATIVE VIEW OF MEMORY MAP
Dr.Faisal Alzyoud
5/10/2017
STANDARD…WHAT STANDARD?
Pentium (80x86), VAX are little-endian
IBM 370, Moterola680x0 (Mac), and most RISC
are big-endian
Internet is big-endian
—Makes writing Internet programs on PC more
awkward!
—WinSock provides htoiand itoh(Host to Internet
& Internet to Host) functions to convert
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