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Current Conveyor with Very Low Output Impedance Voltage Buffer for Laboratory Instrumentation Vratislav Michal 1,3, Geoffroy Klisnick 2, Gérard Sou 2, Michel Redon 2, Jiří Sedláček 3 1) LGEP-Supélec, Univ Paris 06, Gif sur Yvette, France UPMC Univ Paris 06, UR2 L2E, F-75005 Paris, France 3) Brno University of Technology, DTEE, Czech Republic [email protected], www.postreh.com/vmichal 2) Abstract— This paper presents the design and implementation of second generation current conveyor CCII– in 0.35µm CMOS process. In the design, we intended to achieve very low output impedance of voltage buffer over wide frequency range, in order to comply with high requirements for laboratory instrumentation. Selected approach relies on the optimization of voltage buffer, which is composed of minimal amount of transistors. This allows considerably reducing all parasitic capacitances in the circuit and achieving very low output impedance in units of ohms at frequencies up to 10 MHz. In addition, the solution exhibits high driving capability of both X and Z output terminals. I. INTRODUCTION In some previous works [1], [6], the importance of voltage buffer output impedance in the design of low-pass frequency filters has been shown. The optimization of output impedance reflects better the operations of active components than usually used –3dB open-loop bandwidth, because the active filters for MHz frequencies operate usually at low impedance level. The device optimized in such a way can reduce some well-known imperfections, as the shift of characteristic frequency F0 or quality factor Q, or can help to avoid the stability problems, such as in design with current feedback amplifiers. The structure of second generation current conveyor was described in the literature (e.g. [3], [4]) and is shown in Fig. 1. The inter-terminal transfers is given by the relations vx = vy, iz = ± ix and iy = 0. The high frequency current transfer IX→ IZ Figure 1. Structure of CCII±. RX is the optimized resistance of the output buffer and RZ the output impedance of current output. This research project has been supported by a Marie Curie Early Stage Research Training Fellowship of the European Community’s Sixth Framework Program under contract number MEST-CT-2005-020692. Project was situated at LGEP – Supélec. can be easily done by ordinary current mirrors. Therefore, the main design constrains is to generate accurately the current IX, i.e. to maintain the terminal voltage VX = VY, independent on frequency and X-terminal load impedance. In the design of voltage buffer, we can use three different ways: circuit operating in the open-loop [4], circuits with output impedance reduced by the difference in the transconductance term [5] or voltage buffer using a voltage feedback [7] (e.g. OpAmp based buffer). Regarding our objectives, only the two last methods are suitable. For instance, an interesting solution is presented in design of an UVC (universal voltage conveyor) [5] based on four OTA, where the low output impedance relies on the numerator difference term (gma - gmb). However, this solution introduces a low-frequency parasitic zero in the output impedance, caused by the high circuit complexity. Therefore, one of our objectives is to reduce the amount of parasitic capacitances by using a circuit of which the complexity is reduced to minimum. Presented design allows to maintain output impedance at very competitive level up to MHz frequencies, along with high linearity and driving capability. Intended use of the current conveyor is in development of innovative structures of frequency filters, and in the cryogenic instrumentation dedicated for the test and development of new generation superconducting THz detectors [2]. Figure 2. The unity gain voltage follower based on circuit presented in [10]. II. LOW OUTPUT IMPEDANCE VOLTAGE BUFFER The design of CMOS voltage buffers was subject of many previous works (e.g. [5-9]). The above-defined electrical specifications lead us to choice using the modified circuit used in design of a fully differential voltage buffer [10], shown in Fig. 2. In this original design [10], the optimization of output impedance was not considered. The circuit is composed of the input and feedback transistors Mi and Mf, bias transistors Mb1-7 and the transistors of output buffer Mo1, Mo2. The gate of Mi is the input (VIN) and the gate of diode-connected transistor Mf is connected to the output of the buffer (VOUT). The main feature of circuit is the ideally zero DC offset between input and output terminals, i.e. VIN = VOUT. This feature relies on the accurately matched transistors Mi and Mf, as well as theirs bias currents ½·Ib2. The most important parameters of circuits are determined by the open-loop gain. This gain is mainly achieved in the high impedance node between Mi – Mb1. Additional gain is achieved in the output stage, based on the common source amplifiers Mo1 and Mo2. Transistor Mb4 is used for the biasing of Mo2 via the value VGS(Mb3). Transistor Mf provides only the feedback ensuring the unity voltage gain and zero DC offset of the voltage follower. A. Optimization of the Output Impedance The optimization of output impedance is based on the analysis of linearized model. The small-signal model corresponding to original circuit (Fig. 2) is shown in Fig. 3, and contains both Mi and Mf input and feedback transistors (represented by gmi and gmf) and the output transistors Mo1 and Mo2 (both substituted by gmo). In the model, the resistances r1 and r2 resulting from the channel length modulation of Mb1 and Mb2 are also included. Here, the last term shows a way allowing the optimisation of the output resistances rout , via the values of r1, gmo and gm. In the design, the attention has to be focused on the dominant parasitic zero frequency. This frequency is determined by capacitance C’ in the high impedance node (see Fig. 3) and depends primarily on the CGS of Mo1. The analysis of circuit including this capacitance allows to find the zero frequency ωz of the output impedance ZOUT (jω): ωz = 1 ( r1 ⋅ C ' ) B. Methodology of the Optimisation In modern CMOS process, a sufficient high drain resistance (r1 term in Eq. (2)) can be obtained by increasing the transistor channel length approximately above 2µm. The optimization of ZOUT then relies on values of gmi, gmo and C’. The dimensions of transistors can be found by stepped AC simulation reflecting the criterion (2), while keeping the static current consumption below some required level (Iq ≤ 3 mA). The high transconductance values required in (2) were obtained by employing high aspect ratio of the transistors drain bias currents. Resulting parameters are listed in Table I. Using of the feedback does not require an additional capacitor to provide the frequency compensation. A sufficient compensation is realized by gate capacitance of Mo1, i.e. C’ = COXW·L, where COX is the gate capacitance and W·L the gate surface. The stability of the circuit was evaluated by the Middlebrook technique [11] and transient analysis. The bias current of output transistors results namely from VDS of Mb3 and the current gain of Mo2. This signifies that this part of circuit is self-biased and can exhibit temperature depended parameters. Such a dependency may not be critical for intended laboratory use, but should be verified by the worst-case analysis respecting the process dispersions. The control of bias current can be eventually done by using any technique such as in Monticelli class-AB stage [12]. III. Figure 3. Simplified small signal model of the unity voltage follower from Fig. 2 (we consider gmo = gmo1 + gmo2). The voltage transfer can be found in the form of function: G0 = g mi g mf r2 + g mo r1 + g mf g mo r1r2 g mf 1 + g mi r2 + g mi g mo r1r2 (1) and for matched transistors gmi = gmf = gm and r1 = r2 → ∞ tends toward unity. The output resistance of the buffer (also related to the driving capability) can be derived as vout/iout when vin = 0: rout = 2r2 + 1 2 ≈ →0 r2 g m + 1 + r1r2 g mo g m g mo g m r1 (2) (3) SECOND GENERATION CURRENT CONVEYOR CCII- Based on the presented voltage buffer, the only issue of CCII± design is to accurately sense the terminal current IX. The current sensing is usually done by current mirrors in the output stage power path (see for instance [4], Fig. 9). However, this solution considerably reduces the maximal output voltage swing by the voltage drop of 2×VGS. Therefore, we provide the current sensing by measuring of the Mo1,2 gate voltage directly. The CCII– containing the voltage buffer presented in section II and biased by a floating current source Ib is shown in Fig. 4. The transfer IX → IZ is realized by four matched transistors Mm1 − Mm4 (i.e. (W/L)Mo1=(W/L)Mm1 and (W/L)Mo2=(W/L)Mm2, see Table I). By inspecting the circuit from Fig. 2 [10], we notice a mismatch between the Mo1 and Mo2 drain currents, whose values are required to be equal (i.e. IMo1 = IMo2 for IX = 0). The matching of IMo1 and IMo2 can be obtained by an additional current source of Ib(2)/2 realized by transistor Mb7, shown in Fig. 4. By this way, the gate of feedback transistor Mf becomes a high impedance node and no additional current is added to IMo1. A. Static Characteristics The measurements of DC characteristics allow to verify the basic functions of the current conveyor. The measured transfers between terminals are shown in Fig. 5. As mentioned in the figure caption, the 500Ω resistors were used to generate the X-terminal current IX and Z-terminal voltage drop V(Z). From these measured curves, we observe a large dynamic range and linearity as well as the accurate gain of voltage buffer δ (VX / VY) and its offset voltage Vos. 3.0 1.06 1.5 1.03 0 1.00 -1.5 0.97 Figure 4. Integrated CMOS CCII–. The transistor sizes and operating points are listed in Tab. I. The dimensions of transistors have been determined by stepped network simulation, respecting the criterions defined in section II. An important design parameter was also the low input capacitance of terminal Y. This capacitance results from (W·L)Mi and requires the use of a short-channel transistor Mi (LMi = 1 µm). Contrary to that, the bias transistors (Mb1−Mb7) use large transistors in order to provide very low DC offset and good matching of the output transistors bias currents. As we already mentioned, the matching is also important to control the power consumption: the overall consumption of Fig. 4 CCII reaches four-times the consumption of the buffer due to double folding of the output current by transistors Mm1 Mm6 (see Table II). -3.0 -3 -2 -1 0 1 2 3 0.94 Figure 5. DC transfer characteristics: voltage transfer Y→X for X terminal open-ended and loaded by 500 Ω, X→Z current transfer measured with matched resistances 500 Ω connected to X and Z terminals. TABLE I. DIMENSIONS AND BIAS POINTS OF THE TRANSISTORS FROM FIG. 4. NAME Mi Mf Mb1 Mb2 Mb7 Mo1 Size/type N:800/1µ N:800/1µ P:400/5µ N:401/5µ P:400/5µ P:400/2µ 401µ 400µ –401µ 802µ –403µ –2.32m ID (A) 6.32m 6.31m 1.17m 2.96m 1.17m 4.24m gm (S) NAME Mo2 Mb3 Mb4 Mb5 Mb6 Mm1 Size/type N:1000/3µ N:400/5µ N:400/2µ N:400/5µ P:800/5µ P:400/2µ 2.33m 800µ 800µ 800µ -800µ –2.37m ID (A) 10.5m 2.95m 3.61m 2.95m 2.33m 4.34m gm (S) NAME Mm2 Mm3 Mm4 Mm5 Mm6 Size/type P:800/3µ P:800/3µ N:1000/3µ N:800/4 N:800/4µ 2.37m 2.37m ID (A) –2.33m –2.37m 2.33m 5.01m 5.11m 10.5m 8.02m 8.02m gm (S) IV. PARAMETERS OBTAINED IN CMOS 0.35µm The CCII– current conveyor from Fig. 4 was integrated in a regular 0.35µm 5V process, and the main static and dynamic characteristics have been measured. The main measured features are summarized in the following table: TABLE II. B. AC Characteristic The most important parameter of design is the output impedance at high frequencies. This impedance was measured by network analyser, resulting in the curve shown in Fig. 6. We can notice a very low impedance in order of the units of ohms up to 10MHz, what is about 10 times smaller in comparison to the state of the art in CMOS (for instance [5], where the output resistance rx = 80Ω@10MHz), or another devices realised in bipolar technology. However, the impedance at lower frequency exhibits a higher value than simulation due to the signal path: metallic path and bounding resistances and connection with analyser. 100 10 MAIN MEASURED PARAMETERS VDD Voltage buffer quiescence current CCII- quiescence current Port X, Z driving ability Port Z impedance (DC) Port Z offset current -3dB AC transfer Y→X Port X impedance @ 1MHz +/- 2.5V 3 mA 11 mA +/- 20 mA ~7.5 MΩ 2.25 µA ~110 MHz 2.5 Ω 1 0.1 3 10 4 10 5 10 6 10 7 10 8 10 Figure 6. Measured and simulated resistance of terminal X. The parameters of the buffer were also evaluated by measuring the AC voltage transfer function. However, this measurement is not very significant as the shape of characteristic depend significantly on the load impedance. This is one of reasons why the output impedance was the best parameter to be optimised. For information, 3pF loaded buffer exhibits approximately 110MHz –3 dB bandwidth [2]. state of the art, especially the output impedance which reaches units of ohms up to 10MHz with 3mA power consumption. C. Design Example: 1.5MHz Low-Pass Active Filter The current conveyor functionality was demonstrated by 5th order low-pass filter design based on the biquadratic sections with high attenuation rate [1]. The circuit of active filter calculated for Butterworth type of approximation is shown in Fig. 7. R1 in 500Ω out1 X CCII– R3 1 Y X CCII– 1kΩ Z R2 C2 1 R4 5.23kΩ Q=1.68 F0=1.5MHz 65.6 pF Y Z C1 C4 65.6 pF 85.9 pF 1.53kΩ C3 Q=0.62 F0=1.5MHz R5 Out 1.06kΩ C5 F0=1.5MHz 100pF 85.9 pF Figure 7. Cascade realization of 5th order LP filter (Butterworth) [1]. The resulting frequency characteristics (Fig.8) show the transfer of entire filter, as well as the transfer of the 1st biquadratic section (out1), which correspond to the simulation results. The attenuation floor is limited by crosstalk at 100MHz and is constantly below 50dB. The photography of integrated chip containing six CCII– conveyors and fixed gain 40dB feedback-free instrumentation amplifiers [13] is shown in Fig. 9. Figure 9. Microphotography of fabricated chip on 3×3 mm2 surface, containing CCII– and feedback-free instrumentational amplifiers [13]. REFERENCES [1] [2] 0 [3] Transfer (dB) -25 [4] -50 [5] -75 -100 5 10 [6] [7] 6 10 7 10 8 10 9 10 [8] Figure 8. Measured and simulated characteristic of 1.5MHz 5th order lowpass filter from Fig. 7. [9] CONCLUSION [10] In this article, we present design of CCII– current conveyor designed to attain very low output impedance of the voltage buffer in MHz frequency range. It is shown that the optimisation of output impedance give more intelligible results compared to the optimisation of AC bandwidth. The output impedance optimisation was based on simple criterion built upon the analysis of linearized circuit. The resulting obtained electrical characteristics are fully competitive to the [11] [12] [13] V. Michal, J. Sedlacek. “Low-pass biquadratic filters with high suppression rate,” IET Electronics Letters, Volume 45, Issue 12, p. 591-593 (June 2009). V. Michal, Ph.D. thesis, Brno University of Techonolgy and Paris 6 university, http://postreh.com/vmichal/thesis/ (2009) A. Sedraa, K.C. Smith, “A second generation current conveyor and its application,” IEEE Trans., 1970, CT-17, pp. 132-134. A.S. Sedra, G.W. Roberts, F. Gohh, “The current conveyor: history, progress and new results,” IEE Proceedings Devices and Systems, Vol. 137, Issue: 2, Apr 1990. M. Minarcik, K. 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Journal of Electronics, 38 pp. 485-512, Apr. 1975. D. M. Monticelli, “A quad CMOS single-supply opamp with rail-to-rail output swing,” IEEE J. Solid-State Circuits, Vol. SC-21, 1986. V. Michal et al. “Fixed-gain CMOS differential amplifiers with no external feedback for a wide temperature range,” Cryogenics, Vol. 49, Issue 11, November 2009, Pages 615-619.