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Thin Solid Films 462 – 463 (2004) 34 – 41
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Metal gate technology for nanoscale transistors—material selection and
process integration issues
Yee-Chia Yeo *
Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, S117576 Singapore, Singapore
Available online 31 July 2004
Abstract
Reduction of the gate length and gate dielectric thickness in complementary metal oxide semiconductor (CMOS) transistors for higher
performance and circuit density aggravates problems such as poly-silicon (poly-Si) gate depletion, high gate resistance, and dopant
penetration from doped poly-Si gate. To alleviate these problems in nanoscale transistors, there is immense interest in the replacement of the
conventional poly-Si gate material with metal gate materials. A metal gate material not only eliminates the gate depletion and dopant
penetration problems but also greatly reduces the gate sheet resistance. In this paper, we discuss the material requirements for metal gate
CMOS technology and the challenges involved in the integration of metal gate electrodes in a nanoscale transistor. Issues addressed include
the choice of metal gate materials for conventional bulk and advanced transistor structures, the physics of the metal – dielectric interface, and
the process integration of these materials in a CMOS process.
D 2004 Published by Elsevier B.V.
Keywords: Work function; Metal gate; Transistor; High-k dielectric materials
1. Introduction
Size reduction of the metal oxide semiconductor field
effect transistor (MOSFET) has provided continued improvement in speed performance, circuit density, and cost
per transistor over the past few decades. In scaling the
transistor gate length LG below 50 nm, problems related to
poly-silicon (poly-Si) gate depletion and high gate resistance become very significant [1]. The gate depletion layer
(Fig. 1) increases the equivalent gate oxide thickness tox,eq
and reduces the gate capacitance in the inversion regime.
This compromises device performance due to a lower
inversion charge density or a lower effective gate voltage.
To reduce the problems of gate depletion and high gate
resistance, the active dopant density in the poly-Si gate
material must be increased. This is nevertheless limited by
the saturation active dopant density in p+ or n+ doped polySi [2]. In addition, increasing the dopant density in poly-Si
worsens the dopant penetration problem [3]. There is
therefore immense interest in replacing conventional polySi gates with metal gates [4 – 7,13 – 27]. A metal gate
* Tel.: +65-6874-2298; fax: +65-6779-1103.
E-mail address: [email protected] (Y.-C. Yeo).
0040-6090/$ - see front matter D 2004 Published by Elsevier B.V.
doi:10.1016/j.tsf.2004.05.039
material not only eliminates the gate depletion and boron
penetration problems but also reduces the gate sheet resistance. Metals are also generally more compatible with
alternative gate dielectric or high-permittivity (high-k) gate
dielectric materials than poly-Si. The urgent need for
alternative gate dielectrics to suppress excessive transistor
gate leakage and power consumption could speed up the
introduction of metal gates in complementary metal oxide
semiconductor (CMOS) transistors.
In this paper, we review the material requirements for
metal gate technology and the challenges involved in the
integration of metal gate electrodes in CMOS transistors.
Issues addressed include the choice of metal gate materials
for conventional bulk and advanced transistor structures,
physics of the metal – dielectric interface, and process integration of these materials in a CMOS process.
2. Material selection: gate work function requirements
The metal work function Um is a very important consideration in the selection of metal gate materials for device
integration because it directly affects the threshold voltage
VTH and performance of a transistor. Appropriate metal gate
Y.-C. Yeo / Thin Solid Films 462 – 463 (2004) 34–41
35
Fig. 1. (a) The energy band diagram of an NMOS device showing the
depletion layer in the poly-Si gate. (b) The poly-Si gate depletion effect
decreases the gate capacitance in the inversion regime, as evident in the
capacitance – voltage plot.
channel transistors because the magnitude of their threshold
voltages AVTHA would be too large for typical channel
doping concentrations used to control short-channel effects.
Counter-doping the channel in transistors with midgap
gates achieves the desired VTH but degrades short-channel
and turn-off characteristics [6], leading to poor transistor
performance.
For advanced transistor structures such as the surroundgate transistor or double-gate transistors, the gate work
functions must be chosen such that the gate Fermi level
falls slightly (0.2 V) above and below the intrinsic Si Fermi
level EI for optimal transistor performance [6,8]. This work
function requirement excludes the use of conventional n+ or
p+ doped poly-Si gates and emphasizes the need to replace
conventional gate materials with new gate materials for such
devices. In these advanced transistors where short-channel
effects are effectively suppressed by the novel device
architecture, heavy channel doping is not required. By
allowing the use of a lightly doped channel, significant
benefits such as enhanced mobility and immunity to statistical dopant fluctuation can be achieved. Because the
depletion charge density is too low to affect the threshold
voltage, the threshold voltage has to be tuned by gate work
function engineering alone.
Fig. 2 shows the required effective work functions for
bulk and advanced transistors relative to the silicon conduction and valence bands. The effective work function Um,eff
of a metal in a metal – dielectric system is typically extracted
from the flat-band voltage deduced from the capacitance –
voltage characteristics of a metal-dielectric semiconductor
capacitor [11,12]. On the other hand, the work function of a
metal in vacuum is usually extracted by making use of
phenomena such as photoelectric effect or thermionic emission. Work functions of several elemental metals measured
in vacuum are also plotted in Fig. 2. In addition to the
materials have to be chosen so that the threshold voltages
for n- and p-channel transistors are complementary and
sufficiently small to achieve high transistor drive currents
for a given supply voltage. Because metal gates are likely to
be introduced in conventional bulk transistors and in advanced transistor structures such as thin-body or double-gate
transistors [9,10], we shall discuss the work function
requirements for these transistors.
For bulk CMOS transistors, the required gate work
functions for n- and p-channel transistors are close to the
conduction and valence bands of silicon, respectively, to
achieve low and symmetrical VTHs for optimal CMOS
performance [6]. This requires the introduction of two
metals or metallic materials, one with an n+ poly-Si-like
work function for n-channel transistors, and another with a
p+ poly-Si-like work function for p-channel transistors.
Essentially, it is an approach that is analogous to the
conventional dual poly-Si gate technology. While the use
of a single metal with midgap work function has been
considered, it does not seem viable for bulk n- and p-
Fig. 2. Work function of several elemental metals in vacuum plotted on a
scale ranging from the positions of the conduction band to the valence band
of silicon. It should be noted that metal work functions are generally
dependent on the crystal orientation and on the underlying gate dielectric.
For metals where the crystal orientation is not indicated, the work function
is extracted from a polycrystalline sample. The required effective work
functions for bulk and double-gate (DG) transistors are also indicated.
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Y.-C. Yeo / Thin Solid Films 462 – 463 (2004) 34–41
elemental metals, other metallic materials such as metal
silicides [13 – 18], metal nitrides [19 – 21], metal oxides [23],
and metal alloys [24,25] are also considered as potential
metal gate candidates. As will be discussed in the next
section, the selection of metal materials is not as straightforward as suggested by Fig. 2 because the effective metal
work function could differ appreciably from the vacuum
work function and could depend on other factors such as the
underlying dielectric material.
3. Work function and the metal –dielectric interface
An accurate knowledge of the metal – dielectric interface
is essential for understanding the energy band alignment
between the metal and the gate dielectric and for the design
of metal gate transistors. There is a common assumption that
the effective work function of a metal on a gate dielectric is
the same as that measured in vacuum. This is inconsistent
with experimental observations [26,27]. In this section, we
explore the physics of the interface between the gate
electrode and the gate dielectric and explain the dependence
of gate work functions on the gate dielectric material.
3.1. Role of intrinsic states
Intrinsic states or metal-induced gap states (MIGS) exist
at the interfaces between a metal and a dielectric [26 – 28],
between a metal and a semiconductor [29], and between two
semiconductors [30]. It is known that wave functions of
electrons in a metal decay into a semiconductor or dielectric
in the energy range where the conduction band of the metal
overlaps the semiconductor or dielectric band gap [31].
These resulting states in the forbidden gap are the metalinduced gap states [29], or simply, the intrinsic states. For
the metal –semiconductor interface, the existence of metalinduced gap states was predicted [29] using self-consistent
pseudopotential calculations of the electronic structure of
material interfaces. For the metal –dielectric interface, metal-induced gap states or intrinsic states were experimentally
observed using electron energy loss spectroscopy (EELS)
[28]. These states are predominantly donor-like close to Ev
and mostly acceptor-like near Ec (Fig. 3). The energy level
in the band gap at which the dominant character of the
interface states changes from donor-like to acceptor-like is
called the charge neutrality level, ECNL [30]. Charge transfer
generally occurs across the interface due to the presence of
intrinsic interface states. This is contrary to the Schottky
model [32] where there is no charge transfer across the
metal– dielectric interface and the barrier height for the
electrons is given by the difference between the work
function of the metal in vacuum Um,vac and the electron
affinity of the dielectric v. Charging of the intrinsic interface
states creates a dipole that tends to drive the band lineup
towards a position that would give zero dipole charge. Fig. 3
illustrates the case where the metal Fermi level, EF,m, is
Fig. 3. Energy band diagram (left) and charging character of interface states
(right) for the metal – dielectric interface. In general, the character of
interface states becomes more acceptor (donor)-like towards the conduction
(valence) band, as indicated by the solid (dashed) line. Filling an acceptorlike interface state results in a negative charge, while leaving a donor-like
interface state empty results in a positive charge. Hence, the shaded area
represents the total negative charge on the dielectric side, while the light
gray region represents the total positive charge on the dielectric side.
above the charge neutrality level in the dielectric, ECNL,d,
creating a dipole that is charged negatively on the dielectric
side. This interface dipole drives the band alignment so that
EF,m goes towards ECNL,d, and the effective metal work
function Um,eff therefore differs from the vacuum metal
work function Um,vac. The work function change is proportional to the difference between ECNL,d and EF,m, or equivalently, the difference between Um,vac and UCNL,d [=(Evac ECNL,d)/q]. Thus, Um,eff is given by
Um;eff ¼ UCNL;d þ SðUm;vac UCNL;d Þ;
ð1Þ
where S is a slope parameter that accounts for dielectric
screening and depends on the electronic component of the
dielectric constant, el [33,34]. With a larger dielectric
screening, the slope parameter S becomes smaller, as shown
in Fig. 4(a) where the slope parameters for a variety of
materials are documented. The slope parameter S obeys an
empirical relationship given by
S¼
1
1 þ 0:1ðel1 Þ2
:
ð2Þ
Materials with a smaller S tend to pin the metal Fermi level
more effectively to ECNL,d, as illustrated in Fig. 4(b). The
maximum value for S is unity which corresponds to no
pinning of the metal Fermi level.
The interface dipole theory was first applied to the
interface between the gate and the gate dielectric of a
transistor by Yeo et al. [26,27] to explain the dependence
of the metal gate work function on the gate dielectric.
Recently, this has been substantiated by a study on the
impact of sub-monolayer coverage of a gate dielectric on
metal gate work function [35]. In Fig. 5(a), experimental
data (symbols) showing the varying degrees of pinning of
metal work functions on SiO2 and ZrO2 are plotted, demonstrating pinning towards the respective ECNL,d of the gate
Y.-C. Yeo / Thin Solid Films 462 – 463 (2004) 34–41
37
dependency is examined in Fig. 5(b) where the required
Um,vac to achieve Um,eff = 4.05 V for NMOS (solid circle)
and Um,eff = 5.17 V for PMOS (solid square) is plotted as a
function of el for five different dielectrics. The data points
in Fig. 5(b) are obtained using the extracted values of ECNL,d
and S (Table 1). For a high-k gate dielectric, a high work
function inert metal must be used as the PMOS gate
electrode. High work function metals such as platinum are
Fig. 4. (a) Variation of the slope parameter S with electronic dielectric
constant el. The relationship is empirically modeled by Ref. [34].
Materials with large el have small S. (b) A smaller S leads to a higher
degree of pinning of the metal Fermi level EF,m to the charge neutrality level
ECNL,d of the dielectric.
dielectrics. A fit of Eq. (1) to the experimental data reveals
the good agreement between the interface dipole theory and
measured data and allows the extraction of ECNL,d and S for
the gate dielectrics.
Yeo et al. [26,27] extracted the material parameters for
SiO2, Al2O3, ZrO2, HfO2, and Si3N4, as summarized in
Table 1. These parameters are useful for the selection of
metal gate materials for a given gate dielectric based on the
desired effective metal work function. For example, consider the case where the gate dielectric is ZrO2. Fig. 5(a)
suggests that in order to obtain Um,eff of 4.05 V (or 5.17 V)
for optimal NMOS (or PMOS) transistor performance, a
metal with an even smaller (or larger) Um,vac has to be used.
In fact, the selection of metal gate materials to achieve the
desired effective work functions depends on the choice of
the gate dielectric materials. As a result, research work on
metal gate technology should be performed in close conjunction with work on alternative gate dielectrics [4]. This
Fig. 5. (a) Effective work functions of metals on SiO2 and ZrO2 versus their
work functions in vacuum. Good agreement is observed between
experimental data (symbols) and the theoretical fit (lines) based on the
interface dipole theory. (b) Selection of metals to obtain effective work
functions of 4.05 and 5.17 V for five different gate dielectrics. The data
points are calculated from our experimentally extracted UCNL,d and S. The
trend lines are shown in dashes.
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Y.-C. Yeo / Thin Solid Films 462 – 463 (2004) 34–41
Table 1
Comparison of theoretical and experimental slope parameters and charge
neutrality levels for several gate dielectrics
EG
(eV)
Si
Ge
SiO2
Al2O3
Si3N4
HfO2
ZrO2
1.12
0.66
9
8.8
5.3
6.0
5.8
el
2.25
3.4
3.8
4
4.8
Theory
Empirical
Model
Experiment
ECNL Ev
(eV)
S
ECNL Ev
(eV)
S
0.86b
0.63b
0.56b
0.53b
0.41b
5.04
6.62
2.79
3.64
3.82
0.95
0.69
0.59
0.52
0.52
0.36a
0.18a
4.5
5.5c
2.6d
3.7c
3.6c
a
Taken from Ref. [30].
Determined from empirical model: S=[1 + 0.1(el 1)2] 1.
c
Taken from Ref. [36], electron band structures obtained using the
tight-binding method.
d
Calculated from band structures obtained using the self-consistent
orthogonalized linear combination of atomic orbitals (OLCAO) method
[37].
b
resistant to chemical or plasma etching, so gate patterning
would be particularly challenging. On the other hand, a low
work function metal must be used as the NMOS gate
electrode. Low work function metals such as magnesium
and hafnium are extremely reactive, and this might introduce extrinsic interface states due to defects arising from an
interfacial reaction.
3.2. Interfacial reaction and extrinsic states
The dependence of metal work function on the gate
dielectric material is explained [26,27] to be due to the
dipole formation at the interface of the gate electrode and
the gate dielectric. This model has been particularly successful for metal – dielectric interfaces where there is minimal interfacial reaction or where intrinsic states or metalinduced gap states (MIGS) dominate. In addition to the
dependency on the gate dielectric material, the metal gate
work function has been observed to be dependent on
process conditions [22,38,39]. In Ref. [38], it was reported
that the work function of TiN on the SiO2 gate changes on
high temperature (>850 jC) annealing. In Ref. [22], it was
observed that the work functions of the TaN, TaSi, and
TaSiN metal gates on HfO2 change with post-gate anneal. A
larger work function shift is observed when the thermal
budget is increased. It was postulated that atomic interdiffusion and reaction at the metal –dielectric interface could
have caused the aforementioned variations. Interfacial reaction, interdiffusion, or formation of extrinsic states can
manifest as thermal instability of work function or transistor
threshold voltages.
Extrinsic interface states arising from defects or interfacial reaction should be distinguished from intrinsic interface
states discussed in the context of the interface dipole theory.
Any large deviation of the measured effective work functions from the linear trend in Fig. 5(a) may be attributed to
the existence of extrinsic interface states. Extrinsic states at
the metal –dielectric interface could drive Fermi level pinning and the convergence of work function to a pinning
level. A metal – dielectric interface model that takes the role
of extrinsic states into account was recently proposed to
qualitatively explain the work function instability phenomenon [40]. The creation of extrinsic states and the resulting
Fermi level pinning of the metal gate work function is
observed for certain combinations of metal gate and gate
dielectric materials, particularly when the gate dielectric is
SiO2. The effect appears to be thermodynamically driven,
becoming more pronounced when the annealing temperature is higher. A similar observation was made for the case
of the interface between poly-Si and a high-permittivity gate
dielectric such as HfO2 and Al2O3 [41].
It should be noted that the creation of extrinsic states and
the resulting Fermi pinning is not a universal phenomenon
that occurs for all combinations of metal gates and gate
dielectrics. Extrinsic states are absent at a defect-free interface where the metal work function is predominantly
determined by intrinsic states [26,27].
4. Process integration of metal gates
Besides the achievement of the appropriate effective
work function at the metal – dielectric interface, one of the
most important challenges in metal gate CMOS technology
is the integration of two different types of metal gates in a
device fabrication process.
4.1. Dual metal approach
The most straightforward method of introducing two
metals in a CMOS-integrated circuit is the dual metal gate
process, which was employed in the first demonstration of a
dual metal gate CMOS technology by Yeo et al. [4]. After
device isolation structures are formed, a first metal which is
to become the NMOS transistor gate electrode is deposited.
A noncritical lithography step is used to cover the NMOS
regions with photoresist, while the first metal over the
PMOS region is etched to yield the cross-section shown
in Fig. 6(a). This is followed by the deposition of a second
metal, as shown in Fig. 6(b). Given that the first and second
metals have thicknesses of about 200 Å or less, a poly-Si
layer is added on the metal layers to reduce sheet resistance
and to provide a structure for blocking source/drain implants
or for forming sidewall spacers. Transistors are then formed
[Fig. 6(c)]. The NMOS and PMOS transistor gate electrodes
have effective work functions determined by the first and
second metals, respectively. In Ref. [4], the first metal
comprises titanium (Ti) and the second metal comprises
molybdenum (Mo). Titanium nitride barriers are also
inserted between the first and second metals and between
the second metal and the poly-Si to prevent reactions or
interdiffusion. In principle, the concept is applicable to any
Y.-C. Yeo / Thin Solid Films 462 – 463 (2004) 34–41
39
Fig. 7. Dual work function metal gate CMOS technology using metal
interdiffusion [43].
Fig. 6. Dual metal gate process flow [4] showing the use of a first metal for
the NMOS transistor and a second metal for the PMOS transistor.
combination of metal candidates. This approach, however,
exposes the gate dielectric to a metal etchant which causes
undesirable thinning and potential gate dielectric damage.
The first metal should preferably have a high etch selectivity
over the gate dielectric so that the gate dielectric is not
significantly damaged during the etching of the first metal.
Park et al. [42] improved the dual metal approach by
inserting an ultrathin buffer layer of aluminum nitride
AlNx between the gate dielectric and the first metal, effectively preventing the exposure of gate dielectric to metal
etchants. The AlNx buffer layer gets completely consumed
upon annealing through reaction with the metal gate, modifying the original metal work function as a result.
function can be controlled by choosing the thickness compositions of the metal layers. In Ref. [43], the second metal
has the propensity to segregate at the dielectric interface [Fig.
7(b)]. For the case where the first metal is Ti and the second
metal is Ni, the segregation has been substantiated using Xray photoelectron spectroscopy. Consequently, the second
metal solely determines the work function of the PMOS gate
electrode. Polishchuk et al. [44] reported the fabrication of
transistors using the metal interdiffusion approach, and work
functions of f 4 and f 5 eV were obtained for Ti and Ni
gate transistors, respectively.
4.3. Single metal dual work function approach
The introduction of two different metal materials requires
substantial process complexity, as one may appreciate in the
abovementioned approaches. While two metals with appropriate work functions would ordinarily be required, a
method for tuning the work function for a single deposited
metal gate layer over the entire required work function range
would offer minimal process complexity. Ranade et al.
[45,46] pioneered the single metal dual work function
4.2. Metal interdiffusion approach
An alternative approach in which dual metal gates can be
fabricated without exposing the gate dielectric to the etchant
is the metal interdiffusion approach [43,44]. In this approach,
a thin layer of a first metal, e.g., Ti, is deposited over the
entire wafer. A second metal, e.g., Ni, is then deposited on
the first metal, while removing the second metal on selected
regions, as shown in Fig. 7(a). Because the first metal is the
only metal remaining on the NMOS region, it will determine
the threshold voltage of the NMOS transistor. The two
remaining metals on the PMOS region are subsequently
allowed to interdiffuse. In some cases, the two metals will
mix, yielding an intermediate gate work function. Work
Fig. 8. Single metal dual work function approach using ion implantation of
nitrogen into molybdenum to modify metal work function [45].
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Y.-C. Yeo / Thin Solid Films 462 – 463 (2004) 34–41
unreacted metal may be removed [Fig. 9(b)]. However,
cobalt silicide is not the ideal gate electrode material
because it has a work function that corresponds to the
silicon midgap. Maszara et al. [14] employed nickel silicidation on n+ and p+ doped poly-Si and found that dual work
function silicided gates can be achieved. The values of work
functions were f 4.5 and 4.9 eV for NMOS and PMOS,
respectively. Pile-up of arsenic at the NMOS dielectric is
believed to be responsible for the NiSi work function
modification. This technique was applied to fully depleted
silicon-on-insulator transistors [15] and to double-gate transistors [18]. The work function of 4.5 eV is still not low
enough for bulk NMOS transistors, and further work on
alternative metal silicides with lower work functions would
be useful.
5. Conclusion
Fig. 9. Silicidation of poly-Si gate to form a fully silicided gate electrode.
approach, as shown in Fig. 8. Mo film with a (110) crystal
orientation displayed a high work function of 4.9 eV
suitable for PMOS transistors. When the Mo film is nitrogen-implanted and annealed, it exhibits a work function
reduction by as much as f 0.5 eV, depending on the
implant energy and dose. An implant dose of about
1 1016 cm 2 is required to realize the maximum work
function shift. It is hypothesized that the effect is primarily
due to a chemical change in the metal gate material at the
gate dielectric interface, probably the formation of Mo2N.
Although the work function shift demonstrated is not
sufficient for bulk CMOS transistors, it is acceptable for
ultrathin body transistors and double-gate transistors. The
applicability of this technique to ultrathin body transistors
and double-gate transistors was recently demonstrated [46].
Metal gate electrodes will be required for nanoscale bulk
transistors and advanced transistor structures such as double-gate transistors. The work function requirements for
metal gate CMOS technology were reviewed. Bulk CMOS
transistors require effective metal work functions near the
conduction and valence bands of silicon, while double-gate
CMOS transistors require effective metal work functions 0.2
eV above and below the intrinsic level of silicon. The
metal – dielectric interface was examined. Metal work functions on high-permittivity dielectrics differ appreciably from
their values on silicon oxide or in vacuum. This dependence
of metal gate work functions on the underlying gate dielectric was explained using the interface dipole theory. Metal
work functions could also be affected by interfacial reaction,
interdiffusion, and defects that lead to Fermi level pinning.
Challenges involved in the process integration of metal gate
electrodes in nanoscale transistors were described. Several
promising integration approaches were reviewed and compared. The dual metal approach and the metal interdiffusion
approach appear to be attractive for bulk CMOS transistors,
while the single metal dual work function approach and the
full silicidation approach seem attractive for ultrathin body
transistors and double-gate transistors.
4.4. Full silicidation approach
The first demonstration of the total or full silicidation of
the poly-Si was by Tavel et al. [13] where transistors with
cobalt silicided gate electrodes are formed. In the work of
Tavel et al. [13], one way to perform the full silicidation
process is to form a poly-Si gate transistor, deposit a
dielectric over the transistor, perform a chemical – mechanical polishing step to expose the poly-Si gate, and then
deposit a metal over the exposed poly-Si to give the crosssection shown in Fig. 9(a). This is followed by a silicidation
process which is done at an elevated temperature. The
silicidation consumes the entire poly-Si gate, stopping on
the gate dielectric and forming a silicide gate. Excess
6. Uncited reference
[47]
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