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Library Netlists Inverter (ece3663Inverter) // Cell name: ece3663Inverter // An inverter with sizing parameters and parameterized AD,AS,PD,PS // The S/D parameters assume a single-finger device subckt ece3663Inverter VDD VSS in out parameters wp=3u wn=1.5u ln=600n lp=600n mult=1 MP (out in VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp MN (out in VSS VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn ends ece3663Inverter // End of subcircuit definition pd=3u+wp m=mult pd=3u+wn m=mult 2-input NAND (ece3663NAND2) // Cell name: ece3663NAND2 // modified by Team XOR on 3/31/10 to fix naming convention and size for equal PUN/PDN resistances subckt ece3663NAND2 Vdd Vss InA InB Out parameters wp=3u wn=1.5u ln=600n lp=600n mult=1 P1 (Out InB Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \ pd=3u+wp m=mult P0 (Out InA Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \ pd=3u+wp m=mult N1 (net18 InB Vss Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+2*wn \ pd=3u+2*wn m=mult N0 (Out InA net18 Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \ ps=3u+2*wn pd=3u+2*wn m=mult ends ece3663NAND2 // End of subcircuit definition. 2-input NOR (ece3663NOR2) // Cell name: ece3663NOR2 // Modified by Team XOR on 3/31/10 to fix naming convention and size for equal PUN/PDN resistances subckt ece3663NOR2 Vdd Vss InA InB Out parameters wp=3u wn=1.5u ln=600n lp=600n mult=1 P1 (Out InB net10 Vdd) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp \ pd=3u+2*wp m=mult P0 (net10 InA Vdd Vdd) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp \ pd=3u+2*wp m=mult N1 (Out InB Vss Vss) ami06N w=wn l=lp as=1.5u*wn ad=1.5u*wn \ ps=3u+wn pd=3u+wn m=mult N0 (Out InA Vss Vss) ami06N w=wn l=lp as=1.5u*wn ad=1.5u*wn \ ps=3u+wn pd=3u+wn m=mult ends ece3663NOR2 // End of subcircuit definition. 2-input AND (ece3663AND2) // Cell name: ece3663AND2 // Implementation: NAND in series w/ inverter // Modified 3/17/2010 by Team Mux to correct faults in netlist parameters // Modified 4/4/2010 by Team Mux to conform to class conventions subckt ece3663AND2 Vdd Vss InA InB Out parameters wp=3u wn=1.5u ln=600n lp=600n mult=1 P2 (Out net049 Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp \ ps=3u+wp pd=3u+wp m=mult region=sat P1 (net049 InB Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp \ ps=3u+wp pd=3u+wp m=mult region=sat P0 (net049 InA Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp \ ps=3u+wp pd=3u+wp m=mult region=sat N2 (Out net049 Vss Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn \ ps=3u+wn pd=3u+wn m=mult region=sat N1 (net22 InB Vss Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \ ps=3u+2*wn pd=3u+2*wn m=mult region=sat N0 (net049 InA net22 Vss) ami06N w=2*wn l=ln as=1.5u*2*wn \ ad=1.5u*2*wn ps=3u+2*wn pd=3u+2*wn m=mult region=sat ends ece3663AND2 2-input OR (ece3663OR2) // Cell name: ece3663OR2 // // // // Implementation: NOR in series with inverter Modified 3/17/2010 by Team MUX to standardize transistor names Modified 3/31/2010 by Team XOR to fix naming convention and size for equal PUN/PDN resistances Modified 4/4/2010 by Team MUX to fix wrong bulk connection and conform to class conventions subckt ece3663OR2 Vdd Vss InA InB Out parameters wp=3u wn=1.5u ln=600n lp=600n mult=1 P2 (Out net21 Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \ pd=3u+wp m=mult region=sat P1 (net21 InB net10 Vdd) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp \ pd=3u+2*wp m=mult region=sat P0 (net10 InA Vdd Vdd) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp \ pd=3u+2*wp m=mult region=sat N2 (Out net21 Vss Vss) ami06N w=wn l=lp as=1.5u*wn ad=1.5u*wn \ ps=3u+wn pd=3u+wn m=mult region=sat N1 (net21 InB Vss Vss) ami06N w=wn l=lp as=1.5u*wn ad=1.5u*wn \ ps=3u+wn pd=3u+wn m=mult region=sat N0 (net21 InA Vss Vss) ami06N w=wn l=lp as=1.5u*wn ad=1.5u*wn \ ps=3u+wn pd=3u+wn m=mult region=sat ends ece3663OR2 2-input XOR (ece3663XOR2) // Cell name: ece3663XOR2 // An implementation of a two input XOR =A'*B+A*B'=((A'*B)'*(A*B')')' // // // // Inputs to the XOR are named "A" and "B" Output of the XOR is named "out" High voltage is named "VDD" Low voltage (ground) is named "VSS" //subsubcircuit inverters used have been sized to make worst-case PUN resistance and worst-case PDN resistance the same //subsubcircuit NANDs used have been sized to make worst-case PUN resistance and worst-case PDN resistance the same //edited by Team ADD at 10:38 p.m. on Sunday, 4 April 2010 subckt ece3663XOR2 VDD VSS A B out parameters wpGlobal=3u wnGlobal=1.5u lnGlobal=600n lpGlobal=600n multGlobal=1 //subsubcircuits that invert the inputs //inverter for input A invA (VDD VSS A notA) ece3663Inverter wp=wpGlobal wn=wnGlobal ln=lnGlobal lp=lpGlobal mult=multGlobal //inverter for input B invB (VDD VSS B notB) ece3663Inverter wp=wpGlobal wn=wnGlobal ln=lnGlobal lp=lpGlobal mult=multGlobal //basically first input NAND p1comma1 (intermediate1 notA VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal p1comma2 (intermediate1 B VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal n1comma1 (intermediate1 notA node1 VSS) ami06N w=2*wnGlobal l=lnGlobal as=1.5u*2*wnGlobal ad=1.5u*2*wnGlobal ps=3u+2*wnGlobal pd=3u+2*wnGlobal m=multGlobal n1comma2 (node1 B VSS VSS) ami06N w=2*wnGlobal l=lnGlobal as=1.5u*2*wnGlobal ad=1.5u*2*wnGlobal ps=3u+2*wnGlobal pd=3u+2*wnGlobal m=multGlobal //basically second input NAND p2comma1 (intermediate2 A VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal p2comma2 (intermediate2 notB VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal n2comma1 (intermediate2 A node2 VSS) ami06N w=2*wnGlobal l=lnGlobal as=1.5u*2*wnGlobal ad=1.5u*2*wnGlobal ps=3u+2*wnGlobal pd=3u+2*wnGlobal m=multGlobal n2comma2 (node2 notB VSS VSS) ami06N w=2*wnGlobal l=lnGlobal as=1.5u*2*wnGlobal ad=1.5u*2*wnGlobal ps=3u+2*wnGlobal pd=3u+2*wnGlobal m=multGlobal //basically third combining/output NAND p3comma1 (out intermediate1 VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal p3comma2 (out intermediate2 VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal n3comma1 (out intermediate1 node3 VSS) ami06N w=2*wnGlobal l=lnGlobal as=1.5u*2*wnGlobal ad=1.5u*2*wnGlobal ps=3u+2*wnGlobal pd=3u+2*wnGlobal m=multGlobal n3comma2 (node3 intermediate2 VSS VSS) ami06N w=2*wnGlobal l=lnGlobal as=1.5u*2*wnGlobal ad=1.5u*2*wnGlobal ps=3u+2*wnGlobal pd=3u+2*wnGlobal m=multGlobal ends ece3663XOR2 // End of subcircuit definition 2-input XNOR (ece3663XNOR2) // Cell Name: ece3663XNOR2 // Edited by Team XOR: a 2-input XNOR gate built from other subcircuits // Has tunable parameters including: wp, wn, lp, ln, and m // Has parameterized AS, AD, PS, PD // Implements the function: XNOR = ((F*G)')' // where F = B + A'B' and G = A + A'B' // // // // not the most efficient implementation, but this is what the 2008 group chose to do. originally this was made of 18 discrete transistors with a ridiculous netlist that was very difficult to understand. we've improved this by "packaging" the transistors into the gates they had essentially created. subckt ece3663XNOR2 (VDD VSS A B Out) parameters wp0=3u wn0=1.5u lp0=600n ln0=600n mult0=1 NOR (VDD VSS A B center) ece3663NOR2 wp=wp0 wn=wn0 lp=lp0 ln=ln0 mult=mult0 ORtop (VDD VSS B center F) ece3663OR2 wp=wp0 wn=wn0 lp=lp0 ln=ln0 mult=mult0 ORbottom (VDD VSS A center G) ece3663OR2 wp=wp0 wn=wn0 lp=lp0 ln=ln0 mult=mult0 NAND (VDD VSS F G Outbar) ece3663NAND2 wp=wp0 wn=wn0 lp=lp0 ln=ln0 mult=mult0 INVERTER (VDD VSS Outbar Out) ece3663Inverter wp=wp0 wn=wn0 lp=lp0 ln=ln0 mult=mult0 ends ece3663XNOR2 3-input NAND (ece3663NAND3) // Cell name: NAND3 // View name: schematic // Edited by group NOR: 3 input NAND gate with tunable wp, wn, lp, ln, and m // Sized for equal pull-up, pull-down to Inv subckt ece3663NAND3 (VDD VSS A B C OUT) parameters wp=3u wn=4.5u ln=600n lp=600n mult=1 MNC (NETCB C VSS VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \ pd=3u+wn m=mult region=sat MNB (NETBA B NETCB VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \ pd=3u+wn m=mult region=sat MNA (OUT A NETBA VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \ pd=3u+wn m=mult region=sat MPC (OUT C VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \ pd=3u+wp m=mult region=sat MPB (OUT B VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \ pd=3u+wp m=mult region=sat MPA (OUT A VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \ pd=3u+wp m=mult region=sat ends ece3663NAND3 //END OF subcircuit definition 3-input NOR (ece3663NOR3) // Cell name: NOR3 // View name: schematic // Edited by group NOR: 3 input NOR gate with tunable wp, wn, lp, ln, and m // Sized for equal pull-up, pull-down to Inv subckt ece3663NOR3 (VDD VSS A B C out) parameters wp=9u wn=1.5u ln=600n lp=600n mult=1 MPa (netab A VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \ pd=3u+wp m=mult MPb (netbc B netab VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \ pd=3u+wp m=mult MPc (out C netbc VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \ pd=3u+wp m=mult MNa (out A VSS VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \ pd=3u+wn m=mult MNb (out B VSS VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \ pd=3u+wn m=mult MNc (out C VSS VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \ pd=3u+wn m=mult ends ece3663NOR3 // End of subcircuit definition. 3-input AND (ece3663AND3) // Cell name: AND3 // View name: schematic // Edited by group NOR: 3 input AND gate with tunable wp, wn, and m // sized for pull-up/pull-down equal to inverter subckt ece3663AND3 (VDD VSS A B C OUT) parameters wpA=3u wnA=1.5u multA=1 NAND (VDD VSS A B C Invertin) ece3663NAND3 wp=wpA wn=wnA*3 mult=multA Inv (VDD VSS Invertin OUT) ece3663Inverter wp=wpA wn=wnA mult=multA ends ece3663AND3 //end of subcircuit definition 3-input OR (ece3663OR3) // Cell name: OR3 // View name: schematic // Edited by group NOR: 3 input OR gate with tunable wp, wn, and m // sized for pull-up/pull-down equal to inverter subckt ece3663OR3 (VDD VSS A B C out) parameters wpO=3u wnO=1.5u multO=1 NOR (VDD VSS A B C Invertin) ece3663NOR3 wp=wpO*3 wn=wnO mult=multO Inv (VDD VSS Invertin out) ece3663Inverter wp=wpO wn=wnO mult=multO ends ece3663OR3 // End of subcircuit definition. 2:1 MUX (ece3663MUX2to1) // Cell name: ece3663MUX2to1 // Modified by: Team NAND // improvement: resized NMOS transistors to reduce transmission delay // 4/23/10 - conformed to class naming convention // - fixed sizing mistakes for area and perimeter for NMOS subckt ece3663MUX2to1 VDD VSS in0 in1 Select out parameters wp=3u wn=1.5u ln=600n lp=600n mult=1 I0 (VDD VSS Select selectBar) ece3663Inverter wn=wn wp=wp mult=mult P5 (net15 Select VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \ pd=3u+wp m=mult P4 (net15 in1 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \ pd=3u+wp m=mult P3 (out net15 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \ pd=3u+wp m=mult P2 (out net31 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \ pd=3u+wp m=mult P1 (net31 in0 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \ pd=3u+wp m=mult P0 (net31 selectBar VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \ pd=3u+wp m=mult N5 (net35 net15 VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \ pd=3u+wn*2 m=mult N4 (out net31 net35 VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \ pd=3u+wn*2 m=mult N3 (net43 Select VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \ pd=3u+wn*2 m=mult N2 (net15 in1 net43 VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \ pd=3u+wn*2 m=mult N1 (net31 selectBar net55 VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \ pd=3u+wn*2 m=mult N0 (net55 in0 VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \ pd=3u+wn*2 m=mult ends ece3663MUX2to1 //end subcircuit definition 4:1 MUX (ece3663MUX4to1) //Cell name: ece3663MUX4to1 // Modified by: Team NAND // fixed ability to size mux with variables // 4/23/10 - conformed to class naming convention subckt ece3663MUX4to1 VDD VSS in00 in01 in10 in11 Select0 Select1 out parameters wp=3u wn=1.5u ln=600n lp=600n mult=1 I0 (VDD VSS in00 in01 Select0 net75) ece3663MUX2to1 wn=wn wp=wp mult=mult I1 (VDD VSS in10 in11 Select0 net79) ece3663MUX2to1 wn=wn wp=wp mult=mult I2 (VDD VSS net75 net79 Select1 out) ece3663MUX2to1 wn=wn wp=wp mult=mult ends ece3663MUX4to1 //end subcircuit definition Transmission Gate (ece3663tgate) // Cell name: ece3663tgate // Modified by: Team NAND // Added ability to control the size of tgate with variables wn and wp. // 4/23/10 - conformed to class naming convention // - fixed wp and wn sizing mistakes subckt ece3663tgate VDD VSS in pass out parameters wp=3u wn =1.5u ln=600n lp=600n mult=1 I3 (VDD VSS pass pass_inv) ece3663Inverter wn=wn wp=wp mult=mult N0 (in pass out VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \ pd=3u+wn m=mult region=sat P0 (out pass_inv in VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \ pd=3u+wp m=mult region=sat ends ece3663tgate //end of subcircuit definition TGate MUX (ece3663tGateMux) // Cell: ece3663tGateMux // Modified by: Team NAND // added ability to control sizing from variables wn and wp. // 4/23/10 - conformed to class naming convention subckt ece3663tGateMux VDD VSS in0 in1 select out parameters wp=3u wn=1.5u ln=600n lp=600n mult=1 I0 (VDD VSS in0 selectPrime out) ece3663tgate wn=wn wp=wp mult=mult I1 (VDD VSS in1 select out) ece3663tgate wn=wn wp=wp mult=mult I2 (VDD VSS select selectPrime) ece3663Inverter wn=wn wp=wp mult=mult ends ece3663tGateMux //end of subcircuit definition