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EECS 270, Winter 2017, Lecture 9
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Today
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Go over using Verilog to model state machines.
Discuss the exam on Wednesday
Start on Memories (we likely won’t finish)
Wednesday’s class will be a 15-25 minute talk reminding people of topics and ideas in the class. The rest will be
Q&A, mainly from old exams and quizzes. We recommend you bring the old exams and quizzes with you to class
on Wednesday (you can have them during the exam, so printing them and bringing them seems reasonable).
Verilog
Everything we’ve done so far in lab has been combinational logic using assign statements. In lab 4 we’ll need a
way to implement sequential logic AND we’ll want something a bit more flexible for combinational logic.
Verilog is a very powerful language with a large mess of complexity that can be gotten into. In EECS 270 we
greatly restrict the form of the language you can use. We do this partly for pedagogical reasons, but also to
restrict the number of ways you can shoot yourself in the foot. Take EECS 470 if you want to learn more about
Verilog (but even it is probably only the equivalent of EECS 280 for C++).
The “always @” statement
One way to model sequential logic is to say “only reevaluate this logic at certain times”. The always @
statement does exactly that.
As the above figure indicates, we use only two forms of this. One is “evaluate only on the positive edge of the
clock” and the other is “constantly reevaluate”. That last one is another way to do combinational logic. Why do
we need two ways of doing combinational logic? Well, always @* blocks are much more flexible but much
easier to mess up. So my rule is to use an assign statement when you can.
The begin and end here are just like { and } in C++.
Example
The following is take from a lab document which builds the following FSM in Verilog.
EECS 270, Winter 2017, Lecture 9
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In our @* block we can use case statements, if
statements and a few other things. That
makes it all a LOT more flexible. That said, it’s
really just asking Verilog to do the work. Let’s
consider this encoding (one-hot) with state
and next_state having 3 bits.
Next state logic via always @* block
via assign
Next state logic
statements?
What are the pros and cons of each scheme?
Sequential logic in Verilog
We say “always @ (posedge clock)” to build something that is only updated at the positive edge of the
clock (like a flip-flop). The following implements our 3 flip-flops (recall that state and next_state are
declared as 3-bit registers).
Notice how we’ve created a
reset state. Also notice that
we use <= to assign in a
sequential logic block.
EECS 270, Winter 2017, Lecture 9
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Final Verilog comments:
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If we assign to something with an assign statement, it needs to be a “wire”.
If we assign to something in an always block it needs to be a “reg”.
If you assign to a variable in an always@* block you must be sure you assign to it on all paths.
This means that if you ever assign a variable a value in an always block you must be sure that
every time that block is evaluated that variable is assigned a value (even if you don’t care).
o Why do you think is important?
You must never assign a value to the same variable in more than one block.
o You may however assign to it more than once in a given block. The last one wins.
Exam material
This document is not meant to be complete, it is merely an attempt to organize things and provide a
checklist of things you really know. The exam is open book and open notes, but don’t expect to have
time to look everything up! If you’ve never taken an open-book exam before, don’t be overconfident.
Things you should be able to:
 Convert a logic function to a truth table and/or a digital circuit
 Convert digital circuit to a truth table and/or logic function
 Utilize, and implement using gates various MSI devices including Encoders, Adders, Decoders,
Priority Encoders and MUXes.
 Convert to and from different number bases (base 2, 10, etc.)
 Use and understand tri-state devices.
 Convert to and from different methods of number representation (unsigned, 2’s complement,
signed-magnitude, excess) as well as understand what values can be represented in these
schemes given N bits.
 Manipulate a logic function using the basic rules of logic.
 Understand the use of S-R latch, D latch T flip-flop, SR flip-flop, JK flip-flop, and D flip-flop.
 Design a state transition diagram to solve a problem
 Design a state machine given a state transition diagram
 Design a state transition diagram given the circuit for a state machine
 Terms/concepts you should know:
o Gray code, MSB, sign extension
o literal, minterm, maxterm, canonical sum/product, Sigma/Pi notation
 Understand delay—both worst-case analysis and gate-by-gate analysis
 Understand setup and hold times and how those impact our designs.
 Compute minimum clock period for a given design.
 Read and write Verilog as used in lab 3 including assign statements, implementing modules, and
instantiating modules. Understand how Verilog is just another way of representing digital logic.
Expect to have a 20-30 point closed book part. On that part you should expect things like designing MSI
devices out of gates (including using tri-states), terms and definitions (minterms, literals, etc.), number
representation (negative schemes, base 2, 8, 16, etc.), the 4 logic rules you are to know, timing
diagrams. Also how to build each of the latches and flip-flops from gates, clock period/frequency
conversions, truth tables, SoP/PoS representation, and similar topics that you could likely just copy
answers from the text.
EECS 270, Winter 2017, Lecture 9
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Memories (5.6)
A memory is a device that acts like a big array. You supply an index (called an address) and it supplies
the data at that location. You can also write to a given address.
10
A[9:0]
Data[7:0] 8
OE
WE
On the left is a 1024x8 memory. That is it has 1024 entries and each
entry is 8 bits wide. If Write Enable (WE) is a 1, that means we want
to write the value on the data lines into the memory location specified
by the address (A) lines. If WE is a 0 and Output Enable (OE) is a 1 that
means we want the data at location A to be put on the Data lines. If
both WE and OE are zeros, Data is high-Z.
Clock
Notice that data is sometimes an input and sometimes an output!
Questions:
1. What values should we apply if we want to write 0x12 to memory location 0x044?
A[9:0]= __________ OE=______ WE=______ Data[7:0]=__________
2. What values should we apply if we want to read memory location 0x44?
A[9:0]= __________ OE=______ WE=______ Data[7:0]=__________
Types of memories
There are a number of different types of memories each with a different set of properties.

ROM: _______________________________________________________________________
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RAM:
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Volatile vs. Non-volatile: _________________________________________________________
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Static vs. Dynamic: _____________________________________________________________
_______________________________________________________________________
And we commonly find the following common memory types:
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DRAM: ______________________________________________________________________
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SRAM: ______________________________________________________________________
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Flash*:______________________________________________________________________
*Note that flash is a particular technology. There are other things (e.g. Magnetoresistive RAM
(MRAM)) that have similar properties.
EECS 270, Winter 2017, Lecture 9
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Inside the memories—the little picture
Memories are generally large arrays with small 1-bit cells in them. Let’s look at the cell in an SRAMi and
DRAMii.
On the left is a single SRAM cell. The
inverter pair should be familiar to you—
it’s the same bi-stable device we started
with as a starting point for a latch. The
other devices are transistors. We’ll cover
them in a few weeks, but in this context
you can basically think of them as being a
door. If the word line is high, A connects
to Q and B connects to Qbar. Otherwise
they don’t. To read from the device, we
simply set the word line high and read the
bit line. To write, we “strongly” drive the bit lines and set the word line to be one. That will override the
inverter pair’s relatively weak signal.
DRAM works in a very similar way. The main difference is that a
capacitor is used to store the value. That capacitor will only hold
the value for a short time (on the order of 1 to 10 ms!). (A
capacitor is a device that holds a certain voltage level for a
while). It also suffers from a feature called a “destructive
read”—when you read the data, the data is lost.
To deal with the issues associated with the value going away on a DRAM we have to “refresh” the
capacitor on a regular basis. That means we read and re-write the data many hundreds of times a
second…
SRAM vs. DRAM
Area/Density:
 You can generally put about 5-20 DRAM cells in place of one SRAM cell. This translates into
DRAM being a lot cheaper per bit.
Cost:
 Cost tends to be fairly proportional to area…
Speed:
 SRAM tends to be a lot faster (say on the order of 1-3ns compared to 20-100ns for DRAM).
Power:
 SRAM tends to eat a lot more power (4GB of DRAM is around 10 Watts in one case, 4MB of
SRAM is about 0.5 Watts in another, so a factor of 50/bit in this case. That’s not quite a fair
comparison; a factor of 10 might be closer…)
We tend to use DRAM when we need lots of cheap memory. SRAM when we need to go fast. A
microprocessor uses DRAM for the main memory and SRAM for the cache (small fast memory that
keeps most likely to be needed data).
EECS 270, Winter 2017, Lecture 9
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Inside the memories—the big picture
The figure on the left shows how to use a 4x4
memory block to create a 16x1 memory (16
addresses, each one bit). In this diagram we
have 4 address lines and one data line. There
is also an OE’ (meaning active low) and a WE’
(also active low).
5. Given a 16x16 memory array in
which we want to have 4-bit words,
how many different words would
there be?
________
6. Fill in the five blanks found in the
figure to the right.
________
_____ decoder
Questions:
1.
What is the decoder doing?
2.
What is the MUX doing?
3.
What is CS’ doing?
4.
Memory blocks tend to be square (4x4
in this case).
Why do you think that is?
memory
array
256bits (16x16)
______mux/demux
OE’
CS’
WE’
________
i
ii
Figure taken from necel.com.
Figure taken from 1.bp.blogspot.com