Download Double Bridge Test Structures

A
Report
on
Defect Modeling in Integrated Circuits
as a part of the project
Yield Estimation based on Layout & Process Data
by
Karthik Subramanian
628-78-6005
Hamish Swaminathan
628-78-2972
January 2003
DEFECT MODELING IN ICs.
Need for an appropriate defect model:
The ability to predict the yield of a product has become critical, as short time-to-market
for volume productions is one of the most important objectives of any modern
semiconductor operation. The accuracy of prediction, however, depends on the accuracy
of the model and most importantly, the ability to extract the relevant defect characteristics
from the manufacturing line. Presently, the majority of the spot defect models used in the
industry assume that any spot defect on an IC die causes a functional failure in that die. A
variety of models assuming such dimensionless “point” representations of the defect have
been proposed for yield estimation. Such models tend to be pessimistic, as they do not
take into account the true nature of interaction between the defect and the elements of the
IC in its neighborhood. The problem with the concept of “point” defect models in that in
reality, not all defects affect the circuit equally. A larger defect is more likely to cause a
fault than a smaller defect; on the other hand, smaller defects are higher in number, and
may affect the circuit more. In addition, areas of the circuit with higher layout density
are affected more than sparse ones. Thus, the size distributions of all defect types and
their relationship with the actual circuit layout are extremely important for accurate yield
prediction. A methodology for extraction of the size distributions is therefore, absolutely
essential for any IC manufacturer. In addition, note that each manufacturer is likely to
have some specific unique characteristics for defects, generated by the available
manufacturing line. Therefore, a methodology enabling efficient extraction of
characteristics of spot defects, which is universal and flexible enough to handle a large
variety of technologies, has been recognized as an essential and inherent element of any
good yield prediction strategy able to handle modern design and manufacturing problems.
Terminology[1]:
Any unwanted particle or a droplet of liquid, which falls on the wafer during the
manufacturing process, is defined as contamination. If the contamination causes any
deformity in the form of extra or missing material in some layer of the circuit, then it is
called a defect. The term fault is used to describe functional misbehavior of the circuit
caused by such defects. It is important to note that not all contamination causes defects,
and only some of the defects cause faults. In addition, the shape and size of a defect is
often different from that of the contamination causing it.
Defect Size Distribution Model:
The main problem with the “point” defect is it’s dimensionless nature, which does not
allow for any interaction between the defect and the layout. This can be solved by
treating defects as disks of extra or missing material, which may occur in any layer of an
IC structure. Using this model, shorts in a conducting layer are assumed to be caused by
disks of extra material in that layer, while opens are assumed to be caused by disks of
missing conducting material. On the other hand, extra or missing material in the
insulating layer can cause opens or shorts respectively. These extra or missing material
defects in a layer are not of the same size, but they have some size distribution.
In addition, each defect is assumed to have the following parameters: (a). Size
distribution, which specifies the variation in frequency between defects of different radii;
(b). Density, Doi, which specifies the frequency of occurrence of defects of type I; and
(c). Location, (x,y), which specifies the special location.
A number of studies have been made on modeling the defect size distribution of both
shorts and opens in an IC layer. The accuracy of these models depends largely on the
accuracy of the information available to the user. One specific model, which has been
widely used in the industry, has been chosen. In this model, the size distribution for
defects of types I (which may be extra or missing material defects in some layer of the IC
are described by a function (see Fig 1).
where X0i and pi are the parameters of the model. The value of X0i in this model is a very
small number compared to the existing spacing and width of the layer. Both of these
parameters X0i and pi will have different values for shorts and opens. In addition, these
parameters will also vary between different fabrication facilities.
Fig1: A typical defect size distribution function[1].
Test Structures for Defect Characteristics:
The test vehicles used in the industry to obtain defect characteristics are predominantly
snake and comb structures. An example of a device, so called comb structure-used
commonly in the industry to detect shorts is shown in Fig.2. A simple continuity test is
used to detect shorts, which of course cannot determine the size of the defect that caused
the short. Similarly, Fig. 3 shows a snake structure used for detection of opens.
Again, a simple continuity test is used to check for opens, providing data only in terms of
“point” defects. Thus the main drawback of snake and comb structures is that they only
indicate the existence of a short or an open, but do not give any knowledge about the size
distribution of the defects. In order to solve this problem, special test structures are
needed, which categorize the defects not only as shorts or opens, but also give some
information about the size of the defects. More importantly, there is a necessity to
develop algorithms which extract the defect size distributions from this test structure
data. These test structures and the extraction algorithms together should form a complete
defect size extraction strategy, which can be used by the manufacturer to characterize the
shorts and opens in an IC layer.
Fig2: Detection of shorts using a “comb” structure[1].
Fig 3: Detection of opens using a “snake” structure[1].
One such special test structure in the Double Bridge Test Structure (DBTS). The DBTS
can be used to size both shorts and opens in the metal layer, and hence is used to
demonstrate the extraction algorithm for obtaining the size distributions of both shorts
and opens.
Double Bridge Test Structures:
This project estimates yield by classifying the defects into different classes and
calculating the mean yield of all the class. The classification of the defects into classes
depends on the number of lines it shorts or opens in a circuit. This classification can be
done with the help of test structures. Traditionally “snake” or “comb” structures were
used to study the characteristics of an open or a short respectively. These structures can
detect the presence of a short or an open in the circuit but it does not give any information
about the size of the defect. Thus these structures do not give the complete characteristic
of a defect. A double bridge test structure can give a good description of a defect.
A double bridge test structure can be obtained by laying meanders of polysilicon layer on
the oxide layer. A metal layer is then laid over the polysilicon layer except on the end-
wraps. If the resistance of both the end-wraps and the metal layer is exactly known, then
a thorough analysis can be done on the characteristics of the defects. The structure of a
double bridge test structure is shown below in Fig 4.
Fig 4: Double Bridge test structures[2].
The resistance between the terminals 1 and 2 of the test structure gives the total resistance
of the structure, while the resistance between the terminals 3 and 4 gives the resistance of
an end-wrap. Since the resistance due to the metal layer is much smaller when compared
to that of an end-wrap, it can be neglected. With this assumption the ratio between the
two resistances will be equal to the number of lines minus one in the test structure. The
test structures are built such that the spacing between them is equal to the minimum
acceptable distance allowed by the design rule chosen. This is done to analyze the worstcase scenario.
A short in the structure will decrease this ratio related to the number of lines shorted
because of the defect. If a defect shorts 3 lines in the structure, then the ratio between the
two resistances R12 and R34 will be reduced by a factor of 2. In general, a defect shorting
‘n’ lines in a structure reduces the ratio by n-1 times. Similar explanation can be given for
an open circuit case. Using this test structure, the defects can be classified in to different
classes depending on the number of lines shorted or opened. Histograms can be plotted,
the height of which gives the defect density of a defect of a particular radius.
Critical Area:
Not all the defects deposited on the chip cause a fault in the circuit. For example, a defect
that has a radius less than half of the spacing between two metal strips will not cause a
short between the two strips. Fig 5 gives a clear idea about the critical area. This
introduces a new technical term called ‘Critical Area’.
Fig 5: “Critical Area” concept[2].
Critical area of a circuit is that area between two layers of metal strips in an IC, where if
the center of the defect of radius r falls, will cause a short or open in the circuit. This area
varies with the radius of the defect and the spacing between metal strips in the layout.
The software used to place and route the circuit determines the spacing between the metal
strips of an IC. However, editing the technology file used by the software can change this
spacing. The yield of the circuit can be increased by increasing the spacing between the
metal strips.
The yield model can now be updated as


Y = exp   Acri (r ) Di (r )dr 


where Acri is the critical area and Di(r) is the defect density variation.
Critical Area Approximation:
Studies show that the critical area of a circuit can be approximated as two linear
functions. Fig 6 below shows the plot of the defect radius Vs critical area. It can be seen
that the critical area of the circuit increases with the defect radius until a certain point
after which it is almost constant with respect to defect radius. This is quite obvious, as
defects with bigger radius will definitely cause a failure in the circuit no matter where it
is centered. Such big defects are quite rare in the circuit. So the saturated region of the
curve can safely be neglected for analysis. So the critical area can be approximated with
that of the linearly increasing part of the curve.
Fig 6: Critical Area Vs Defect Radius[2].
The critical area is approximated to be a piecewise linear function. Using this
approximation the yield can be derived as


k * m1
Y = exp 
p 2 
 ( p  1)( p  2)r1 
where m1 is the slope of the curve and r1 is half the minimum spacing between the metal
lines. This formula can be rewritten as
k. Acr (r0 )


Y = exp 
p 2 
 ( p  1)( p  2)( r0  r1 )r1 
where, r0 is a point on the linear portion of the curve.
The standard cell yield can be enhanced by optimizing both the critical area and the
defect density of the circuit. The yield can be further enhanced by proper placement,
rotation of the transistors, optimizing the spacing etc.
References:
[1] Khare J.B, Maly W, Thomas M.E, “Extraction of defect size distributions in an IC
layer using Test Structure Data”, Dept. of Electr. & Computer Eng., Carnegie Mellon
Univ., Pittsburgh, PA, Semiconductor Manufacturing, IEEE Transactions on
On, pp.354-368, Aug 1994.
[2] Khare, J.B.; Daniels, B.J.; Campbell, D.M.; Thomas, M.E.; Maly, W, “Extraction of
Defect Characteristics for yield estimation using the double bridge test structure”,
VLSI Technology, Systems, and Applications, 1991, Proceedings of Technical Papers,
1991 International Symposium on, pp. 428 –432.