Download High voltage regulator and corresponding voltage regulation method

Europäisches Patentamt
(19)
European Patent Office
*EP000915408B1*
Office européen des brevets
(11)
EP 0 915 408 B1
EUROPEAN PATENT SPECIFICATION
(12)
(45) Date of publication and mention
of the grant of the patent:
19.02.2003 Bulletin 2003/08
(51) Int Cl.7:
G05F 1/00, G05F 1/46
(21) Application number: 97830575.3
(22) Date of filing: 05.11.1997
(54) High voltage regulator and corresponding voltage regulation method
Hochspannungsregelungsschaltung und entsprechendes Spannungsregelungsverfahren
Régulateur de haute tension et méthode de régulation de tension correspondante
(84) Designated Contracting States:
DE FR GB IT
(43) Date of publication of application:
12.05.1999 Bulletin 1999/19
(73) Proprietor: STMicroelectronics S.r.l.
• Golla, Carla
20099 Sesto S. Giovanni (Milano) (IT)
(74) Representative: Botti, Mario
Botti & Ferrari S.r.l.,
Via Locatelli, 5
20124 Milano (IT)
20041 Agrate Brianza MI (IT)
(56) References cited:
(72) Inventors:
EP 0 915 408 B1
• Ghilardelli, Andrea
20092 Cinisello B. (Milano) (IT)
• Brani, Francesco Maria
20144 Milano (IT)
FR-A- 2 681 180
US-A- 5 132 565
US-A- 5 530 640
US-A- 5 077 518
US-A- 5 162 668
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give
notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in
a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art.
99(1) European Patent Convention).
Printed by Jouve, 75001 PARIS (FR)
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EP 0 915 408 B1
Description
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sufficiently fast settling during transient phases,
such as the regulator triggering phase;
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low space requirements, i.e. reduced occupation of
silicon area.
Field of the Invention
[0001] This invention relates to a high voltage regulator.
[0002] The invention specifically relates to a high voltage regulator which is partly supplied by a boosted voltage and is adapted to deliver a regulated output voltage
on an output terminal, starting from a sampled voltage
obtained by dividing the regulated output voltage, which
regulator comprises at least a comparator element being supplied by a supply voltage and feedback connected to a divider of said regulated output voltage.
[0003] The invention also concerns a method of regulating a voltage obtained from a boosted voltage.
[0004] The invention particularly, but not exclusively,
relates to a high voltage regulator for a memory of the
'flash' type, and the description which follows is given in
connection with this field of application for simplicity of
illustration only.
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Background Art
[0005] As is well known, many applications concerning electronic circuits integrated in a semiconductor require that voltages above the supply voltage Vcc and
below the ground voltage reference GND be generated.
This requirement is most stringent with devices which
are supplied by a low voltage, as in the current trend for
many electronic devices among which are electrically
programmable and erasable non-volatile memories.
[0006] A boosted voltage is usually generated by
means of a voltage multiplier or "booster" circuit, which
is purposely formed within the integrated circuit itself.
[0007] The booster circuit output is not at a regulated
value but depends to supply voltage, temperature, output current, and process factors.
[0008] In such cases, it becomes necessary to
smooth the output voltage Vout by means of a purposely
provided regulator circuit. In particular, a regulator for a
voltage multiplier circuit of the charge pump type, i.e. a
high voltage regulator, must be designed with high accuracy criteria because charge pump circuits can only
supply limited value currents.
[0009] Basic requirements for a regulator of high voltages generated by a booster circuit of the charge pump
type are:
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low current consumption by the charge pump booster circuits which supply the high voltage to be regulated;
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high precision, especially as regards absence of
overshoot and ripples in the regulated voltage, and
its independence of the parasitic effects that are
typical of high voltages;
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[0010] A high voltage regulator 1 according to the prior art is shown schematically in Figure 1 appended hereto.
[0011] The high voltage regulator 1 is partly supplied
by a boosted voltage PUMPOUT generated by a charge
pump circuit which supplies a high voltage at a small
current capacity.
[0012] The output voltage Vout is regulated by resistive division of the boosted voltage PUMPOUT.
[0013] In this way, an output voltage Vout can be obtained for the high voltage regulator 1.
[0014] The voltage regulator 1 comprises a resistive
divider consisting of two resistive elements R1 and R2,
connected between an output terminal OUT and a
ground voltage reference GND. The central connection
node X of the resistive elements R1 and R2 is connected
to a non-inverting input terminal of a comparator element 2 having an inverting input terminal connected to
an input terminal IN of the high voltage regulator 1 and
a supply terminal connected to a supply voltage reference Vdd.
[0015] The input terminal IN of the high voltage regulator 1 receives a reference voltage Vref of constant value, usually for utilisation by several circuits in the same
device.
[0016] The comparator element 2 also has an output
terminal connected to the supply terminal of a drive transistor M1.
[0017] The drive transistor M1, specifically one of the
NMOS type, has its source terminal connected to the
ground voltage reference GND and its drain terminal
connected to the control gate terminal of an output transistor M2, itself connected between the boosted voltage
reference PUMPOUT and the output terminal OUT of
the high voltage regulator 1.
[0018] The high voltage regulator 1 further includes a
load transistor M3, specifically one of the PMOS type,
which is connected between the boosted voltage reference PUMPOUT and the control gate terminal of the
output transistor M2 and has its control gate terminal
connected to the ground voltage reference GND. This
load transistor M3 has the n-well terminal connected to
its source terminal and, hence, to the boosted voltage
reference PUMPOUT.
[0019] The regulated output voltage Vout is sampled
by the resistive divider of the high voltage regulator 1,
which then provides a feedback of the same. Therefore,
the value of this regulated output voltage Vout will be
dependent on both the value of the reference voltage
Vref and the ratio of the resistive divider R1, R2.
[0020] While achieving its objective, this solution is
less than fully satisfactory and has certain drawbacks.
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EP 0 915 408 B1
[0021] A major problem originates from the resistive
divider R1, R2.
[0022] First, to conform with the above requirement
for the charge pump booster circuit supplying the boosted voltage PUMPOUT to have a low current consumption, this resistive divider, and particularly the combined
resistances of the resistors R1 and R2, should be rather
large (in the MΩ range).
[0023] However, the use of a resistive divider of this
size clashes with the other requirements set forth above
for the high voltage regulator 1, namely precision,
speed, and low space occupation. In fact, to provide an
integrated resistor, there are essentially two methods
that can be used:
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formation in an n+ diffusion;
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formation in an n-well.
[0024] Actually, in view of the size (in the MΩ range)
involved, only the last-mentioned method can be used
for forming the resistive divider of the prior art high voltage regulator 1, since the n-well of an integrated circuit
has a higher specific resistivity than n+ diffusions. An nwell resistor is shown schematically in Figure 2.
[0025] Unfortunately, resistors formed in n-wells give
rise to two important problems:
1. They exhibit a high parasitic capacitance Cpar
toward the substrate layer of the integrated circuit.
2. They exhibit a varying resistance, dependent in
particular on the voltages applied across them, due
to the depleted reverse-biases area that exists between the n-well and the substrate.
[0026] Referring to the high voltage regulator 1 shown
in Figure 1, the parasitic capacitance associated with a
resistive divider so formed causes delayed following of
a divided voltage Vsample at the central connection
node X of the resistive elements R1 and R2 with respect
to variations occurring in the regulated output voltage
Vout.
[0027] This delay reflects in a slowed settling of the
output voltage Vout, as well as overshooting and rippling
thereof, in contrast with the requirements set above for
the high voltage regulator 1.
[0028] In addition, the varying character of the resistance of the divider formed in the n-well makes it difficult
to obtain a desired value for the regulated output voltage
Vout. In fact, this varying resistance is difficult to model
and reproduce. Thus, the high voltage regulator 1 incorporating such a divider is unsuitable to meet the aforementioned requirements.
[0029] The underlying technical problem of this invention is to provide a high voltage regulator, in particular
for voltages supplied by booster circuits, which exhibits
low current consumption and high precision features, as
well as sufficient speed during the transient phases, with
no overshoot and ripples, and reduced space requirements. In this way, the requirements for such regulators
can be met and the drawbacks besetting the prior art
regulators overcome.
Summary of the Invention
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[0030] The idea of solution behind this invention is
one of using a diode type of divider connected to an output voltage reference to be regulated and to a varying
reference voltage.
[0031] Based on this idea of solution, the technical
problem is solved by a high voltage regulator as previously indicated and defined in the characterising portion
of Claim 1.
[0032] The problem is also solved by a method of regulating a voltage obtained from a boosted voltage as
previously indicated and defined in the characterising
portion of Claim 11.
[0033] The features and advantages of a high voltage
regulator according to the invention will be apparent
from the following description of embodiments thereof,
given by way of non-limitative examples with reference
to the accompanying drawings.
Brief Description of the Drawings
[0034]
In the drawings:
30
Figure 1 shows in schematic form a high voltage
regulator including a resistive divider according to
the prior art;
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Figure 2 is a detail view of a detail of the regulator
in Figure 1;
Figure 3 shows in schematic form a high voltage
regulator including a diode divider according to the
invention;
Figure 4 shows a modified embodiment of the high
voltage regulator according to the invention.
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Detailed Description
[0035] Referring in particular to Figure 3, generally
and schematically shown at 3 is a high voltage regulator
according to the invention. Corresponding circuit elements and signals, described in connection with the prior art high voltage regulator 1, will be denoted by the
same alphanumerical references.
[0036] The high voltage regulator 3 is partly supplied
by a boosted voltage PUMPOUT, generated by a charge
pump circuit (not shown) which supplies a high voltage
at a small current capacity. The high voltage regulator
3 has an input terminal IN receiving a varying reference
voltage Vref_v, and an output terminal OUT delivering
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EP 0 915 408 B1
a regulated output voltage Vout.
[0037] The output voltage Vout is regulated by having
it divided by a diode divider 4.
[0038] The diode divider 4 comprises a plurality of diodes D1, D2,..., Dn, D1', D2',..., Dn' connected between
the output terminal OUT and a ground voltage reference
GND. The diode divider 4 is functionally split into first 5
and second 6 legs respectively comprising first and second diode pluralities D1, D2,..., Dn and D1', D2',..., Dn'
which are connected together at a central connection
node Y.
[0039] The central connection node Y is connected to
a non-inverting input terminal of a comparator element
2 which has an inverting input terminal connected to the
input terminal IN of the high voltage regulator 1 and a
supply terminal connected to a supply voltage reference
Vdd, similar as the prior art high voltage regulator 1.
[0040] The comparator element 2 also has an output
terminal connected to the control terminal of a drive transistor M1 which has its source terminal connected to the
ground voltage reference GND and its drain terminal
connected to the control terminal of an output transistor
M2, itself connected between the boosted voltage reference PUMPOUT and the output terminal OUT of the
high voltage regulator 3.
[0041] The high voltage regulator 3 further comprises
a load transistor M3, specifically one of the PMOS type,
which is connected between the boosted voltage reference PUMPOUT and the control terminal of the output
transistor M2 and has its control terminal connected to
the ground voltage reference GND. This load transistor
M3 has an n-well terminal connected to the source terminal and, hence, to the boosted voltage reference
PUMPOUT.
[0042] The regulated output voltage Vout is sampled
by the resistive divider of the high voltage regulator 3 at
the central connection node X. The comparator element
2 in combination with the transistors M1, M2 and M3
then provide a negative feedback of the sampled voltage Vsample.
[0043] Advantageously in this invention, the comparator element 2 basically comprises an operational amplifier or a simple differential. In either cases, this operational amplifier or simple differential is supplied by the
supply voltage Vdd and, accordingly, can draw large
amounts of current from the supply voltage reference
Vdd, which makes it specially fast.
[0044] On the other hand, the portion which includes
the drive transistor M1, output transistor M2, and load
transistor M3 is supplied by the boosted voltage
PUMPOUT, i.e. a higher voltage than the supply voltage
Vdd.
[0045] It should be noted that the varying reference
voltage Vref_v may lie anywhere between the supply
voltage reference Vdd and the ground voltage reference
GND.
[0046] Advantageously in this invention, the diode divider 4 may comprise a plurality of diode-configured
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MOS transistors, which would exhibit none of the aforementioned problems affecting the resistive dividers of
conventional circuits.
[0047] This diode divider 4 may be formed of PMOS
transistors, as shown in Figure 3; likewise, it could be
formed of NMOS transistors or semiconductor junctions.
[0048] In all cases:
1. The diode-connected MOS transistors have a
high transresistance, and limited silicon area requirements for their formation.
2. The reduced area requirement eliminates the
presence of undesired parasitic capacitances,
thereby enabling the divided voltage Vsample at the
central connection node Y of the diode divider 4 to
most promptly follow the value of the voltage to be
regulated (Vout) at the output terminal OUT, thus
enhancing both accuracy and speed during transient phases and attenuating overshoot and ripples
of the high voltage regulator 3 as a whole.
3. The equivalent resistance of the diode divider 4
is in no way concerned with the voltages applied
across it, which means that the diode divider 4 will
be unaffected by parasitic effects typical of high voltages.
[0049] The value of the regulated output voltage Vout
of the high voltage regulator 3 according to the invention
is given as:
nu + nd
Vout = ------------------- Vref_v
nd
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(1)
where:
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4
nu, nd are the (obviously natural) numbers of diodes
included in the first 5 and second 6 legs of the diode
divider 4.
[0050] If, from a given value of the varying reference
voltage Vref_v, numbers (which obviously must be natural numbers) of diodes nu, nd included in the first 5 and
second 6 legs of the diode divider 4 can be found which
yield the desired value for the regulated output voltage
Vout, then the varying reference voltage Vref_v can be
used.
[0051] It should be noted that for the diode divider 4
to perform as expected, its diodes should be in the on
state. For this to occur, a voltage drop at least equal to
the diode threshold voltage VT is required across each
diode.
[0052] On the contrary, if no number pair nu, nd of diodes exist in the first and second legs 5 and 6 of the
diode divider 4 which can yield the desired value for the
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EP 0 915 408 B1
regulated output voltage Vout, the reference voltage
Vref_v should be changed. This does not represent a
problem, since for a value of the reference voltage
Vref_v lying, as already stated, between the value of the
supply voltage Vdd and the ground GND, a different
starting reference voltage Vref' can be derived therefrom, in a known manner by the skilled persons in the
art, which lies anywhere between the supply voltage
Vdd and the ground GND. A circuit adapted to provide
the new starting reference voltage Vref' is simple to design and allows the same supply voltage Vdd to be used
from which a large amount of current can be extracted.
[0053] Such a circuit, therefore, exhibits low current
consumption of the booster circuits, is highly accurate,
and shows no overshoot and ripples of the regulated
voltage, which will be free of parasitic effects typical of
high voltages and settle at a fast rate during the transient
phases.
[0054] The single drawback of such a circuit is a waste
of occupied area, especially where a new starting reference voltage Vref' with a high value is to be generated.
[0055] Figure 4 shows a modified embodiment 3' of
the high voltage regulator according to the invention. In
particular, this regulator 3' has the input terminal IN connected to the ground voltage reference GND and to the
inverting input of the comparator element 2, itself having
a non-inverting input connected to a central connection
node Z of the diode divider 4.
[0056] The comparator element 2, comprising in particular an operational amplifier being supplied by the
supply voltage Vdd, also has an output terminal OUT'.
[0057] In the modified embodiment of Figure 4, the diode divider 4 is connected between the varying reference voltage reference Vref_v and the output terminal
OUT of the high voltage regulator. This diode divider 4
comprises first 5 and second 6 diode legs connected
together at the central connection node Z.
[0058] Thus, the high voltage regulator 3' is a regulator of negative voltages. Its operation is similar to that
of the high voltage regulator 3 shown in Figure 3.
[0059] In particular, the output voltage Vout to be regulated is sampled through the diode divider 4, in this
case with respect to the varying reference voltage
Vref_v rather than to the ground GND. The voltage value
so sampled is then compared, by means of the operational amplifier 2, with the ground GND through a suitable feedback network (not shown) connected to the output terminal OUT'.
[0060] In summary, the high voltage regulator of this
invention provides a regulated output voltage from a
boosted voltage obtained, in particular, by means of a
charge pump booster circuit, through a diode divider. In
particular, the output voltage is regulated by comparison
of the sampled voltage from the divider with a varying
reference voltage or the ground.
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Claims
1.
A high voltage regulator partly supplied by a boosted voltage (PUMPOUT) and adapted to deliver a
regulated output voltage (Vout) on an output terminal (OUT), starting from a sampled voltage (Vsample) obtained by dividing the regulated output voltage (Vout), which regulator comprises at least a
comparator element (2) being supplied by a supply
voltage (Vdd) and feedback connected to a divider
(4) of said regulated output voltage (Vout), characterised in that said divider (4) is a diode divider
connected between the output terminal (OUT) and
a first comparison voltage reference (GND, Vref_v)
and has a central connection node (Y, Z) connected
to a non-inverting terminal of the comparator element (2), and that the high voltage regulator further
comprises an input terminal (IN), connected to a
second comparison voltage reference (Vref_v,
GND) and to an inverting terminal of the comparator
element (2) incorporated to the high voltage regulator (3).
2.
A high voltage regulator according to Claim 1, characterised in that said diode divider (4) comprises
first and second legs (5, 6) of diodes (D1,D2,...,Du,
D1',D2',...,Dd') connected in series with one another at said central connection node (Y, Z), said first
leg (5) of diodes being connected between the output terminal (OUT) and the central connection node
(Y, Z) of said divider, and said second leg (6) being
connected between the central connection node (Y,
Z) and the first comparison voltage reference (GND,
Vref_v).
3.
A high voltage regulator according to Claim 2, characterised in that the second leg (6) of diodes is
connected between the central connection node (Y)
and a ground voltage reference (GND), and that the
input terminal (IN) of the high voltage regulator (3)
is connected to a varying voltage reference
(Vref_v).
4.
A high voltage regulator according to Claim 1, characterised in that the comparator element (2) comprises essentially an operational amplifier or a simple differential.
5.
A high voltage regulator according to Claim 4, characterised in that only said operational amplifier or
simple differential included in the comparator element (2) is supplied by the supply voltage (Vdd).
6.
A high voltage regulator according to Claim 1, characterised in that said comparator element (2) has
an output terminal connected to the output terminal
(OUT) of the high voltage regulator (3) through a
series of the drive transistor (M1), an output tran-
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EP 0 915 408 B1
sistor (M2), and a load transistor (M3), said drive
transistor (M1) having its control gate terminal connected to the output terminal of the operational amplifier (2), its source terminal connected to the
ground voltage reference (GND), and its drain terminal connected to the control gate terminal of the
output transistor (M2), said output transistor (M2)
being connected between the boosted voltage reference (PUMPOUT) and the output terminal (OUT)
of the high voltage regulator (3), and said load transistor (M3) being connected between the boosted
voltage reference (PUMPOUT) and the control gate
terminal of the output transistor (M2) and having its
control gate terminal connected to the ground voltage reference (GND).
7.
8.
A high voltage regulator according to any one of the
preceding claims, characterised in that the value
of the varying reference voltage (Vref_v) ranges
from the value of the supply voltage (Vdd) to the
ground value (GND).
A high voltage regulator according to Claim 2, characterised in that the second leg (6) of diodes is
connected between the central connection node (Z)
and a varying voltage reference (Vref_v), and that
the input terminal (IN) of the high voltage regulator
(3) is connected to a ground voltage reference
(GND).
comparison of said sampled voltage (Vsample)
with the second comparison voltage reference
(Vref_v, GND).
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9.
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13. A regulating method according to Claim 12, characterised in that the comparison of said sampled
voltage (Vsample) with said second comparison
voltage reference (Vref_v, GND) is performed by an
operational amplifier (2) being supplied a supply
voltage (Vdd) and feedback connected to said divider (4), the central connection node (Y, Z) of the
diode divider (4) being connected to a non-inverting
terminal of the operational amplifier (2).
14. A regulating method according to Claim 13, characterised by the step of comparing the sampled
voltage (Vsample) with a varying reference voltage
(Vref_v) supplied to an inverting input of the operational amplifier (2), said diode divider (4) being connected to said voltage to be regulated (Vout) and to
a ground voltage reference (GND).
15. A regulating method according to Claim 14, characterised in that, with said diode divider (4) comprising first and second legs (5, 6) of diodes
(D1,D2,...,Du,D1',D2',...,Dd') connected in series
with one another at said central connection node (Y,
Z), the value of the voltage to be regulated (Vout) is
obtained from the varying reference voltage
(Vref_v) by the following relation:
A high voltage regulator according to Claim 1, characterised in that the diode divider (4) comprises a
plurality of MOS transistors in diode configuration.
10. A high voltage regulator according to Claim 1, characterised in that the diode divider (4) comprises a
plurality of semiconductor junctions.
11. A high voltage regulator according to any one of the
preceding claims, characterised in that said
boosted voltage (PUMPOUT) is generated by a
booster circuit adapted to supply a high voltage at
a small current capacity.
12. A method of regulating a voltage (Vout) derived
from a boosted voltage (PUMPOUT) and adapted
to be performed in a high voltage regulator according to any one of claims 1-11, characterised in that
it comprises the following steps:
nu + nd
Vout = --------------------- Vref_v
nd
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where:
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obtaining the sampled voltage (Vsample) as
the voltage value at the central connection
node (Y, Z) of the diode type of divider (4) connected to the reference of the voltage to be regulated (Vout) and to the first comparison voltage reference (GND, Vref_v);
(1)
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regulating said voltage (Vout) according to the
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nu, nd are the numbers of diodes included in the
first and second legs (5, 6) of the diode divider
(4).
16. A regulating method according to Claim 15, characterised in that, if the numbers (nu, nd) of diodes
included in the first and second legs (5, 6) of the
diode divider (4), said numbers being of necessity
natural numbers, can be found from a value whichever of the varying reference voltage (Vref_v), then
a desired value of the regulated voltage is obtained.
17. A regulating method according to Claim 15, characterised in that, starting from a given number (nu,
nd) of diodes included in the first and second legs
(5, 6) of the diode divider (4), the varying reference
voltage (Vref_v) can be varied to obtain a desired
value of the regulated voltage.
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EP 0 915 408 B1
Patentansprüche
1.
2.
3.
Hochspannungsregulator, der teilweise mit einer
angehobenen Spannung (PUMPOUT) beliefert
wird und der dazu ausgebildet ist, eine regulierte
Ausgangsspannung (Vout) an einen Ausgangsanschluß (OUT) zu liefern, startend von einer abgetasteten Spannung (Vsample), die durch Teilen der
regulierten Ausgangsspannung (Vout) erhalten
wird, wobei der Regulator wenigstens ein Komparatorelement (2) aufweist, dem eine Versorgungsspannung (Vdd) zugeführt wird, und eine Rückkopplung, die mit einem Teiler (4) der regulierten
Ausgangsspannung (Vout) verbunden ist, dadurch
gekennzeichnet, daß der Teiler (4) ein Diodenteiler ist, der zwischen den Ausgangsanschluß (OUT)
und eine erste Vergleichsspannungsreferenz
(GND, Vref_v) geschaltet ist und einen Mittelverbindungsknoten (Y, Z) aufweist, der mit einem nichtinvertierenden Anschluß des Komparatorelementes verbunden ist, und daß der
Hochspannungsregulator außerdem einen Eingangsanschluß (IN) aufweist, der mit einer zweiten
Vergleichsspannungsreferenz (Vref_v, GND) und
einen invertierenden Anschluß des in dem Hochspannungsregulator (3) enthaltenen Kornparatorelementes (2) angeschlossen ist.
Hochspannungsregulator nach Anspruch 1, dadurch gekennzeichnet, daß der Diodenteiler (4)
einen ersten und zweiten Schenkel (5, 6) von Dioden (D1, D2,...., Du, D1', D2' Dd') aufweist, die in
Reihenschaltung zueinander in einem Zentralverbindungsknoten (Y, Z) verbunden sind, wobei der
erste Schenkel (5) der Dioden zwischen den Ausgangsanschluß (OUT) und den Zentralverbindungsknoten (Y, Z) des Teilers geschaltet ist und
der zweite Schenkel (6) zwischen den Zentralverbindungsknoten (Y, Z) und die erste Vergleichsspannungsreferenz (GND, Vref_v) geschaltet ist.
Hochspannungsregulator nach Anspruch 2, dadurch gekennzeichnet, daß der zweite Schenkel
(6) von Dioden zwischen den Zentralverbindungsknoten (Y) und eine Massespannungsreferenz
(GND) geschaltet ist und daß der Eingangsanschluß (IN) des Hochspannungsregulators (3) mit
einer veränderlichen Spannungsreferenz (Vref_v)
verbunden ist.
bzw. das in dem Komparatorelement (2) enthalten
ist, mit der Versorgungsspannung (Vdd) beliefert
wird.
5
Hochspannungsregulator nach Anspruch 1, dadurch gekennzeichnet, daß das Komparatorelement (2) einen Ausgangsanschluß aufweist, der mit
dem Ausgangsanschluß (OUT) des Hochspannungsregulators (3) über Reihenschaltung aus dem
Treibertransistor (M1), einem Ausgangstransistor
(M2) und einem Lasttransistor (M3) verbunden ist,
wobei von dem Treibertransistor (M1) ein Steuergateanschluß mit dem Ausgangsanschluß des
Operationsverstärkers (2), ein Sourceanschluß mit
der Massespannungsreferenz (GND) und ein
Drainanschluß mit dem Steuergateanschluß des
Ausgangstransistors (M2) verbunden sind, wobei
der Ausgangstransistor (M2) zwischen die angehobene Spannungsreferenz (PUMPOUT) und den
Ausgangsanschluß (OUT) des Hochspannungsregulators (3) geschaltet ist und der Lasttransistor
(M3) zwischen die angehobene Spannungsreferenz (PUMPOUT) und den Steuergateanschluß
des Ausgangstransistors (M2) geschaltet ist, wobei
dessen Steuergateanschluß mit der Massespannungsreferenz (GND) verbunden ist.
7.
Hochspannungsregulator nach einem der vorausgehenden Ansprüche, dadurch gekennzeichnet,
daß der Wert der veränderlichen Referenzspannung (Vref_v) im Bereich von dem Wert der Versorgungsspannung (Vdd) bis zum Massewert (GND)
liegt.
8.
Hochspannungsregulator nach Anspruch 2, dadurch gekennzeichnet, daß der zweite Schenkel
(6) der Dioden zwischen den Zentralverbindungsknoten (Z) und eine variable Spannungsreferenz
(Vref_v) geschaltet ist und daß der Eingangsanschluß (IN) des Hochspannungsregulators (3) mit
einer Massespannungsreferenz (GND) verbunden
ist.
9.
Hochspannungsregulator nach Anspruch 1, dadurch gekennzeichnet, daß der Diodenteiler (4)
eine Mehrzahl MOS-Transistoren in Dioden-Konfiguration aufweist.
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30
35
40
45
Hochspannungsregulator nach Anspruch 1, dadurch gekennzeichnet, daß das Komparatorelement (2) im wesentlichen einen Operationsverstärker oder ein einfaches Differenzglied aufweist.
55
5.
6.
10
50
4.
12
Hochspannungsregulator nach Anspruch 4, dadurch gekennzeichnet, daß lediglich der Operationsverstärker oder das einfache Differenzglied, der
7
10. Hochspannungsregulator nach Anspruch 1, dadurch gekennzeichnet, daß der Diodenteiler (4)
eine Mehrzahl Halbleiterübergänge aufweist.
11. Hochspannungsregulator nach einem der vorausgehenden Ansprüche, dadurch gekennzeichnet,
daß die angehobene Spannung (PUMPOUT) durch
eine Booster-Schaltung erzeugt ist, die dazu ausgebildet ist, eine hohe Spannung mit einer kleinen
Stromkapazität zu liefern.
13
EP 0 915 408 B1
12. Verfahren zum Regulieren einer Spannung (Vout),
die von einer angehobenen Spannung (PUMPOUT) abgeleitet wird und dazu geeignet ist, in einem Hochspannungsregulator nach einem der Ansprüche 1 bis 11 ausgeführt zu werden, gekennzeichnet durch folgende Schritte:
-
Erhalten der abgetasteten Spannung (Vsample) als der Spannungswert an dem Zentralverbindungsknoten (Y, Z) des Diodentypteilers (4),
der mit der Referenz der zu regulierenden
Spannung (Vout) und mit der ersten Vergleichsspannungsreferenz (GND, Vref-v) verbunden
ist;
odenteilers (4) enthalten sind.
5
10
15
-
Regulieren der Spannung (Vout) entsprechend
dem Vergleich der abgetasteten Spannung
(Vsample) mit der zweiten Vergleichsspannungsreferenz (Vref_v, GND).
20
13. Regulierungsverfahren nach Anspruch 12, dadurch gekennzeichnet, daß der Vergleich der abgetasteten Spannung (Vsample) mit der zweiten
Vergleichsspannungsreferenz (Vref_v; GND) mit
einem Operationsverstärker (2) durchgeführt wird,
dem eine Versorgungsspannung (Vdd) zugeführt
wird und der eine Rückkopplungsverbindung zu
dem Teiler (4) aufweist, wobei der Zentralverbindungsknoten (Y, Z) des Diodenteilers (4) mit einem
nicht-invertierenden Anschluß des Operationsverstärkers (2) verbunden ist.
14. Regulierungsverfahren nach Anspruch 13, gekennzeichnet durch den Schritt des Vergleichens
der abgetasteten Spannung (Vsample) mit einer
veränderlichen Referenzspannung (Vref_v), die einem invertierenden Eingang des Operationsverstärkers (2) zugeführt wird, wobei der Diodenteiler
(4) mit der zu regulierenden Spannung (Vout) und
mit einer Massespannungsreferenz (GND) verbunden ist.
15. Regulierungsverfahren nach Anspruch 14, dadurch gekennzeichnet, daß in dem Fall, in dem
der Diodenteiler (4) erste und zweite Schenkel (5,
6) von Dioden (D1, D2,...; Du, D1', D2', ...., Dd') aufweist, die in Reihenschaltung zueinander in einem
Zentralverbindungsanschluß (Y, Z) verbunden sind,
der Wert der zu regulierenden Spannung (Vout) von
der veränderlichen Referenzspannung (Vref_v)
durch folgende Beziehung erhalten wird:
nu + nd
Vout = ------------------- Vref_v
nd
14
16. Regulierungsmethode nach Anspruch 15, dadurch
gekennzeichnet, daß dann,
wenn die Zahlen (nu, nd) der in dem ersten Schenkel
und in dem zweiten Schenkel (5, 6) des Diodenteilers (4) enthaltenen Dioden, wobei die Zahlen notwendigerweise natürliche Zahlen sind, von welchem Wert der veränderlichen Referenzspannung
(Vref_v) auch immer gefunden werden können, ein
gewünschter Wert der regulierten Spannung erhalten wird.
17. Regulierungsverfahren nach Anspruch 15, dadurch gekennzeichnet, daß, beginnend von einer
gegebenen Zahl von Dioden, die sich in dem ersten
Schenkel und in dem zweiten Schenkel (5, 6) des
Diodenteils (4) befinden, die veränderliche Referenzspannung (Vref_v) verändert werden kann, um
einen gewünschten Wert der regulierten Spannung
zu erhalten.
Revendications
25
1.
Un régulateur haute tension partiellement alimenté
par une tension survoltée (PUMPOUT) et adapté
pour délivrer une tension de sortie régulée (Vout)
sur une borne de sortie (OUT), à partir d'une tension
échantillonnée (Vsample) obtenue en divisant la
tension de sortie régulée (Vout), régulateur qui
comprend au moins un élément comparateur (2) alimenté par une tension d'alimentation (Vdd) reliée
avec rétroaction à un diviseur (4) de la tension de
sortie régulée (Vout), caractérisé en ce que le diviseur (4) est un diviseur à diodes relié entre la borne de sortie (OUT) et une première référence de
tension de comparaison (GND, Vref_v) et possède
un noeud de liaison central (Y, Z) relié à une borne
non inverseuse de l'élément comparateur, et en ce
que le régulateur haute tension comprend en outre
une bome d'entrée (IN), reliée à une seconde référence de tension de comparaison (Vref_v, GND) et
à une borne inverseuse de l'élément comparateur
(2) incorporé au régulateur haute tension (3).
2.
Un régulateur haute tension selon la revendication
1, caractérisé en ce que le diviseur à diodes (4)
comprend une première et une seconde branche
(5,6) de diodes (D1, D2 ... Du, D1', D2' ... Dd') montées en série les unes avec les autres au noeud de
liaison central (Y, Z), la première branche (5) de diodes étant montée entre la borne de sortie (OUT) et
le noeud de liaison central (Y, Z) du diviseur, et la
seconde branche (6) étant montée entre le noeud
de liaison central (Y, Z) et la première référence de
tension de comparaison (GND, Vref_v).
30
35
40
45
50
(1)
55
wobei nu, nd die Zahlen von Dioden sind, die in dem
ersten und in dem zweiten Schenkel (5, 6) des Di-
8
15
3.
4.
5.
EP 0 915 408 B1
Un régulateur haute tension selon la revendication
2, caractérisé en ce que la seconde branche (6)
de diodes est reliée entre le noeud de liaison central
(Y) et une référence de tension de masse (GND),
en ce que la borne d'entrée (IN) du régulateur haute
tension est reliée à une référence de tension variable (Vref_v).
Un régulateur haute tension selon la revendication
1, caractérisé en ce que l'élément comparateur (2)
comprend essentiellement un amplificateur opérationnel ou un différentiel simple.
Un régulateur haute tension selon la revendication
4, caractérisé en ce que seulement l'amplificateur
opérationnel ou différentiel simple inclus dans l'élément comparateur (2) est alimenté par la tension
d'alimentation (Vdd).
10. Un régulateur haute tension selon la revendication
1, caractérisé en ce que le diviseur à diodes (4)
comprend une pluralité de jonctions semiconductrices.
5
10
15
11. Un régulateur haute tension selon l'une quelconque
des revendications précédentes, caractérisé en ce
que la tension survoltée (PUMPOUT) est produite
par un circuit survolteur adapté pour délivrer une
haute tension à une capacité à faible courant.
12. Un procédé de régulation d'une tension (Vout) dérivée d'une tension survoltée (PUMPOUT) et adapté pour être mis en oeuvre dans un régulateur haute
tension selon l'une quelconque des revendications
1, à 11, caractérisé en ce qu'il comprend les étapes suivantes :
-
6.
Un régulateur haute tension selon la revendication
1, caractérisé en ce que l'élément comparateur (2)
possède une borne de sortie reliée à la borne de
sortie (OUT) du régulateur haute tension (3) au travers d'un ensemble série formé par le transistor de
pilotage (M1), un transistor de sortie (M2) et un transistor de charge (M3), le transistor de pilotage (M1)
ayant sa borne de grille de commande relié à la home de sortie de l'amplificateur opérationnel (2), sa
borne de source reliée à la référence de tension de
masse (GND) et sa borne de drain reliée à la bome
de grille de commande du transistor de sortie (M2),
le transistor de sortie (M2) étant relié entre la référence de tension survolté (PUMPOUT) et la borne
de sortie (OUT) du régulateur haute tension (3), et
le transistor de charge (M3) étant relié entre la référence de tension survolté (PUMPOUT) et la borne
de grille de commande du transistor de sortie (M2)
et ayant sa borne de grille de commande reliée a
référence de tension de masse (GND).
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25
30
35
-
obtention de la tension échantillonnée (Vsample) comme valeur de tension sur le noeud de
liaison central (Y, Z) du diviseur du type à diodes (4) relié à la référence de la tension à réguler (Vout) et à la première référence de tension de comparaison (GND, Vref_v) ;
régulation de ladite tension (Vout) en fonction
de la comparaison de la tension échantillonnée
(Vsample) avec une seconde référence de tension de comparaison (Vref_v, GND).
13. Un procédé de régulation selon la revendication 12,
caractérisé en ce que la comparaison de la tension échantillonnée (Vsample) avec la seconde référence de tension de comparaison (Vref_v, GND)
est effectuée par un amplificateur opérationnel (2)
qui est alimenté par une tension d'alimentation
(Vdd) et relié avec rétroaction au diviseur (4), le
noeud de liaison central (Y, Z) du diviseur à diodes
(4) étant relié à une borne non inverseuse de l'amplificateur opérationnel (2).
40
7.
8.
9.
Un régulateur haute tension selon l'une quelconque
des revendications précédentes, caractérisé en ce
que la valeur de la tension de référence variable
(Vref_v) s'étend de la valeur de la tension d'alimentation (Vdd) à la valeur de la masse (GND).
Un régulateur haute tension selon la revendication
2, caractérisé en ce que la seconde branche (6)
de diodes est reliée entre le noeud de liaison central
(Z) et une référence de tension variable (Vref_v), et
en ce que la borne d'entrée (IN) du régulateur haute
tension (3) est relié à une référence de tension de
masse (GND).
Un régulateur haute tension selon la revendication
1, caractérisé en ce que le diviseur à diodes (4)
comprend une pluralité de transistors MOS configurés en diode.
45
50
55
9
14. Un procédé de régulation selon la revendication 13,
caractérisé par l'étape de comparaison de la tension échantillonnée (Vsample) à une tension de référence variable (Vref_v) délivrée à une entrée inverseuse de l'amplificateur opérationnel (2), le diviseur à diodes (4) étant relié à la tension à réguler
(Vout) et à une référence de tension de masse
(GND).
15. Un procédé de régulation selon la revendication 14,
caractérisé en ce que, le diviseur à diodes (4)
comprenant une première et une seconde branche
(5,6) de diodes (D1, D2 ... Du, D1', D2' ... Dd') montées en série les unes avec les autres au noeud de
liaison central (Y, Z), la valeur de la tension à réguler
(Vout) est obtenûe à partir de la tension de référence variable (Vref_v) d'après la relation suivante :
17
nu + nd
Vout = ------------------- Vref_v
nd
EP 0 915 408 B1
(1)
où :
5
nu, nd sont les nombres de diodes comprises
dans la première et la seconde branche (5, 6)
du diviseur à diodes (4).
10
16. Un procédé de régulation selon la revendication 15,
caractérisé en ce que, si les nombres (nu, nd) de
diodes compris dans la première et la seconde
branche (5,6) du diviseur à diodes (4), ces nombres
étant nécessairement des entiers naturels, peuvent
être déterminés à partir d'une valeur quelle que soit
la tension de référence variable (Vref_v), alors on
obtient une valeur souhaitée de la tension régulée.
17. Un procédé de régulation selon la revendication 15,
caractérisé en ce que, à partir d'un nombre donné
(nu, nd) de diodes comprises dans la première et la
seconde branche (5,6) du diviseur à diodes (4), on
peut faire varier la tension de référence variable
(Vref_v) pour obtenir une valeur souhaitée de la tension régulée.
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25
30
35
40
45
50
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10
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13