Download AP7016

FT/GN/68/00/21.04.15
SRI VENKATESWARA COLLEGE OF ENGINEERING
COURSE DELIVERY PLAN - THEORY
Page 1 of 6
LP: AP7016
Department of ELECTRONICS AND COMMUNICATION ENGINEERING
M.E
: ECE
PG Specialisation
: Applied Electronics
Sub. Code / Sub. Name
: AP7016 - SYSTEM ON CHIP DESIGN
Unit
:I
Rev. No: 00
Regulation: 2013
Date: 30-06-2015
Unit Syllabus: LOGIC GATES
Introduction; Combinational Logic Functions; Static Complementary Gates; Switch Logic; Alternative
Gate Circuits; Low-Power Gates; Delay Through Resistive Interconnect; Delay Through Inductive
Interconnect.
Objective: To learn about designing various logic gates with minimum size, spacing, and parasitic
values.
Session
No *
Topics to be covered
Ref
Teaching Aids
1.
Introduction: CMOS Technology-power consumption – design and
testability - IC design techniques – design hierarchy – computer aided
design
1-Ch.1; Pg.1-31;
PPT, BB
2.
Fabrication process – Wires and Vias – design rules
1-Ch.2; Pg. 34-74
PPT, BB
3.
Combinational Logic Functions - Static Complementary Gates
1-Ch.3; Pg.112-126
PPT, BB
4.
Static Complementary Gates
1-Ch.3; Pg.126-143
PPT, BB
5.
Switch Logic - Alternative Gate Circuits
1-Ch.3; Pg.143-148
PPT, BB
6.
Alternative Gate Circuits
1-Ch.3; Pg.149-154
PPT, BB
7.
Low-Power Gates
1-Ch.3; Pg.154-160
PPT, BB
8.
Delay Through Resistive Interconnect
1-Ch.3; Pg.160-168
PPT, BB
1-Ch.3; Pg.169-177
PPT, BB
Delay Through Resistive Interconnect - Delay Through Inductive
Interconnect
Content beyond syllabus covered (if any): NIL
9.
Course Outcome 1:
To design, logic gates with minimum size, spacing, and parasitic values.
* Session duration: 50 minutes
FT/GN/68/00/21.04.15
SRI VENKATESWARA COLLEGE OF ENGINEERING
COURSE DELIVERY PLAN - THEORY
Page 2 of 6
Sub. Code / Sub. Name: AP7016 - SYSTEM ON CHIP DESIGN
Unit : II
Unit Syllabus: COMBINATIONAL LOGIC NETWORKS
Introduction - Standard Cell-Based Layout – Simulation - Combinational Network Delay - Logic and
interconnect Design - Power Optimization - Switch Logic Networks - Combinational Logic Testing
Objective: To design combinational logic functions and analyze delay and testability properties of
interconnect and gates.
Session
No *
Topics to be covered
Ref
Teaching Aids
10.
Introduction - Standard Cell-Based Layout
1-Ch.4; Pg.185-196;
PPT, BB
11.
Standard Cell-Based Layout - Simulation
1-Ch.4; Pg.196-202;
PPT, BB
12.
Combinational Network Delay
1-Ch.4; Pg.202-208;
PPT, BB
13.
Combinational Network Delay
1-Ch.4; Pg.209-218;
PPT, BB
14.
Logic and interconnect Design
1-Ch.4; Pg.219-224;
PPT, BB
15.
Logic and interconnect Design
1-Ch.4; Pg.224-229;
PPT, BB
CAT - 1
16.
Power Optimization
1-Ch.4; Pg.229-233;
PPT, BB
17.
Switch Logic Networks
1-Ch.4; Pg.233-237;
PPT, BB
18.
Combinational Logic Testing
1-Ch.4; Pg.237-244;
PPT, BB
Content beyond syllabus covered (if any): NIL
Course Outcome 2:
To design combinational logic machines with optimum power.
* Session duration: 50 mins
FT/GN/68/00/21.04.15
SRI VENKATESWARA COLLEGE OF ENGINEERING
COURSE DELIVERY PLAN - THEORY
Page 3 of 6
Sub. Code / Sub. Name: AP7016 - SYSTEM ON CHIP DESIGN
Unit : III
Unit Syllabus: SEQUENTIAL MACHINES
Introduction - Latches and Flip-Flops - Sequential Systems and Clocking Disciplines - Sequential
System Design - Power Optimization - Design Validation - Sequential Testing.
Objective: To learn optimization of power in sequential logic machines.
Session
No *
Topics to be covered
Ref
Teaching Aids
19.
Introduction Sequential Machines – Latches
1-Ch.5; Pg.249-256;
PPT, BB
20.
Latches - Flip-Flops
1-Ch.5; Pg.256-260;
PPT, BB
21.
Sequential Systems and Clocking Disciplines
1-Ch.5; Pg.260-273;
PPT, BB
22.
Sequential Systems and Clocking Disciplines
1-Ch.5; Pg.273-281;
PPT, BB
23.
Sequential System Design
1-Ch.5; Pg.281-285;
PPT, BB
24.
Sequential System Design
1-Ch.5; Pg.285-291;
PPT, BB
25.
Sequential System Design
1-Ch.5; Pg.292-297;
PPT, BB
26.
Power Optimization - Design Validation
1-Ch.5; Pg.298-301;
PPT, BB
27.
Sequential Testing
1-Ch.5; Pg.301-308;
PPT, BB
CAT - 2
Content beyond syllabus covered (if any): NIL
Course Outcome 3:
To design sequential logic machines with optimum power.
* Session duration: 50 mins
FT/GN/68/00/21.04.15
SRI VENKATESWARA COLLEGE OF ENGINEERING
COURSE DELIVERY PLAN - THEORY
Page 4 of 6
Sub. Code / Sub. Name: AP7016 - SYSTEM ON CHIP DESIGN
Unit : IV
Unit Syllabus: SUBSYSTEM DESIGN
Introduction - Subsystem Design Principles - Combinational Shifters – Adders – ALUs – Multipliers –
High Density Memory – Field Programmable Gate Arrays - Programmable Logic Arrays – References
- Problems.
Objective: To study the design principles of FPGA and PLA.
Session
No *
Topics to be covered
Ref
Teaching Aids
28.
Introduction - Subsystem Design Principles
1-Ch.6; Pg.311-315;
PPT, BB
29.
Subsystem Design Principles
1-Ch.6; Pg.315-319
PPT, BB
30.
Combinational Shifters – Adders
1-Ch.6; Pg.319-323;
PPT, BB
31.
Adders – ALUs
1-Ch.6; Pg.323-330;
PPT, BB
32.
Multipliers
1-Ch.6; Pg.330-333;
PPT, BB
33.
Multipliers
1-Ch.6; Pg.334-339;
PPT, BB
34.
High Density Memory
1-Ch.6; Pg.339-348;
PPT, BB
35.
High Density Memory
1-Ch.6; Pg.348-351;
PPT, BB
36.
Field Programmable Gate Arrays - Programmable Logic Arrays
1-Ch.6; Pg.351-356;
PPT, BB
Content beyond syllabus covered (if any): NIL
Course Outcome 4:
To study the design principles of FPGA and PLA.
* Session duration: 50 mins
FT/GN/68/00/21.04.15
SRI VENKATESWARA COLLEGE OF ENGINEERING
COURSE DELIVERY PLAN - THEORY
Page 5 of 6
Sub. Code / Sub. Name: AP7016 - SYSTEM ON CHIP DESIGN
Unit : V
Unit Syllabus: FLOOR-PLANNING
Introduction - Floor-planning Methods – Block Placement & Channel Definition - Global Routing switchbox Routing - Power Distribution - Clock Distributions - Floor-planning Tips - Design
Validation - Off-Chip Connections – Packages, The I/O Architecture - PAD Design.
Objective: To learn various floor planning methods for system design.
Session
No *
Topics to be covered
Ref
Teaching Aids
37.
Introduction - Floor-planning Methods
2-Ch.7; Pg.427-431;
PPT, BB
38.
Block Placement & Channel Definition
2-Ch.7; Pg.431-436;
PPT, BB
39.
Global Routing - switchbox Routing
2-Ch.7; Pg.436-439;
PPT, BB
40.
Power Distribution
2-Ch.7; Pg.439-445;
PPT, BB
41.
Clock Distributions
2-Ch.7; Pg.445-450;
PPT, BB
42.
Floor-planning Tips - Design Validation - Off-Chip Connections –
Packages
2-Ch.7; Pg.450-456;
PPT, BB
43.
The I/O Architecture - PAD Design
2-Ch.7; Pg.457-461;
PPT, BB
44.
CAD Systems – Switch level simulation, Layout synthesis –
Placement – Global routing – Detailed routing
1-Ch10; Pg.510-537
PPT
45.
Timing analysis and optimization –Technology independent logic
optimization –Test Generation
1-Ch10; Pg.540-542
PPT
46.
SOC Design
3
PPT/ICT
47.
System-on-Chip Architecture
4
PPT/ICT
CAT - 3
Content beyond syllabus covered (if any):
CAD Systems and Algorithms; SOC Design; System-on-Chip Architecture
Course Outcome 5:
To learn various floor planning methods for system design.
* Session duration: 50 mins
FT/GN/68/00/21.04.15
SRI VENKATESWARA COLLEGE OF ENGINEERING
COURSE DELIVERY PLAN - THEORY
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Sub Code / Sub Name: AP7016 - SYSTEM ON CHIP DESIGN
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A – Excellent ; B – Good ; C - Average
REFERENCES:
1. Wayne Wolf, “Modern VLSI Design – System – on – Chip Design”, Prentice Hall,
3rd Edition, 2008.
2. Wayne Wolf, “Modern VLSI Design – IP based Design”, Prentice Hall, 4th
Edition, 2008.
3. http://www.nptel.ac.in/courses/108102045/10
4. https://www.youtube.com/watch?v=UYx9c4_NH14
Prepared by
Approved by
S. R. MALATHI
DR. S. GANESH VAIDHYANATHAN
ASSOCIATE PROFESSOR
HOD – EC
8-07-2015
8-07-2015
Signature
Name
Designation
Date
Remarks *:
Remarks *:
* If the same lesson plan is followed in the subsequent semester/year it should be
mentioned and signed by the Faculty and the HOD