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A 107 dB DR, 106dB SNDR
Sigma-Delta ADC
Using a
Charge-Pump Integrator for
Audio Application
The final year project
presentation
The graduation thesis plea of
XXX University
Student No.：
Sam, (DB028791); Hubert, (DB029125)
Supervisor：Prof. Sin-Weng Sai
Co-Supervisor：Prof. U Seng Pan
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1. Introduction
2. Basic theory of Sigma-Delta ADC
CON
TENTS
3. Target specification
4. Architecture Chosen
5. Charge Pump Integrator
6. Behavioral Model
7. Circuit Partial Design
8. Conclusion
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01
Introduction
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Introduction
1Audio in life 2A/D converter 3 Audio standard
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Introduction
1Audio in life 2A/D converter 3 Audio standard
ADC
Analog
Digital
Signal:
Continuous signal
which represents
physical
measurements.
Discrete time signals
generated by digital
modulation.
Example:
Human voice in air,
analog electronic
devices.
Computers, CDs, DVDs,
and other digital
electronic devices.
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Introduction
1Audio in life 2A/D converter 3 Audio standard
ADC
Increase the quality,
reduce the noise and Cumulative distortion.
Save energy,
use converter instead of the amplifier in transmission.
Information safety,
Given the timing information, the transmitted waveform can be
reconstructed
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Introduction
1Audio in life 2A/D converter 3 Audio standard
People’s hearing range
 Frequency range: 20~20k Hz
 Sound Pressure Level(SPL)
=𝐿𝑃 = 20 log
𝑃𝑟𝑚𝑠
𝑃𝑟𝑒𝑓
𝑑𝐵; 𝑃𝑟𝑒𝑓 = 2𝑢𝑝𝑎
human ear's audible sounds is from 0
dB SPL (hearing threshold) to 140 dB SPL
(pain threshold)
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Introduction
1Audio in life 2A/D converter 3 Audio standard
Compact Disc Digital Audio (CDDA or CD-DA) is the standard format for
audio Compact Discs. The standard is defined in the Red Book
44.1 KHz 16bit about 96dB dynamic range
Library 30 dB SPL
symphony orchestra
110dB SPL
110 dB - 30 dB = only 80 dB real
dynamic range if you brought the
orchestra into your home
Good enough for listeners !
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Introduction
1Audio in life 2A/D converter 3 Audio standard
16 bit enough?
An professional requires more during mixing
and mastering. Multiplying that noise by a few
thousand times eventually becomes noticeable.
Keep the accumulated noise at a very low
level !
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02
Basic theory of Sigma-Delta ADC
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Conversion Resolution
Basic theory
1Different ADC
2Key features
Sigma Delta
SAR
 High resolution
Subranging/Pipelined
 Low bandwidth
Flash
Signal Bandwidth
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2Key features
1Different ADC
Basic theory
Signal to noise ratio for Nyquist ADC
𝑆𝑁𝑅| 𝑑𝐵
𝑃𝑠𝑖𝑔𝑛
= 10𝑙𝑜𝑔
𝑃𝑛𝑜𝑖𝑠𝑒
where Psign and Pnoise are the power of the signal and the power of the
noise in the band of interest.
Sine wave as example:
𝑃𝑠𝑖𝑛𝑒
1
=
𝑇
𝑇
0
2
𝑋𝐹𝑆
1
2
𝑠𝑖𝑛 2𝜋𝑓𝑡 𝑑𝑡 ≈
4
𝑇
𝑇
0
2
𝑋𝐹𝑆
(∆ ∙ 2𝑛 )2
2
2𝜋𝑓𝑡 𝑑𝑡 =
4
8
∆2
𝑃𝑄 =
12
∴ 𝑆𝑁𝑅𝑠𝑖𝑛𝑒 | 𝑑𝐵 = 6.02 ∙ 𝑛 + 1.78 𝑑𝐵
Every bit of quantizer improves the SNR by 6.02 dB!!!
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1Different ADC
Basic theory
2Key features
fs
Nyquist Operation
A
ADC
fs/2
kfs
B
 Oversampling
(OSR)
 Noise shaping
(Order)
C
fs
Oversampling
+ Digital filter
ADC
Digital
filter
kfs
Oversampling
+ Digital filter
+ Noise shaping
ƩΔ
MOD
Digital
filter
fs/2
kfs/2
kfs
fs/2
kfs/2
kfs
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03
Target specification
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Target specification
1Products’ use
2Our target
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Target specification
1Products’ use
2Our target
Audio Sigma-Delta ADC From TI Company
Normal products
NAME
pcm1870
SNR
90dB
pcm1808
99dB
pcm1851a
101dB
pcm1803a
103dB
From the table, listing some the audio ADCs use in car audio
system. The SNR performance is 99dB.
Thus We set our target as 105dB SNR, After setting the target,
the structure of the ƩΔ ADC will be chosen to build the system.
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04
Architecture Chosen
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Architecture
Chosen
1Architecture
2Quantizer and OSR
Single Loop Architecture
 CIFB – Cascade Integrators with Distributed Feedback
 CIFF – Cascade Integrators with Distributed Feed-forward
 CRFB – Cascade Resonator with Distributed Feedback
 CRFF – Cascade Resonator with Distributed Feed-forward
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Architecture
Chosen
CIFB
2Quantizer and OSR
1Architecture
u(n)
-ai = bi for i ≤ 3
-b4 = 1
b3
b2
b1
c1
-a1
b4
c2
-a2
y(n)
c3
v(n)
-a3
NTF
DAC
CIFF
u(n)
b4
b1
c2
- b1 = b4 = 1
-c1
c3
y(n)
a3
v(n)
a2
a3
DAC
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1Architecture
Architecture
Chosen
CRFB
2Quantizer and OSR
u(n)
b3
b2
b1
b4
-g1
-ai = bi for i ≤ 3
-b4 = 1
c1
-a1
c2
y(n)
c3
v(n)
20-a3
-a2
0





CRFF
-20
u(n)
b1
-40
DAC
NTF
-60
b4
-80
-g1
-100
- b1 = b4 = 1
c2
c3
-120
y(n)
a3
-140 -3
10
-c1
10
-2
v(n)
10
-1
a2
a3
Further increase SNR by optimizing NTF zero
DAC
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Architecture
Chosen
1Architecture
2Quantizer and OSR
Feedforward
Feedback
Only one DAC required
Requires many feedback DACs
Needs an extra adder
No extra adder
First integrator is fastest
Last integrator is fastest
First opamp is power hungry
First opamp is power hungry
With Resonator
Without Resonator
Advantage
Higher SNDR
Simpler Structure
Disadvantage
More Complex
Structure (Resonator)
Lower SNDR
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Architecture
Chosen
01
1Architecture
1.5 Bit Quantizer
2Quantizer and OSR
OSR=256
 Higher SNR
 Ensure linearity
 Higher SNR
 Decrease the Thermal Noise
02
05
3rd order architecture
03
 Higher SNR
A single loop 3rd order CRFB Σ-Δ ADC with 1.5 bit
quantizer and 256 OSR are designed.
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05
Charge Pump Integrator
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1Introduction
Charge Pump
Integrator
Second
Integrator
First
Integrator
VREFP
VREFP
Φ1a
Φ1a
Φ2a
Φ2
Φ1a
Φ2a
VIP
VFBN
Φ1
Φ1a
Φ1a
VIP
Φ2a
Φ2a
VIP
CRFB architecture using
Adder
conventional SC integrator
Third
Integrator
VREFP
VIP
2Conclusion
Φ2
Φ1a
Φ2
Φ1a
Φ2
Φ2
Φ1
Φ1a
Φ2
Φ1
Φ2
Φ1a
Φ2
Φ2
Φ2
FEEDBACK
Φ1
VIP
Φ1a
Φ1
Φ2
Φ2
Φ2
Φ1a
Φ1
Φ1
Φ2
Φ1a
Φ1
Φ2
Φ2
VFBP
Φ2a
VREFN
VIP
VIP
Φ2a
Φ1a
VIP
Φ2a
Φ1a
Φ1a
Φ2a
Second
Integrator
First
Integrator(CP)
VREFP
Φ1a
Φ1a
Φ2a
VIP
Φ2
CRFB architecture using CP
SCAdder
integrator
Third
Integrator
VREFP
Φ1
Φ1a
VREFN
VREFN
VIP
Φ2
Φ1a
VIP
Φ2a
Φ1a
Φ2a
Φ2
VIP
Φ1a
VFBN
2VREFP
Φ1a
Φ2a
Φ2
Φ1a
Φ2
Φ1a
Φ2
Φ2
Φ1
2VREFN
Φ1
Φ1a
VIN
Φ2a
Φ1a
Φ2
Φ1
Φ1
Φ2
Φ2
Φ2
Φ2
Φ1a
Φ1
Φ1a
Φ2
Φ1
Φ2
Φ2
Φ1a
Φ2
Φ2
FEEDBACK
Φ1
Φ1
Φ2
Φ2
VFBP
Φ1a
Φ1
VIP
VIP
Φ2a
Φ1a
Φ1a
VREFN
Φ2a
VIP
Φ1a
Φ2a
Φ1a
Φ2
VREFN
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1Introduction
Charge Pump
Integrator
2Conclusion
Conventional
𝐶𝑠/𝑘
Ci
Cs
Φ1
VIN
Φ2
Φ2
VOUT
Φ2
Cs
Vref
VOUT
Φ1
Cl
VREF
Charge-pump
Cs1=Cs/2
Φ2
VIN
Φ2
Φ1
Φ2
Φ2
Φ1
Cs2=Cs/2
Cs/2k
Ci2
VOUT
Cs/4
2Vref
VOUT
Cl
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1Introduction
Charge Pump
Integrator
2Conclusion
Conventional
Charge-pump
𝐶𝑠/𝑘
Cs/2k
Cs
Cs/4
Vref
2Vref
VOUT
VOUT
Cl
𝐶𝑠
𝐶𝐿 =
+ 𝐶𝑙
𝑘+1
1
𝛽=
𝑘+1
𝐶𝐿
= 𝐶𝑠 + 𝐶𝑙 (𝑘 + 1)
𝛽
Cl
𝑃𝑂𝑊𝑂𝑃 ∝ 𝑔𝑚
𝑔𝑚 =
𝐶𝐿
𝛽
𝜔−3𝑑𝐵 𝐶𝐿
𝛽
𝐶𝐿 ′ =
𝐶𝑠 2
+ 𝐶𝑙
𝑘+2
2
𝑘+2
𝐶𝐿
𝐶𝑠
𝑘
( )′ = + 𝐶𝑙 ( + 1)
𝛽
4
2
𝛽′ =
′
≈
𝐶𝐿
4𝛽
𝑔𝑚
4
′ = 𝑃𝑂𝑊𝑂𝑃
 𝑃𝑂𝑊𝑜𝑝
4
′ =
𝑔𝑚
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Charge Pump
Integrator
1Introduction
STRENGTH
WEAKNESS
Reduce the power consumption
of the amplifier
S W
OPPORTUNITY
Easier to implement by adding
capacitor
2Conclusion
O T
Need double supply voltage
(two 0.25um transistor)
THREATS
May cause unmatched problem
and high requirements to other
parts
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06
Behavioral Model
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1Ideal Model 2Model with Non-idealities
Behavioral Model
The 3rd order CRFB with noise block in Matlab
PSD of a 3rd-Order Sigma-Delta Modulator
0
-20
SNR = 134.8dB @ OSR=256
-40
ENOB = 22.10 bits @ OSR=256
-60
PSD [dB]
-80
-100
-120
-140
-160
-180
-200
4
10
5
10
Frequency [Hz]
6
10
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Behavioral Model
1Ideal Model 2
Model with Non-idealities
The main non-idealities
 Operational amplifier non-idealities:
5%
20%
1. Bandwidth of Op-amp;
2. Slew rate of Op-amp;
3. Operational amplifier saturation voltages.
75%
 Thermal noise of Switch Capacitor structure.
 noise of op-amp.
 clock jitter at the input sampler.
kT/C plus Op-amp thermal noise
Other noise
Quantization noise
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Behavioral Model
1Ideal Model 2
Model with Non-idealities
DC gain requirement of first op-amp
Finite DC gain
SNR
80dB
134.8dB
60dB
134.8dB
-60
58dB
132.3dB
-80
54dB
128.1dB
-100
50dB
120.4dB
PSD of a 3rd-Order Sigma-Delta Modulator
0
-20
PSD [dB]
-40
-120
First Integrator Output
Second Integrator Output
Third Integrator Output
250
250
250
200
200
200
150
150
150
-140
-200
4
10
5
10
Frequency [Hz]
Occurrences
-180
Occurrences
Occurrences
-160
100
100
100
50
50
50
6
10
0
-0.05
0
Voltage [V]
0.05
0
-0.4
-0.2
0
Voltage [V]
0.2
0.4
0
-1
-0.5
0
Voltage [V]
0.5
1
Repeat the operation to obtain behavioral model of the system
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Behavioral Model
1Ideal Model 2
Model with Non-idealities
Behavioral Model of The Project
Sigma-delta Parameter
SNR (dB)
Ideal modulation
134.8
Finite DC gain (A=58dB, 58dB,
50dB)
130.6
Finite bandwidth(GBW=100MHz)
134.8
Finite Slew-rate (SR=60V/us)
134.8
Saturation voltages (|Vmax|=1V)
134.8
Sampling Jitter (Δ𝜏 = 17𝑝𝑠)
130.7
Switch (kT/C) noise (Cs=10pF)
110.4
Input-referred operational
amplifier noise (Vn=1.5uV)
Including all of the non-idealities
108
107-107.5
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Behavioral Model
1Ideal Model 2
Model with Non-idealities
In cadence simulation, the first Op-amp gain requirement is 58 dB for
133dB SNR, now change the architecture:
The gain of first Opamp(dB)
simulation result of
Cadence(dB)
54
133
50
133
48
133
46
132
42
130
It is clearly found that the requirement of first Op-amp is reduced
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07
Circuit Partial Design
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1Op-amp 2Optimization3Quantizer 4Switch
Circuit Partial
Design
Op-amp DesignV
DD
vOP1
R1
C1
vON1
VDD
vON
vOP
VCMFB
M10
M11
VCMFB1
1st
VB3
M8
M3
vOP
IREF
2
M13
vON1
M12
VB2
M6
M2
M15
vON
M9
vOP1
VIN
M14
VREFP
VREFP
VREFP
VB0
5
3
4
VB1
VB2
6
VB3
M7
VIP
VB2
7
VREF
VB1
M4
VB4
1
M5
M1
GND
GND
VOP
VCM
Φ1
Φ2
C1
Φ1
VON
Φ2
C2
C3
Φ2
Φ2
VBIAS
VCMFB
Φ1
VCM
C4
Φ1
VBIAS
CMFB
Op-Amp:
 Main structure
 Bias Circuit
 Switched-capacitor CMFB
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1Op-amp 2Optimization3Quantizer 4Switch
Circuit Partial
Design
Op-amp Design
VDD
VDD
VB1
M18
VCMFB
M19
M1
M10
M16
M1
M12
M11
M17
M14
VCMFB
VB4
VB2
VIN
M15
vON
VCMFB1
VB2
vOP
M2
M3
VB3
M8
M9
M13
VIN
M2
M3
VIP
M8
M11
VB3
VB3
M6
VB4
M9
M6
M7
M4
M4
vOP
vON
M13
vON1
vOP1
M10
M15
M14
VIP
M12
VB2
M7
VB1
M5
M5
GND
2nd
GND
3rd
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Circuit Partial
Design
1Op-amp 2Optimization3Quantizer 4Switch
Zero Optimization
For the CRFB structure, it needs a local feedback from third integrator output to
second integrator input to make up a resonator which effects the zero.
Vi2
Φ2
Φ1
C2
C1
Φ1a
C3
Φ2a
Φ2
𝐶1 ||(𝐶2 + 𝐶3 )
𝐶2
Q 2 = V𝑜3
∙
2
𝐶3 + 𝐶2
Vo3
Vi2
Cb
Vo3
Extremely
small
Q = g ∙ V𝑜3
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1Op-amp 2Optimization3Quantizer 4Switch
Circuit Partial
Design
1.5 Bit Quantizer
VREFP
VCM
Φ2
Φ2
VDD
C1
Φ1
VIP
D0
VIN
CLK
Φ1
C2
Φ2
M10
M8
M7 M9
Φ2
VREFN
VCM
VREFN
VCM
Φ2
M11
CLK
vON
vOP
CLK
M4
M5
Φ2
C1
Φ1
M6
vIN
VIP
M2
M3
vIP
D1
VIN
Φ1
CLK
C2
Φ2
VREFP
M1
VSS
Φ2
VCM
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Circuit Partial
Design
1Op-amp 2Optimization3Quantizer 4Switch
CMOS switch
Ron,p
Ron,n
CLK
Vin
Vout
CH
CLK’
Ron,eq
VTHP
VIN
VDD-VTH
It is often used very large or small voltage input, under such
situation, the transmission resistor will change critically
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1Op-amp 2Optimization3Quantizer 4Switch
Circuit Partial
Design
Bootstrapped Switch
Vdd
Vdd
sw4 Φ1
Vout
Φ2
M1
Vin
Output
sw2
Φ2 sw3
Φ1 sw1
M5
M1
Φ2 sw5
Vss
C0
M8
C2
C1
Input
M2
Vss
M7
M6
M3
M4
Vss
To obtain constant conductance, the bootstrap technique can be used to
keep the gate-source voltage at a certain value.
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08
Conclusion
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1System Performance 2
3Summary
Comparison
Conclusion
0
PdydB
-20
-40
PSD(dB)
-60
-80
-100
107dB Dynamic Range
-120
-140
3
10
4
10
5
10
Frequency(Hz)
6
7
10
10
Output PSD for the system
Measured SNDR versus input amplitude
Technology
Sampling
Frequency
Bandwidth
Peak
SNDR
Power
Consumption
FOM
65nm CMOS
10.24MHz
20kHz
106dB
1.332mW
204f/conv.
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Conclusion
1System Performance 2
3Summary
Comparison
Transistor level comparison of system using CP And Conventional
32.4%
Peak SNDR
Power
consumption
Power consumption
32.4% decrease because
of first stage
FOM
CP
Conventional
106dB
102dB
1.332mW
1.972mW
204f/conv.
479f/conv.
It achieves a higher SNDR but cost less power by using CP integrator
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1System Performance 2
3Summary
Comparison
Conclusion
Comparison with Other Σ-Δ ADC
This
work
JSSC/06
CICC/11
TCAS-1/13
JSSC/09
JSSC/08
JSSC/03
[1]
[2]
[5]
[4]
[3]
[6]
Tech
[um]
0.065
0.065
0.065
0.13
0.18
0.13
0.35
Supply
[V]
1.0
1.2
1.0
1.2
0.7
0.9
2
Input Range
[Vpp-diff ]
0.9
1.0
0.9
0.4
1.0
1.1
/
OSR
256
300
64
128
100
128
154
BW
[kHz]
20
20
24
10
20
24
20
SNDR
[dB]
106
95
95
87.8
81
89
105
Power
[uW]
1332
2200
371
148
36
1500
68000
FOM
[fJ/conv.]
204
11200
170
369
98
1360
11700
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Conclusion
1System Performance 2
3Summary
Comparison
 For audio application => high SNDR (target ≥105dB)
 Suppress the in-band noise (oversampling and noise shaping)
 3rd CRFB Sigma-Delta modulator architecture using CP integrator
is selected
 As a result, with a full-scale input of 900mVpp differential the
CRFB ADC using charge-pump integrator achieves 106 dB SNDR
and 107dB dynamic range in audio bandwidth (20kHz), while
consuming 1.332mW power.
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Reference
1.
Dorrer, L., et al. "A 2.2 mW, continuous-time sigma-delta ADC for voice coding with 95dB dynamic
range in a 65nm CMOS process." Solid-State Circuits Conference, 2006. ESSCIRC 2006.
Proceedings of the 32nd European. IEEE, 2006.
2.
Liu, L., et al. "A 95dB SNDR audio ΔΣ modulator in 65nm CMOS." Custom Integrated Circuits
Conference (CICC), 2011 IEEE. IEEE, 2011.
3.
M. G. Kim, G.-C. Ahn, P. Hanumolu, S.-H. Lee, S.-H. Kim, S.-B. You,J.-W. Kim, G. C. Temes, and U.-K.
Moon, “A 0.9 V 92 dB double-sampled switched-RC delta-sigma audio ADC,” IEEE J. Solid-State
Circuits, vol. 43, no. 5, pp. 1195–1206, May 2008.
4.
Y. Chae and G. Han, “Low voltage, low power, inverter-based switched-capacitor delta-sigma
modulator,” IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 458–472, Feb. 2009.
5.
Nilchi, Alireza, and David A. Johns. "A low-power delta-sigma modulator using a charge-pump
integrator." Circuits and Systems I: Regular Papers, IEEE Transactions on 60.5 (2013): 1310-1321.
6.
Yang, YuQing, et al. "A 114-dB 68-mW chopper-stabilized stereo multibit audio ADC in 5.62 mm
2." Solid-State Circuits, IEEE Journal of 38.12 (2003): 2061-2068.
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THANK YOU !
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