Download T3029919 - Telecommunications Industry Association

Telecommunications Industry Association
(TIA)
Columbia, MD
TR-30.2/99-10-019
October 15, 1999
COMMITTEE CONTRIBUTION
Technical Committee TR-30 Meetings
SOURCE:
PN-4540 Editor
CONTRIBUTOR:
Fred Lucas
3Com Corporation
10440 Little Patuxent Parkway, Suite 900
Columbia, MD 21044
Phone: 410-884-4095
Fax: 410-884-4094
Email: [email protected]
TITLE:
Draft 2, Revision of TIA/EIA-334-B to -C
PROJECT:
PN-4540
DISTRIBUTION:
Members of TR-30.2
____________________
ABSTRACT
This contribution is the 2nd draft for the Revision of TIA/EIA-334-B to -C, Signal Quality At Interface
Between Data Terminal Equipment and Synchronous Data Circuit-Terminating Equipment For Serial
Data Transmission. The changes made to the draft revision, which were agreed to at the August meeting
of TR-30.2, are highlighted with strikethrough of deleted text and new text underlined. Editorial changes
made at the August meeting are not highlighted.
Copyright Statement
"The contributor grants a free, irrevocable license to the Telecommunications Industry Association (TIA) to incorporate text
contained in this contribution and any modifications thereof in the creation of a TIA standards publication; to copyright in
TIA's name and TIA standards publication even though it may include portions of this contribution; and at TIA's sole
discretion to permit others to reproduce in whole or in part the resulting TIA standards publication."
PN-4540, Draft 2
SIGNAL QUALITY AT INTERFACE BETWEEN
DATA TERMINAL EQUIPMENT
AND SYNCHRONOUS DATA CIRCUIT-TERMINATING EQUIPMENT
FOR SERIAL DATA TRANSMISSION
(From TIA/EIA Standard EIA-334-B and Standards Proposal
No. 4540 formulated under the cognizance of TIA
Subcommittee TR-30.2 on Data Transmission Interfaces and Protocols
CONTENTS
1
SCOPE........................................................................................................................ 1
2
NORMATIVE REFERENCES ...................................................................................... 1
3
DEFINITIONS.............................................................................................................. 2
3.1
Co-directional Timing ............................................................................................. 2
3.2
Contra-directional Timing ....................................................................................... 3
3.3
Duty Cycle ............................................................................................................. 3
3.4
Jitter ...................................................................................................................... 3
3.5
Signal Element ...................................................................................................... 3
3.6
Signal Element Timing ........................................................................................... 4
3.7
Transition ............................................................................................................... 4
3.8
Unit Interval ........................................................................................................... 4
4
INTERFACE CONFIGURATIONS ............................................................................... 4
4.1
Point of Demarcation ............................................................................................. 4
4.2
Interconnecting Cable ............................................................................................ 5
5
INTERFACE AT TRANSMITTING TERMINAL ............................................................ 5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
Timing Signals ....................................................................................................... 5
Frequency Accuracy ........................................................................................... 5
Duty cycle of Timing Signals ............................................................................... 5
Jitter on circuit DB, Transmit Signal Element Timing (DCE Source).................... 5
Jitter on Circuit DA, Transmit Signal Element Timing (DTE Source) ................... 5
5.2
Timing Relationship Between Transmit Data and Transmit Signal Element
Timing.................................................................................................................... 6
Contra-directional Timing (DCE Source Timing) ................................................. 6
Co-directional Timing (DTE Source Timing) ........................................................ 7
5.2.1
5.2.2
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PN-4540, Draft 2
6
INTERFACE AT RECEIVING TERMINAL ................................................................... 7
6.1
6.1.1
6.1.2
6.1.3
Timing Signals ....................................................................................................... 7
Frequency Accuracy ........................................................................................... 7
Duty Cycle of Timing Signals .............................................................................. 7
Jitter on Circuit DD, Receiver Signal Element Timing ......................................... 7
6.2
Timing Relationship between Received Data and Receiver Signal Element
Timing.................................................................................................................... 8
Timing Signals Provided by DCE (Co-directional Timing) ................................... 8
6.2.1
7
MEASUREMENT OF SIGNAL QUALITY..................................................................... 8
7.1
7.1.1
7.1.2
7.1.3
7.1.4
Signal Quality for Unbalance Generators ............................................................... 9
Interchange Circuit Signal Return ....................................................................... 9
Generator Voltage .............................................................................................. 9
Signal Quality Voltage Thresholds ...................................................................... 9
Standard Test Load .......................................................................................... 10
7.2
7.2.1
7.2.2
7.2.3
Signal Quality for Balance Generators ..................................................................10
Generator Voltage ............................................................................................ 11
Signal Quality Threshold Voltages .................................................................... 11
Standard Test Load .......................................................................................... 11
ANNEX A (INFORMATIVE) ................................................................................................ 12
A
INFORMATIVE REFERENCE ..............................................................................12
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PN-4540, Draft 2
FOREWORD
(This foreword is not part of this Standard)
This Standard was formulated under the cognizance of TIA Subcommittee TR-30.2 on
Data Transmission Interfaces and Protocols.
This Standard is a revision to EIA-334-B. This revision adds requirements for: TIA/EIA687, Medium Speed Interface for Data Terminal Equipment and Data Circuit Terminating
Equipment along with its associated electrical characteristics standard TIA/EIA-423-B,
Electrical Characteristics of Unbalanced Voltage Digital Interface Circuits; TIA/EIA-723,
High Speed 232 Type DTE/DCE Interface along with its associated electrical
characteristics standard TIA/EIA-694, Electrical Characteristics for an Unbalanced
Digital Interface for Data Signaling Rates Up to 512 kbit/s; and TIA/EIA-561, Simple 8
Position Non-Synchronous Interface Between Data Terminal Equipment and Data
Circuit-Terminating Equipment Employing Serial Binary Data Interchange and TIA/EIA574, 9 Position Non-Synchronous Interface Between Data Terminal Equipment and Data
Circuit-Terminating Equipment Employing Serial Binary Data Interchange and their
associated electrical characteristics standard TIA/EIA-562, Electrical Characteristics for
An Unbalanced Digital Interface. It also incorporates new timing diagrams for Figures 4
- 8 which better represent the requirements set forth in this standard.
Annex A is informative and is not considered part of this standard.
iii
PN-4540, Draft 2
This Page Intentionally Left Blank
iv
PN-4540, Draft 2
1
SCOPE
1.1
This Standard is applicable to the exchange of serial binary data signals and timing
signals across the interface between Data Terminal Equipment (DTE) and synchronous
Data Circuit-terminating Equipment (DCE). The DCE is considered to be synchronous if the
timing signal circuits are required at the transmitting terminal or the receiving terminal, or
both. The signal quality requirement is limited to synchronous transmission at the interface
with synchronous DCEs. Signal quality pertaining to asynchronous DTEs is not part of this
Standard.
1.2
The interfaces referred to in this Standard conform to TIA/EIA standards:
TIA/EIA-232-F
TIA/EIA-530-A together with TIA/EIA-422-B electrical characteristics
TIA/EIA-561 together with TIA/EIA-562
TIA/EIA-574 together with TIA/EIA-562
TIA/EIA-687 together with TIA/EIA-423-B electrical characteristics
TIA/EIA-723 together with TIA/EIA-694 electrical characteristics
1.3
This Standard specifies signal quality in relation to jitter, duty cycle, and frequency
accuracy of timing signals and time displacement between data signals and timing signals.
Electrical specifications for the signals are not part of this Standard but are part of the
reference interface specifications.
1.4
This Standard is of particular importance when the equipments in a system are
furnished by different organizations. It does not attempt to indicate what action, if any, is to
be taken if the limits are not met, but it is intended to provide a basis for agreement between
the parties involved.
1.5
This Standard does not describe any requirements for error performance either for
a complete system or any system components. It should not be assumed that compliance
with this Standard will produce error rates that are acceptable in any particular application.
1.6
Any equipment which is represented as complying with this Standard shall meet
the applicable specifications within the range of those factors which are described as
appropriate for the normal operation of the equipment, such as primary power voltage and
frequency, ambient temperature, or humidity.
1.7
2
This Standard may also be used for DTE to DTE direct connections.
NORMATIVE REFERENCES
The following standards contain provisions which, through reference in this text, constitute
provisions of this Standard. At the time of publication, the editions indicated were valid. All
Standards are subject to revision, and parties to agreements based on this Standard are
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PN-4540, Draft 2
encouraged to investigate the possibility of applying the most recent editions of the
standards indicated below. ANSI and TIA maintain registers of currently valid national
standards published by them.
ANSI/TIA/EIA-232-F-1997, Interface Between Data Terminal Equipment and Data CircuitTerminating Equipment Employing Serial Binary Data Interchange.
ANSI/TIA/EIA-422-B-1995, Electrical Characteristics of Balanced Voltage Digital Interface
Circuits.
ANSI/TIA/EIA-423-B-1995, Electrical Characteristics of Unbalanced Voltage Digital Interface
Circuits
ANSI/EIA/TIA-530-A-1998, High Speed 25-Position Interface For Data Terminal Equipment
and Data Circuit-Terminating Equipment Including Alternative 26-Position Connector.
ANSI/TIA/EIA-561-1998, Simple 8 Position Non-Synchronous Interface Between Data
Terminal Equipment and Data Circuit-Terminating Equipment Employing Serial Binary Data
Interchange
ANSI/TIA/EIA-562-1998, Electrical Characteristics for An Unbalanced Digital Interface
ANSI/TIA/EIA-574-1998, 9 Position Non-Synchronous Interface Between Data Terminal
Equipment and Data Circuit-Terminating Equipment Employing Serial Binary Data
Interchange
ANSI/TIA/EIA-687-1997, Medium Speed Interface for Data Terminal Equipment and Data
Circuit Terminating Equipment
ANSI/TIA/EIA-694-1997, Electrical Characteristics for an Unbalanced Digital Interface for
Data Signaling Rates Up to 512 kbit/s
ANSI/TIA/EIA-723-1998, High Speed 232 Type DTE/DCE Interface
3
DEFINITIONS
For the purposes of this Standard, the following definitions apply:
3.1
Co-directional Timing
A configuration in which a timing signal and associated binary signals (data or control) are
transferred in the same direction across the interface (see Figure 1).
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PN-4540, Draft 2
Data
Circuit
Terminating
Equipment
Data
Terminal
Equipment
Information signal
timing signal
Figure 1 - Co-directional Timing
3.2
Contra-directional Timing
A configuration in which a timing signal and associated binary signals (data or control) are
transferred in opposite directions across the interface (see Figure 2). This configuration
would apply to Transmit Clock/Data only.
Data
Circuit
Terminating
Equipment
Data
Terminal
Equipment
Information signal
timing signal
Figure 2 - Contra-directional Timing
3.3
Duty Cycle
In signal element timing the duration of the signal condition form which a significant
transition is originated. The duration is usually expressed as a percentage of the unit
interval.
3.4
Jitter
The degree of short term variation of the significant instant of a digital signal from its ideal
position in time.
3.5
Signal Element
Each of the parts constituting a data signal and distinguished from the others by its nature,
magnitude, duration and relative position (or by one or some of these features only).
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PN-4540, Draft 2
3.6
Signal Element Timing
A signal used to determine the duration of signal elements and to achieve synchronization
with a synchronous transmission system.
3.7
Transition
A change from one significant condition to another in a data signal.
3.8
Unit Interval
A unit interval is the duration of the shortest nominal signal element. It is the longest interval
of time such that the nominal durations of the signal elements in a synchronous system are
whole multiples of this interval.
4
4.1
INTERFACE CONFIGURATIONS
Point of Demarcation
Figure 3 illustrates the point of demarcation between the DTE and the DCE. The interface
cable is considered to be provided with the DTE and the connector which is the point of
demarcation shall be physically attached to the DCE or extended by means of a cable (less
than 3 meters or 10 feet).
The measurements of relative phase relationship (timing displacement) between data and
timing signals, jitter, duty cycle, and frequency accuracy of the timing signals shall be made
at the point of demarcation.
Table 1 specifies the mnemonic terms used for timing and data signals relating to this
standard and the direction of the DTE-DCE interchange circuits.
Table 1 - Interchange Circuits
Timing
Contra
Timing
Source
ITU-T V.24
Number
X
DCE
114
X
DTE
113
X
DCE
115
BA
DTE
103
BB
DCE
104
Circuit Name
Mnemonic
Transmit Signal Element
Timing
DB
Transmit Signal Element
Timing
DA
Receiver Signal Element
Timing
DD
Transmitted Data
Received Data
Co
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PN-4540, Draft 2
DCE
DTE
3 Meters (10 Feet)
Maximum
Figure 3 - Point of Demarcation
4.2
Interconnecting Cable
The length of the interconnecting cable is not specified. Guidelines on the maximum cable
length are included in the applicable interface standards. In the case of contra-directional
timing, the requirements on timing displacement at the higher data rates (greater than 20
kbit/s) may be more restrictive than the guidelines presented in the interface standards.
5
INTERFACE AT TRANSMITTING TERMINAL
The interchange circuits associated with the transmit direction of synchronous DTEs should
operate within the specified requirements given in the following sections.
5.1
5.1.1
Timing Signals
Frequency Accuracy
The frequency of Circuits DA or DB (Transmit Signal Element Timing) shall not deviate more
than 0.01% from the nominal value.
5.1.2
Duty cycle of Timing Signals
The duty cycle of Circuits DA or DB (Transmit Signal Element Timing) shall be 50 10% of
the unit interval of the data signal (see Figure 4).
5.1.3
Jitter on circuit DB, Transmit Signal Element Timing (DCE Source)
Figure 4 defines the significant transitions of Circuit DB (Transmit Signal Element Timing
(DCE Source)). The jitter on the significant transitions shall not be greater than 30% of the
unit interval of the data signal. The observation period for this measurement shall be 10
seconds.
5.1.4
Jitter on Circuit DA, Transmit Signal Element Timing (DTE Source)
Figure 4 defines the significant transitions of Circuit DA (Transmit Signal Element Timing
(DTE Source)). The jitter on the significant transitions shall not be greater than 1% of the
unit interval of the data signal. The observation period for this measurement shall be 10
seconds.
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PN-4540, Draft 2
5.2
5.2.1
Timing Relationship Between Transmit Data and Transmit Signal Element
Timing
Contra-directional Timing (DCE Source Timing)
The displacement between data transitions on Circuit BA (Transmitted Data) and the
associated transition form OFF to ON of Circuit DB (Transmit Signal Element Timing (DCE
Source)) shall not be greater than 25% of the unit interval of the data signal (see Figure 5).
Significant transition
"ON"
Circuit DA
"OFF
"
100%
0.5% max
0.5% max
40%
Duty
Cycle
Limits
50%
60%
15% max
15% max
"ON"
Circuit DB
"OFF"
Significant transition
Figure 4 - Transmit Signal Element Timing
"ON"
Circuit DB
25%
max
Sampling
Interval
25%
max
25%
max
Sampling
Interval
25%
max
"OFF
"
"0"
Circuit BA
"1"
Figure 5 - Contra-directional Timing
6
PN-4540, Draft 2
5.2.2
Co-directional Timing (DTE Source Timing)
The displacement between data transitions on Circuit BA and the associated transition from
ON to OFF of Circuit DA (Transmit Signal Element Timing (DTE Source)), shall not be less
than 25% of the unit interval of the data signal (see Figure 6).
"ON"
Circuit DA
"OFF
"
Sampling Interval
25%
min
25%
min
"0"
25%
min
Circuit BA
25%
min
"1"
Figure 6 - Co-directional Timing
6
INTERFACE AT RECEIVING TERMINAL
The interchange circuits associated with the receive direction of synchronous DTE's should
operate within the specified requirements given in the following sections. The signals
appearing on the interchange circuits are shown in Figure 5.
6.1
6.1.1
Timing Signals
Frequency Accuracy
The frequency of Circuit DD (Receiver Signal Element Timing) shall not deviate more than
0.01% from the nominal value.
6.1.2
Duty Cycle of Timing Signals
The duty cycle of Circuit DD (Receiver Signal Element Timing) shall be 50 10% of the unit
interval of the data signal (see Figure 7).
6.1.3
Jitter on Circuit DD, Receiver Signal Element Timing
Figure 7 defines the significant transitions of Circuit DD (Receiver Signal Element Timing).
The jitter on the significant transitions shall not be greater than 30% of the unit interval of the
data signal. The observation period for this measurement shall be 10 seconds and the
measurement shall be taken after the system has stabilized.
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PN-4540, Draft 2
6.2
6.2.1
Timing Relationship between Received Data and Receiver Signal Element
Timing
Timing Signals Provided by DCE (Co-directional Timing)
The displacement between data transitions on Circuit BB (Received Data) and the
associated transition from ON to OFF of Circuit DD (Receiver Signal Element Timing) shall
not be less than 25% of the unit interval of the data signal (see Figure 8).
Significant transition
"ON"
Circuit DD
15% max
40%
15% max
50%
60%
"OFF
"
Duty
Cycle
Limits
100%
Figure 7 - Receive Signal Element Timing
"ON"
Circuit DD
"OFF
"
Sampling Interval
25%
min
25%
min
"0"
25%
min
Circuit BB
25%
min
"1"
Figure 8 - Signal Quality Parameters Associated With Receiving Terminal
7
MEASUREMENT OF SIGNAL QUALITY
Measurement of signal quality shall be made on the particular signal interchange circuit(s) of
interest at the interface (i.e., the point of demarcation shown in Figure 3) while the circuit is
loaded with a standard test load. The measurement of timing displacement between data
circuits and associated timing circuits using co-directional timing requires both circuits to be
terminated and the use of an instrument such as a dual-trace oscilloscope to display both
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PN-4540, Draft 2
waveforms simultaneously. Timing displacement for data circuits using contra-directional
timing shall be measured using the test arrangement shown in Figure 9.
Circuit DB
Test
Generator
Equipment
Under
Test
Test
Equipment
Circuit BA
Standard
Test Load
Interface Point
Figure 9 - Contra-directional Timing Test Arrangement
Two different test arrangements exist. One for interchange circuits using unbalance
generators (Figure 10) and the other for interchange circuits using balanced generators
(Figure 11).
7.1
Signal Quality for Unbalance Generators
Unbalanced digital interfaces may use the electrical characteristics specified in TIA/EIA-232F, TIA/EIA-423-B, TIA/EIA-562 or TIA/EIA-694. Figure 10 shows the test arrangement for
use with unbalanced interchange circuits. Table 2 shows the test values for each of the
electrical characteristics.
7.1.1
Interchange Circuit Signal Return
The common return for the interchange circuit under test shall be the applicable signal
common for the particular interface.
7.1.2
Generator Voltage
With the Standard Test Load, the generator shall produce a minimum voltage V1 across the
test load (see Table 2).
7.1.3
Signal Quality Voltage Thresholds
Signal quality measurement shall be made using the threshold voltages specified in Table 2
to determine the time of occurrence of signal transitions.
7.1.3.1
A mark-to-space or OFF to ON transition shall be taken to occur at the
instant a positive going transition of V1 crosses the ON threshold voltage.
7.1.3.2
A space-to-mark or ON to OFF transition shall be taken to occur at the
instant a negative going transition of V1 crosses the OFF threshold voltage.
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PN-4540, Draft 2
7.1.4
Standard Test Load
The standard test load is shown in Figure 10. The values of CL and RL are shown in Table
2.
The value of CL shall be adjusted to account for the nominal value of generator
capacitance and cable capacitance to the interface point.
Unbalanced
Generator
Standard Test
Load
Interchange Circuit
Under Test
V1
CL
RL
To Test
Equipment
Signal Common
Interface Point
Figure 10 - Test Arrangement For Unbalanced Electrical Interchange Circuits
Table 2 - Unbalanced Electrical Characteristic Test Values
Electrical
Characteristic
Standard
Minimum
Generator
Voltage
V1
Threshold
Voltage
Standard Test Load
ON
OFF
CL
RL
TIA/EIA-232-F
±5 V
+3 V
-3 V
2500 pF
3000 
TIA/EIA-423-B
±3.6 V
+200 mV
-200 mV
50 pF
450 , ±1%
TIA/EIA-562
±3.7 V
+3 V
-3 V
Note 1
3000 
TAI/EIA-694
±3 V
+2V
-2 V
100 pF
3000 , ±1%
Note 1: CL is 2500 pF for data rates up to 20 kbit/s and 1000 pF for data rates above
20 kbit/s.
7.2
Signal Quality for Balance Generators
Balanced digital interface are TIA/EIA-530-A using TIA/EIA-422-B electrical characteristics.
Figure 11 shows the test arrangement for use with balanced interchange circuits. The test
equipment used shall have a differential input that displays the signal waveform A-B. The
signal common, Circuit AB, may be connected to the test equipment signal ground.
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PN-4540, Draft 2
7.2.1
Generator Voltage
The TIA/EIA-422-B generator shall produce a voltage V1, where A is positive with respect to
B by a minimum of 2 volts for a binary 0 (space or ON) and A is negative with respect to B
by a minimum of 2 volts for a binary 1 (mark or OFF) with a standard test load.
7.2.2
Signal Quality Threshold Voltages
Signal quality measurement shall be made using the threshold voltages specified in 7.2.2.1
and 7.2.2.2 to determine the time of occurrence of signal transitions.
7.2.2.1
A mark-to-space or OFF to ON transition shall be taken to occur at the
instant the differential voltage A-B crosses +200 mV in a positive going direction.
7.2.2.2
A space-to-mark or ON to OFF transition shall be taken to occur at the
instant the differential voltage A-B crosses -200 mV in a negative going direction.
7.2.3
Standard Test Load
The standard test load shall be 100 ohms connected between the A and B leads of the
interchange circuit.
Standard Test
Load
A
Balanced
Generator
Interchange Circuit
Under Test
V1
100 
To Test
Equipment
B
C
Interface Point
Signal Common
Figure 11 - Test Arrangement For Balanced Electrical Interchange Circuits
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PN-4540, Draft 2
Annex A (Informative)
A
INFORMATIVE REFERENCE
The following standard is for reference and is not considered part of this standard.
ITU-T Recommendation V.24, List of Definitions for Interchange Circuits Between data
Terminal Equipment (DTE) and Data Circuit-Terminating Equipment (DCE)
12