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Circuit characterization and
Performance Estimation
1
Introduction
 Need simple models to estimate system
performance in terms of signal delay and power
dissipation.
 Each layer in an MOS transistor has both
resistance and capacitance that are fundamental
components in estimating the performance of a
circuit or system.
 They also have inductance characteristics that is
assumed to be negligible.
2
Introduction
• Issues include:
 Resistance, capacitance and inductance calculations.
 Delay estimations.
 Determination of conductor size for power and clock
distribution.
 Power consumption.
 Charge sharing mechanisms.
 Design Margining.
 Reliability.
 Effects of scaling.
3
Resistance Estimation
The resistance of a uniform slab of conducting material may be
expressed as:
 l
l
R  ( )( ) where  =resistivity, t=thickness, =length/width
t w
w
l
Alternatively as R  Rs ( ) (ohms) where R s  sheet resistance=R
w
w
w
l
w
l
t
l
t
1 Rectangular Block
R = R (L/W) 
4 Rectangular Blocks
R = R (2L/2W) 
= R (L/W) 
4
Choice of Metals
• Until 180 nm generation, most wires were aluminum
• Modern processes often use copper
– Cu atoms diffuse into silicon and damage FETs
– Must be surrounded by a diffusion barrier
Metal
Bulk resistivity (m*cm)
Silver (Ag)
1.6
Copper (Cu)
1.7
Gold (Au)
2.2
Aluminum (Al)
2.8
Tungsten (W)
5.3
Molybdenum (Mo)
5.3
5
Sheet Resistance
Typical sheet resistance values for materials are very well characterized
Typical Sheet Resistances for 5µm Technology
Layer
Rs (Ohm / Sq)
Aluminium
0.03
N Diffusion
10 – 50
Silicide
2–4
Polysilicon
15 - 100
N-transistor Channel 104
P-transistor Channel 2.5 x 104
6
Sheet Resistance
Note: L defined parallel to current and W defined perpendicular to current.
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Sheet Resistance
8
Rs for poly is 4 /square in 1micron tech.
Rpoly = 4 /square x (19/3 + 11/4 + 19/3) squares = 61.6 .
A note: A corner square has a sheet resistance of ~0.5 Rs.
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Example
Example:
R = Rs(poly) * 13 + 2*(1/2) + 3*(1/2) squares
R = 4Ω/sq * 15.5 squares = 62Ω
Corner (1/2 Square)
1/2 Square
1/2 Square
Corner (1/2 Square)
Corner (1/2 Square)
10
Resistance Estimation
Channel resistance can be estimated in the linear region as:
1
1
L
Rc 
  ohms 
mCox (VGS  Vt )  W 
K (VGS  Vt )
A range of 1,000 to 30,000 ohms/square are possible for n-channel and
p-channel devices.
Temperature changes both m (mobility) and Vt (threshold voltage)
and therefore channel resistance.
Channel resistance increases with temperature, approximately
+0.25% per degree C above 25 degrees.
Metal and poly resistance change about 0.3% and well diffusions
about 1% per degree C.
11
Capacitance Estimation
Switching speed of MOS systems strongly dependent:
Parasitic capacitances associated with the MOS transistor.
Interconnect capacitance of "wires".
Resistance of transistors and wires.
Total load capacitance on the output of a CMOS gate is sum of:
Gate capacitance (of receiver logic gates downstream).
Driver diffusion (source/drain) capacitance.
Routing ( line ) capacitance of substrate and other wires.
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MOS Capacitor Characteristics
The capacitance-voltage characteristics of an MOS structure depend on the
state of the semiconductor surface.
Depending on gate voltage, the surface may be in :
accumulation
depletion
inversion
13
MOS Capacitor Characteristics
In accumulation:
In deletion mode
14
MOS Capacitor Characteristics
In inversion mode:
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Diagrammatic representation of parasitic
Capacitances of MOS
The capacitance of a MOS transistor can be modeled using 5 capacitors
The overlap of gate over the drain and source is assumed to be zero.
An approximation of gate capacitance (Cgs , Cgd and Cgb ) is given as:
Cox 
K SiO 2 ox
tox
16
Estimating Gate Capacitance
For example, for thin-oxide thickness of 15 nm
In  = 0.5 technology, W = 2 and L = 1
This is a conservative estimate of gate capacitance that does not include
fringing fields (extrinsic) gate capacitance.
Gate capacitance increases as the thin-oxide thins.
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The total gate Capacitance
18
The total gate Capacitance
The total gate Capacitance as a function of Vgs
The overall gate capacitance (for an n-device) is approximately equal to
the intrinsic “gate-oxide” capacitance for all values of gate voltage
except for voltages around the threshold voltage of the transistor, Vt
19
Circuit symbol for parasitic Capacitance
20
Estimating Source/Drain Capacitance
This model assumes a zero DC bias across the junction.
21
Estimating Source/Drain Capacitance
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Estimating Source/Drain Capacitance
For example:
Typical values for 0.5 micron process
n-channel device
Because of fan-out, gate capacitance usually dominates the loading.
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Estimating Routing Capacitance
Routing capacitance between metal and poly can be approximated using a
parallel-plate model.
The parallel-plate model approximation ignores fringing fields.
The effect of the fringing fields is to increase the effective area of the plates.
Consequently, poly and metal lines will actually have a higher capacitance than that
predicted by the model.
As line widths are scaled, the width (w) and heights of wires tend to reduce less
than their separations.
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Accordingly, this fringing effect increases in importance.
Estimating Routing Capacitance
C=Cplate*area+CFringe*peripheral
Example:
Poly: Cplate-poly*12*4+Cfringe-poly*2*(12+4) 
Metal:Cplate-metal1*12*4+Cfringe-metal1*2*(12+4) 
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Estimating Capacitance
Example:
Cg=4 * 2  Cox
CPoly=2* (2  * 2 ) Cpoly (plate) + 2* (2 + 2 + 2)  Cpoly (fringe)
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Estimating Capacitance
Example:
C‫[=نفوذ‬12 *3  + 4 *4  ]* C‫(نفوذ‬plate) +
(3 +12 + 1 + 4 +4+16 ) * c ‫نفوذ‬-‫جانبی‬
C‫=فلز‬6  * 10  * C(plate)+ 2*(6 + 10)  * C (fringe)
C ‫ =کل‬C ‫ نفوذ‬+ C‫فلز‬
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Multilayer capacitance calculations
Example: given the layout shown in the
figure calculate the total capacitance at
source and gate given that:
Ignore Fringing Capacitance
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Solution
29
Example
30
Example
31
Example
What are the parasitic capacitances visible from point “A”?
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Example
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Diffusion Parasitics Capacitance
34
Parasitics on 2-input NAND
• How can we estimate Cpdiff and Cndiff?
35
NAND Layout
C ndiff1  (4  4 1  3) 0.0625mm / 2  0.6fF / mm 2
 (5  4  4 1 1  3)  0.25mm /   0.2fF / mm
 0.7125fF  0.9fF  1.625fF
C ndiff 2 
3  2  0.0625mm / 2  0.6fF / mm 2
 (3  2  3  2)  0.25mm /   0.2fF / mm
 0.225fF  0.5fF  0.725fF
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NAND Layout
C pdiff1 
(4  4  1  3)  0.0625mm / 2  0.9fF / mm 2
 (5  4  4  1 1  3)  0.25mm /   0.3fF / mm
 1.07fF  1.35fF  2.42fF
C pdiff 2  C pdiff 1
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Diffusion Parasitics - Summing Up
W=3
L=2
A
W=3
L=2
B
A
W=3
L=2
B
W=3
L=2
Cndiff1
+ Cpdiff1
+ Cpdiff2
= 6.465fF
Cndiff2 = 0.725fF
38
Delay in Long Wires - Lumped RC Model
• What is the delay in a long wire?
in
L
out
• Lumped RC Model:
R = Rs * L / W = r*L
(r = Rs / W - resistance per unit length )
C = L * W * Cplate = c*L
(c = W * Cplate - capacitance per unit length)
• Delay time constant (ignoring driving gate)
t = R * C = (Rs * L / W) * (L * W * Cplate )
= r * c * L2
39
Wire Delay Models
– Lumped RC Model
• Total wire resistance is lumped into a single R and total capacitance
into a single C
• Good for short wires; pessimistic and inaccurate for long wires
R
Vout
Vin
C
Vout(t) = VDD(1-exp(-t/RC))
V50%(t) = VDD(1-exp(-tPLH/RC))
τPLH ≈ 0.69RC
40
Wire Delay Models
T-Model
The above simple lumped RC model can be
significantly improved by the T-model as
R/2
R/2
Vin
Vout
C
 model
This model is used in Elmore Model
41
Delay in Long Wires -Distributed RC Model
• Alternative: Break wire into small segments
• Approx. Solution - 1st moment of impulse response
t(Vout )  rcL 2
rcL2
t(Vout ) 
2
NN  1
 2

for N  
• Important: delay still grows as square of length
42
Example
• Metal2 wire in 180 nm process
– 5 mm long
– 0.32 mm wide
– R = 0.05 /, Cpermicron = 0.2 fF/mm
• Construct a 3-segment -model
– R = 0.05 /
R= R *(5x10-3/0.32 mm ) => R = 781 
– Cpermicron = 0.2 fF/mm C= 0.2 fF/mm x 5x10-3 => C = 1 pF
260 
260 
260 
167 fF 167 fF
167 fF 167 fF
167 fF 167 fF
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44
45
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Elmore Delay Model
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Elmore Delay
• ON transistors look like resistors
• Pullup or pulldown network modeled as RC ladder
• Elmore delay of RC ladder
t pd 

Ri to sourceCi
nodes i
 R1C1   R1  R2  C2  ...   R1  R2  ...  RN  CN
R1
R2
R3
C1
C2
RN
C3
CN
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The Elmore Delay Estimation Technique
D5
tD4: delay
from src to D4
src
a
b
D4
D2
MUX
tD5 ≠ tD4 ≠ tD2
r5
src
r1
C5
r3
r4
C1
r2
C3
C4
C2
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Parasitic Diodes for CMOS Inverter
D1: between p-well and n-substrate
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Switching Power Dissipation of CMOS inverters
Vdsn
Vdsp
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