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Multi-Disciplinary Engineering Design Conference
Kate Gleason College of Engineering
Rochester Institute of Technology
Rochester, New York 14623
Project Number: 08311
FPGA BASED MULTI-PUPOSE DRIVER/DATA
ACQUISITION SYSTEM
Brian Pinkham – EE
Murtuza Quaizar –EE
Corey VanBlarcom -EE
Steven Fastrow –CE
Andrew Fitzgerald -CE
ABSTRACT
The objective of this project is to develop an integrated system
solution that has the capability of enabling PC applications to
acquire and control real time data through a re-configurable
FPGA system. This project will enable future capability that
can be defined and driven by PC applications. This systems
consists of three major functions, a custom designed circuit
board complete with data acquisition, and drivers,
reconfigurable FPGA, embedded PowerPC processor running
an HTTP server. The PowerPC, processor will allow the
versatility of running diverse software applications while at the
same time taking advantage of the custom designed, hardware
system.
AC
Power
Distribution
PC Interface
(GUI)
Test
Vectors
Button
FPGA
Recorded
Output Test
Vectors
Signal
Conditioning
(input)
Signal
Conditioning
(output)
16 Analog
voltage
Inputs
INTRODUCTION
16 Analog
Outputs
12 Digital
Inputs
This system enables PC applications to drive electronic Data
Acquisition and drivers for applications, including ASIC testing
and robotic environmental controls. For ASIC testing the
system must be fast, complete, trouble-free, and economical.
For robotic applications, the device must be robust and accurate
to acquire various environmental data, and drive a wide array of
onsite applications.
Therefore the project P08311, as a revision to the work of
P07301 will contribute significantly to the growing field of data
collection, by creating systems that are capable of acquiring
digital and analog inputs and driving digital and analog inputs.
12 Digital
Outputs
Figure 1: A Block Diagram of the System
The system is designed to be operated over a Web Browser via
Ethernet, using Virtex-4FX platform; an embedded PowerPC
with FPGA. This will enable future functionality that can be
defined though high level application.
This system has the versatility to acquire analog voltage inputs
and TTL/CMOS digital inputs to be implemented by an FPGA
based multi-purposed DAQ system. The final implementation
can support a robotic platform, and serve as viable testing
environment for testing digital ASICs.
Copyright © 2008 by Rochester Institute of Technology
Proceedings of the Multi-Disciplinary Engineering Design Conference
The objective of the design is to meet the desired specifications
and build a working prototype that includes a printed circuit
board. The working prototype will include analog input with
signal conditioning, digital I/O, analog current output, analog
voltage output, and controlling and interfacing software.
NOMENCLATURE
ADC: Analog to Digital Converter
ASIC: Application specific integrated circuit
DAC: Digital to Analog Converter
DAQ: Digital Acquisition
DATA ACQUISITION: The inputs to the System
DRIVER: The output of the FPGA based Data Acquisition
ELF: Executable Linker File
FIFO: First in First Out
FPGA: Field Programmable Gate Array
FTP : File Transfer Protocol
GUI: Graphical User Interface
HTTP: Hyper text transfer protocol
JAVA: Programming Language
Ksp/s: Thousands of Samples per seconds
I/O : Input-output
PC : Personal Computer
PCB: Printed Circuit Board
PIC : programmable integrated circuit
QNX : Supported Operating System for Xilinx ML403
OS : Operating System
RAM: Random Access Memory
MUX : Multiplexer
TTL/CMOS: Transistor-transistor Logic
VXWORKS: Supported Operating System for Xilinx ML403
XilCore: Supported Operating System for Xilinx ML403
Page 2
required to have a run time of 1 hour off an internal
rechargeable battery.
The above specifications were negotiated and were redefined as
the development process progressed. The battery capability was
eliminated from the project, as it required a great deal of
engineering time and had minimum impact on the final
presentation of the system.
The Development board that was selected was the Xilinx Board
for its sufficient number of I/O pins, its small and concise size,
and its technical support from the manufactures. The digital
inputs were reduced from 16 digital inputs and 16 outputs to 12
digital inputs and 12 digital outputs to meet the speed
specification.
The interface to the PC-Host changed from a GUI interface to a
system interface over a web browser. This change was
motivated by time constraints in implementing a JAVA
application communication protocol for PC-Host and
development board.
NEEDS
The goal of the FPGA Driver/Data Acquisition system was to
satisfy the needs of two existing customers. Professor George
Slack from the department of Electrical Engineering at the Kate
Gleason College needs to utilize the DAQ system to record and
output analog data in a robotic platform, and Dr. Marcin
Lukowiak, from the department of Computer Engineering at the
Kate Gleason College, needs to test an ASIC with digital inputs
and outputs.
It was planned that the system was to be presented in the form
of a GUI to be run on a PC host, backed by a supported
hardware. The FPGA based platform that Professor Lukowiak
had recommended, was a Diligent Development board.
SPECIFICATION
The hardware was originally designed with 24 analog voltage
inputs, 16 digital inputs, 8 Analog Voltage Output, 8 Analog
controlled Current Output and 16 digital outputs. The analog
signals had to accept voltage levels from 0 to 12 volts, with a
sampling rate of 20Ksp/s. The digital signals had to be
processed at the fastest possible rate. The system was also
Table 1: Specifications for the final deliverables for the DAQ
system
CONCEPTS
Figure 1 shows the system layout including each of the inputs
and outputs of the systems at the margins, while at the center
was the FPGA. The design was considered to have a hardware
that would interface with the environment, and support the
activities and functions of the FPGA which would reside as the
center of the project.
Project P08311
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Proceedings of the KGCOE Multi-Disciplinary Engineering Design Conference
The analog inputs and outputs, and the digital inputs and
outputs, and power management was developed by the
Electrical Engineers. And the FPGA, embedded processor and
the user interface was designed by the Computer Engineers.
with a ripple of 0.01dB and a 40dB per decade roll off. The
Filter consisted of two 2nd order SallenKey circuits, and voltage
attenuating circuit at the output. The recorded implementation
of the filter is shown below in Figure 2b.
DESIGN OF HARDWARE
Analog Inputs
The active analog Filter was one of the most important
hardware stages in order to ensure signal integrity for the
analog inputs. The inception of the input end of the Analog
design was tested against three different types of
implementations schemes.
The first was to multiplex or MUX the input, and then do the
filtering and signal condition between the multiplex and the
ADC. The second implementation idea was to filter the input
and then multiplex the input signals directly to the ADC.
Thirdly, the idea to use a micro controller to take the place of
the multiplexer, and serially connect the Analog input to the
FPGA, while doing the ADC within the PIC.
The first idea was eliminated due to propagation delay. The
idea behind the micro controller was a plausible alternative to
replacing the ADC, DAC, MUX and the COUNTER. However
this idea was also dropped due to the steep learning curve
associated with the implementation of this method. The third
idea, which was similar to the first, required for the filtering of
the analog input to occur before the MUX, rather then between
the MUX and ADC. It was chosen for its straightforward
solution.
Decision was made to design for a higher order low pass filter.
The motivation for this design was the needed capability of
meeting the customer’s specification to sample data at 20Ksp/s.
According to the Nyquist theorem, to sample at 20KHZ, no
more than a 10KHZ signal was expected to be at the input of
the ADC. Any signal of significant amplitude that was passed
through with a frequency greater then 10KHZ, would alias and
potentially distort all other inputs from that channel.
Therefore, a steep 3dB cutoff was designed with an earlier
frequency roll off.
R49
C38
0.068uF
C39
0.056uF
U7A
953
953
C40
0.18uF
C35
0.068uF
IN+
V-
11
C37 12V
0.027uF
7
OUT
R57
10
U7B
1K
IN+
V+
5
412
4
OUT
R56
12V
LM324M
9
IN-
V-
VV+
R55
4
IN+
1.1K
1
V+
3
AnalogInput31.05K
LM324M
6
IN-
OUT
R54
4
R53
-12V
11
-12V
11
-12V
LM324M
2
IN-
12V
Figure 2b: Voltage input (top), and filtered voltage output
(bottom)
The output from each of these 16 filters goes into one of two 8
channels multiplexers (ADG408). These multiplexers were
used to switch between all 16 input channels and were chosen
for their fast switching speeds (250ns) and low ‘Turn On’
resistance (<100 ohms).
The multiplexers are addressed by the output of one 4 bit binary
counter, which is incremented by the FPGA. This was done to
minimize the number of connections that needed to go to the
FPGA.
Analog to Digital Conversion 2 8ch muxes
Anti-Aliasing Filter
with unfavorable gain
16
analog
voltage
inputs
(0-12V)
1
2
3
4
5
6
7
8
8 ch Analog
Multiplexer
(DG408DY)
Analog to
Digital
Converter
(ADC121S101)
5V scaled input signal
SDATA1
CS (enable)
6 I/O
Pins
used on
the
FPGA
SCLK
9
10
11
12
13
14
15
16
Analog to
Digital
Converter
(ADC121S101)
8 ch Analog
Multiplexer
(DG408DY)
SDATA2
8
U7C
R163
33.2
0
AnalogSelect3
4-bit binary
counter
(74VHC39)
Figure 2a: PSPICE schematic view of the Low pass Chebyshev
filter of the 4th order
RESETcnt
CLKcnt
Figure 3: Complete design of the Analog to Digital Conversion
A Low pass Chebyshev filter of the 4th order, shown in Figure
2a. Cutoff frequency was designed at approximately 1.4K Hz,
Copyright © 2008 by Rochester Institute of Technology
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Proceedings of the Multi-Disciplinary Engineering Design Conference
The output from the multiplexers enters the inputs of two
analog to digital converters (ADC121S101). The voltage
values read at these inputs is then converted into a 12 bit binary
representation and transmitted to the FPGA serially at a sample
rate of 500KS/s.
The other 8 channels were for the Voltage output circuit, shown
below in Figure 5a, and took similar voltage level from the
FPGA and scaled it to 0 to 12 volts.
+2.5V
The complete conceptual design of the analog to digital
conversion was implemented, and is shown in Figure 3.
R97
10K
R99
V_OUT1
Analog Outputs
48.7K
-12V
LM324M
11
2
IN-
The output to the data acquisition board had 16 channels. Of
those channels, 8 are allocated for analog current output, seen
in Figure 4a. Those current outputs ranged from 0-20mA given
an input of 0 to 5 V from the FPGA board, shown in Figure 4b
VR103
OUT
PRE_VOUT1
3
IN+4
U19A
V+
12V
V2
12
V5
12
C3
.1uf
C4
.1uf
1
1K
0
Figure 5a: PSPICE schematic view of the Output Voltage
Source
I
350
Rload
0
U2A4
3
V6
Q3
+
V
V1 = 0
V2 = 5
TD = .001
TR = .5
TF = .5
PW = .7
PER = 2
V+
OUT
1
2
- 11
LM324/NS
Q2N4063
V-
C2
.1uf
Rsense
250
Figure 5b: Voltage input (channel 1), and scaled voltage output
(channel 3)
V4
-12
0
C5
.1uf
Digital Inputs and Output
The Digital input for the Data acquisition system was taken
from an ASIC and other various DAQ applications. The inputs
were meant to be highly modular and fully reconfigurable
giving the user full control of what is designated to be an input
or output. The 12 digital inputs and 12 digital outputs are
interchangeable and reconfigurable. The digital inputs and
outputs are directly tied into the FPGA, meeting the
specification for having the signals be as fast as the electronic
devices were capable.
0
Figure 4a: PSPICE schematic view of the Output Current
Source
5.0V
2.5V
SEL>>
0V
V(V6:+)
20mA
Power Management
10mA
Power was supplied from an ATX power source. The supply,
was rated at 250 W, it supplied all the voltages needed for full
functionality of the FPGA Multipurpose system.
0A
0s
0.5s
1.0s
1.5s
2.0s
2.5s
3.0s
3.5s
4.0s
4.5s
-I(Rload)
Time
Figure 4b: Current output (bottom) Vs. Voltage in (top)
5.0s
Though the power requirement was reduced significantly from
having to design a board with a rechargeable battery to using an
ATX power supply, power management was still a key issue.
Project P08311
Proceedings of the KGCOE Multi-Disciplinary Engineering Design Conference
The option to select a number of different voltage outputs for
the digital inputs and digital outputs was made available on the
hardware system. The Voltages were selected using a jumper
at the output of a specified voltage. These voltages were
floating at the end of a voltage regulator, until a jumper closed
the loop on the requested voltage.
PCB Board
Page 5
The FPGA based Development board that was selected had the
most features, support, and minimal size. The Diligent
Development Board, which was favored by the customer, had
similar favorable features, but lacked support. Therefore the
team decided to go with another FPGA platform, which would
have technical support, since there was little to no prior
experience in programming for a Software /Hardware codesign.
The Printed Circuit board layout was done using the PCAD tool
software. The final revision of the board, was a 12 ½ x8 ½ in
with 4 layers, and a one ounce copper.
Figure 7: Top view of the Development board Xilinx ML403
Figure 6: PCB implementation of the hardware design
The top and bottom layer served as the majority of the routing
layer, Layer 2 was created as the power plane for the -12V,
+12V, and +5V, and Layer 3 was designed to be the Ground
plane. The 4 layer board solution was expensive but necessary
for signal integrity and noise consideration.
The Bottom right corner of the board has 2 rows of 32 pin
headers that were designed to mate with the Development
board from the top. Finally the left most connector was an open
connection for the ATX power supply.
The board was done with experienced hands and was reviewed
by an outside firm that generously gave their time to reviewing
our board.
DESIGN OF FPGA PLATFORM
The team chose the Xilinx ML403, for its numerous and
winning features. It had an Ethernet port, USB, 64 I/O pins,
compact flash, LCD screen, LCD diodes, and buttons and
switches which were useful when debugging.
Operating System
Time and resources was spent in selecting the most appropriate
Operating System to support the communication line between
the PowerPC processor and the FPGA. Before deciding upon
the final operating system, it was evaluated that three different
operating systems, QNX, VXWORKS, and XilCore were
viable to use.
Originally, the QNX operating system was to be used, because
it came packaged with the Xilinx-ML403. However this
operating system was difficult to use, and difficult to load on
the development system and therefore had to be neglected.
Software-Hardware Co-Design
This project offered a unique challenge to the team, since no
one had previously developed code to support both the software
end, which included the embedded processor, and the hardware
end, which was the FPGA.
Development Board
Next VXWORKS was tried. In fact, though VXWORKS was
proprietary software of Wind River, Tom Wall, a representative
from Wind River offered the use of the Operating systems
without cost, as members of the RIT community. He also
offered much of his valuable time to help support VXWORKS
on the Xilinx-ML403. But even with the efforts of Mr. Wall,
the OS was unable to run on the development board
successfully. After much speculation it was seen that though
the Xilinx-ML403 claimed to be supported, the author of that
application note never tested it on its platform, and
Copyright © 2008 by Rochester Institute of Technology
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Proceedings of the Multi-Disciplinary Engineering Design Conference
VXWORKS was abandoned all together.
XilCore was finally selected as the OS, which is a Xilinx
kernel.
User Interface
There was also the limited resources of the development system
that had to be considered. The Development project was
constraint with an original budget of twelve hundred dollars.
However, since most of the cost had to be budgeted for the
development board and the creation of the PCB, the team had
half the amount of the original budget to work with.
A web browser was used to interface with the embedded
processor using HTTP. This would require the user to load all
their driver values (i.e. test vectors) on the compact flash, and
control the configurations that they would want through a web
page.
WFIFO2IP_RdAck = '0'
WFIFO2IP_empty=’0'
wfifo_read
IP2WFIFO_RdReq = '1'
wfifo_data=WFIFO2IP_Data
The original design of the system was to have a GUI
implementation run on a host PC interface to the DAQ system.
What it would have done was set up a FTP protocol using a
JAVA APP, and allow the user to interface with the embedded
processor (having it to run commands and etc), which in turn
would have interfaced with the FPGA on the system.
WFIFO2IP_empty=’1'
idle
WFIFO2IP_RdAck = '1'
wfifo_push
dig_out =
wfifo_data(31 downto 20)
IP2WFIFO_RdReq = '0'
FPGA Implementation
A FIFO data scheme to pass data to and from the FPGA, as
shown in Figure 8. Specifically, 4 FIFO data buffers were
used. The first pair of FIFOs was used for the digital inputs
and outputs. The second pair of FIFOs was used for the digital
information from the analog section’s inputs and outputs. For
the read (input) FIFOs, data is passed in at a user specified
clock rate. The information is then read in the embedded
processor as fast as possible. This information is then written
to the on board compact flash card via SystemAce controller.
Information is passed from the output FIFO at the same user
specified clock rate to the output pins on the development
board.
RFIFO2IP_Full = '0'
rfifo_get
rfifo_data = dig_in & X"00000"
RFIFO2IP_Full = '1'
idle
The DAC and the Counter are both connected to the FPGA,
which controls the timing and flow of its operation on the
Analog end of the DAQ system
rfifo_write
RFIFO2IP_WrAck = '1'
IP2RFIFO_WrReq = '1'
IP2RFIFO_Data <= rfifo_data
ANALYSIS & EVALUATION
RFIFO2IP_WrAck = '0'
HARDWARE IMPLEMENATION
Figure 8: The FIFO algorithm implementation for the FPGA
The initial analysis and evaluation of the functionality of the
hardware was done on computer simulation (the filter system,
and the voltage and current outputs). The next step was to bread
board, including the multiplexers, DAC, and ADC.
The Altera Flex 10K was used to emulate the performance at
the FPGA end of the Xilinx ML403 while the development
board was being worked on, to test the performance of the
system hardware.
Since Vivace Semiconductor allowed the use of their lab and
equipment, the purchase of surface mount components as small
as 0805 for the final implementation was a feasible design
improvement. .
Special interest was take in insuring solid connections between
the supported hardware and the development board, by using
SAMTEC parts, which had gold planted pins and connectors.
FPGA/OS IMPLEMENATION
Implementation on the software end was trying to get the
embedded PowerPC processor to establish a communication
link to the FPGA, as shown above in Figure 9. Doing so
required the need to get through much of the convoluted
operations and workings of the development board. Due to a
Project P08311
Proceedings of the KGCOE Multi-Disciplinary Engineering Design Conference
manufacturers defect, the software that came with the
development board, EDKv9.2, didn’t generate code to talk with
the peripherals of the system. The older version of the same
software, EDKv8.2 was then reverted, which was used to
generate the ELF file containing the code for the embedded
processor, while still using EDKv9.2 for its efficiency in
compiling the bit stream to program the FPGA.
PPC
GPIO BUS
32-Bits Wide (Bi-Directional)
Read FIFO
(32-Bits Wide)
(512 Entries Deep)
(2 MB)
Write FIFO
(32-Bits Wide)
(512 Entries Deep)
(2 MB)
DAQ Control Unit
(State Machines)
Expansion Header
(32 Pin I/O)
Figure 9: Hardware (FPGA), software (PowerPC)
implementation
Resource management with respect to logic cells, called
‘slices,’ became an issue when the FPGA was being worked to
its memory capacity. As the code got more complicated and
lengthy, the download cable became unusable because of a lack
of available memory in the B-RAM. Therefore instead of
downloading the bit stream from the cable, it was compiled into
a SYSTEM ACE file, which placed the software on the
compact FLASH card that copied the software onto the S-RAM
that had more memory, instead of the B-RAM which did not
have as much memory available.
TESTING
DATA ACQUISITION
Testing and confirmation of the basic operations of the power
system and power management on the board were evaluated by
the LED test lights that were placed on the PCB. And all
individual stage of the hardware was tested independently, such
as the filter system, the operation of the multiplexer, and the
operation of the ADC. The output of the system between the
DAC to the voltage output, and current output were also tested
independently of the entire system. When validity of the
subsystems was confirmed, then the entire data acquisitions and
drivers was placed in operational mode and tested. This was
Page 7
done independent of the Xilinx ML403 board, which was still
under development during, using instead the Altera FLEX
FPGA.
FPGA
Due to the nature of the design, Software unlike hardware was
being designed, implemented and tested each step of the way.
Therefore, the software was not expected to be finished till the
end of the project cycle.
The testing on the Development board made aware of some of
the design issues that would have otherwise been missed.
When the ability to read and record data on the FPGA was
implemented, it was observed that the Digital input was never
at a value that was expected from it. For example, when the
digital inputs was not connected to anything, it was expected
that the recoded data would be all zeros. However what was
observed was a random set of ones and zeros, in no particular
order. The issue was resolved when pull down resistors were
introduced to each of the digital inputs. This solution provided
a definite state to each of the digital inputs, as oppose to leaving
them floating and holding an unknown value.
RESULTS
HARDWARE
All aspects of the design was tested, and proved that the system
was a success. The system delivered the customers with an
operational data acquisition and drivers. The data acquisition
offers a rugged signal processing for the analog inputs, which
can be seen in Figure2b. The drivers on the system provide for
a proportional voltage and current outputs.
Through this testing period, issues were raised and the designs
was re-evaluated but the ultimate goal of the project was still
being met: to test digital data – (very important) and have some
operating range over the analog input and analog output.
After overcoming fundamental operational issues, testing of the
performance of the system revealed that the filtering and the
attenuation had to be modified on the Schematic Level. Due to
missing capacitors on the feedback of the second stage of the
filter, there was a unstable amount of noise that was resonating
through the ground and power traces. This issue was resolved
by eliminating the additional stage and appending those
changes for a revised schematic.
During testing, the current outputs showed a non linear
relationship between the input voltages and the output current.
Further hardware testing and simulation indicted that the
problems varied. There were issues with the switched polarity
on the operational amplifier. And the polarity of the BJT had
to be switched to conform to manufactures specifications.
Similarly a non linear relationship was being observed on the
voltage output of the system. Through bread boarding it was
made apparent that what was expected on the simulation for the
Copyright © 2008 by Rochester Institute of Technology
Proceedings of the Multi-Disciplinary Engineering Design Conference
voltage driver was not what we were actually observing. In
order to provide for an input range of 0 to 5 volts from the
FPGA, a 2.5 offset voltage was provided instead of ground.
This provided the input with a swing of 0 to 5V peak to peak,
where 0 would have corresponded with -12V, and 5 volts
would have corresponded to +12V. Instead what was observed
was an offset of about 3.3V’s and clipping on the top rail. The
issue was resolved by switching through resistance values from
the feedback, till clipping at the output was minimized.
SOFTWARE
In testing, the Memory Flash card was used extensity to build
and verify code written on the development board. However
due to the Memory Flash Card’s use; the, the connector that
was mounted under the development board inevitably broke.
The connector was fixed, and the fix provided for it a stable
connection, and a convenient accessibility to the slot.
Page 8
system, so more were added for each and every different
power rail, instead of just the +/-12V and the +5V rail.
Also issues with creating a GUI implementation to run on a
host PC interface to our DAQ system would have been
resolved. The code for the GUI implantation has been written,
and can be used as a future design and improvement on our
own system.
All of the above changes and suggestions have been noted for
future work on the system. The Schematics have been updated
to include the changes that would have made on a revised PCB
board and all other records and progress is viewable on SVN.
It is recommended that future work on the FPGA based
Data/Acquisition system use a different platform besides the
Xilinx ML403 for its FPGA implementation. It is suggested
that the TI DaVinci be used as a possible alternative.
CONCLUSION
Testing was completed, and proved that majority of the project
specifications were met.
On the input side, the anti-aliasing provided an exact 3dB
cutoff at 1.4KHz. However since the attention stage was
removed during the testing phase, the customer now has a
dynamic range of up to 0 to 5 volts, instead of the original 0 to
12V.
The counter and the Multiplexer functioned to provide a fast
and accurate switching between the 16 analog inputs to provide
for the desired sampling time.
The current output was shown to be linearly responsive to a 0
to 5V input from the FPGA. Similarly the voltage output was
also proportional to the 0 to 5V input from the FPGA. And
dynamic rage was redesigned to be 15V peak to peak, instead
of 24V peak to peak.
ACKNOWLEDGEMENTS
Special Thanks and acknowledgments goes to all of the
individuals that helped in the creation of the DAQ system.
In particular we would like to extend our thanks to Tom Wall
from WindRiver, for his time and commitment to the team.
Thanks to Mark Indovina and all the employees at Vivace
Semiconductor for letting us present our ideas, critically
evaluating those ideas, and for letting us use their lab as late as
we needed. The team would like to similarly thank Carl
Kosmeral for his review of our initial design. Thanks also goes
out to the employees of Cadex Design for looking over our
PCB board, before it went into production. And finally, thanks
to the RIT faculty for assisting in our design, namely Professor
Hopkins, Professor Philips, and of course our Customers,
Professor Slacks, and Professor Lukowiak.
REFERENCE
Griffin, Richard, “VxWorks on the ML403 Embedded
Development Platform, 2007 Wind River
RECOMMENDED FUTURE WORK
Given an extra quarter to work on the project, the limitations
that were imposed on the customers’ original specifications
would have been resolved
Some of these changes include, adding an additional inverting
op-amp to the input stage, and correcting the second stage filter
which would provide for the dynamic range of 0 to 12V.
For the output end, the reference voltage was changed from
2.5V to 3.3V, which will give the customer the full dynamic
range of 24V peak to peak.
Wind River “Wind River General Purpose Platform,VxWorks
Edition”2007 Wind River Systems, Inc
Wind River, “Wind River VxWorks Platforms” 2007 Wind
River Systems, Inc
Xilinx, “Embedded Audio Demultiplexer Reference Design for
Xilinx FPGAs” , 2008
Additional trouble shooting components that would have
helped in debugging the PCB board have been appended to a
revised schematic. These would have included more testing
pads, around the analog inputs, DAC, ADC and around the
digital inputs and digital outputs. Also when debugging the
board, it was realized that LED lights were helpful on the
Project P08311