Download Switched Capacitor Filters

Switched Capacitor Filters
Franco Maloberti
F. Maloberti: Switched Capacitor Filters
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OUTLINE
• Switched capacitor technique
• Biquadratic SC filters
• SC N-path filters
• Finite gain and bandwidth effects
• Layout consideration
• Noise
F. Maloberti: Switched Capacitor Filters
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SWITCHED CAPACITOR TECHNIQUE
• An active filter is made of op-amps, resistors and capacitors.
• The accuracy of the filter is determined by the accuracy of the
realized time costants since the capacitors and resitors are
realized by uncorrelated technological steps
 δτ
-----
 τ
2
δR 2  δC 2

= ------- + ------ R
 C
• In CMOS technology δR ⁄ R ≈ 40% ; δC ⁄ C ≈ 30% ; hence
unacceptable for most of the applications
δτ
----- ≈ 50% ,
τ
•Hybrid realization with functional trimming
•Problems for a fully integrated realization
F. Maloberti: Switched Capacitor Filters
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•
Accuracy
•
Values of capacitors and resistors: for 70 nm oxide thickness 1
pF --> 2000 µ2; 10 pF is a large capacitance. To get τ = 10-4 sec
R = 107 Ω
The above problems are solved by the use of simulated resistors
made of switches and capacitors.
MOS technology is suitable because:
•Offset free switches
•Good capacitors
•Satisfactory op-amps
F. Maloberti: Switched Capacitor Filters
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Simple SC structures
I
V1
Φ1
Φ2
C
Φ1
1
I
Φ2
V1 Φ1
C
V2
1
T
V2
Φ2
T
∆Q = C1 (V1 - V2) every ∆t = T
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I
I
V1 – V2
∆Q = i∆t = -------------------T
R
V1
V2
T
t
The two SC structures are
(on average) equivalent to a resistor
T
R eq = ------C1
If the SC structures are used to get an equivalent time constant τeq = ReqC2
it results:
τ eq
F. Maloberti: Switched Capacitor Filters
C2
= T ------C1
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•
Its accuracy depends on the clock and on the capacitor matching
accuracy
•
If τeq=40 T C2 = 40 C1 (acceptable spread) regardless of the
value of τeq
A more complex SC structure:
V1
Φ1
Φ2
Φ2
Φ1
V2
∆Q = 2C 1 ( V 1 – V 2 )
The charge is transferred twice per clock period T or we assume as
clock period half of the period of phases Φ1 and Φ2.
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SC INTEGRATOR
C2
R1
_
+
Starting from the continuous-time circuit of the Integrator, we can obtain a SC integrator by replacing the continuous-time resistor with the
equivalent resistances.
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C2
Φ2
Φ1
C1
_
Φ1
+
C2
Φ2
_
Φ1
C1
Φ1
+
C2
Φ2
Φ1
C
Φ2
F. Maloberti: Switched Capacitor Filters
_
1
Φ1
+
Φ2
Φ1
9
•We consider the samples of the input and of the output taken at
the same times nT (the end of the sampling period).
•
Structure 1:
C1
V out [ ( n + 1 )T ] = V out ( nT ) – ------- V in ( nT )
C2
taking the z-transform:
C1
V out ( z )
1
------------------- = – ------- ⋅ -----------C2 z – 1
V in ( z )
•
Structure 2:
C1
V out [ ( n + 1 )T ] = V out ( nT ) – ------- V in ( n + 1 )T ]
C2
taking the z-transform:
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C1
V out ( z )
z
------------------- = – ------- ⋅ -----------C2 z – 1
V in ( z )
•
Structure 3:
C1
V out [ ( n + 1 )T ] = V out ( nT ) – ------- { V in [ ( n + 1 )T ] + V in ( nT ) }
C2
taking the z-transform:
C1 z + 1
V out ( z )
------------------- = – ------- ⋅ -----------C2 z – 1
V in ( z )
Remember that for the continuous-time integrator:
V out ( s )
1
------------------- = – -----------------V in ( s )
sR 1 C 2
Comparing the sampled-data and continuous-time transfer functions we get:
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•
Structure 1:
T
R 1 → ------C1
•
FE approximation
1 (z – 1)
s → --- ----------------T z
BE approximation
Structure 2:
T
R 1 → ------C1
•
1
s → --- ( z – 1 )
T
Structure 3:
T
R 1 → ---------2C 1
2 (z – 1)
s → --- ----------------T (z + 1)
Bilinear approximation
•It does not exist a simple SC integrator which implement the LD
approximation.
•Note: the cascade of a FE integrator and a BE integrator is
equivalent to the cascade of two LD integrators.
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C2
C1'
_
Φ1
C2'
_
Φ2
C1
+
Φ1
Φ2
+
•The key point is to introduce a full period delay from the input to
the output
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•The same result is got with:
C2'
C2
_
Φ1
Φ2
C1
F. Maloberti: Switched Capacitor Filters
+
Φ2
_
Φ1
C1'
+
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STRAY INSENSITIVE STRUCTURE
The considered SC integrators are sensitive to parasitics.
Toggle structure:
•
The top plate parasitic capacitance Ct,1 is
in parallel with C1
•
It is not negligible with respect to C1 and
it is non linear
•
The top plate parasitic capacitance Ct,1
acts as a toggle structure
Bilinear resistor:
F. Maloberti: Switched Capacitor Filters
Φ2
Φ1
C1
Ct,1
Cb,1
Φ2
C1
Φ1
Ct,1
Cb,1
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•
•
•
Both the parasitic
capacitances Ct,1, Cb,1 act
as toggle structures. Their
values are different (of a
factor ≈ 10) and they are non
linear.
Stray insensitivity can be got
for the first two structures if
one terminal is switched
between points at the same
voltage.
The right-side parasitic
capacitor is switched
between the virtual ground
and ground (note: even in
DC Vv.g. must equal Vground)
F. Maloberti: Switched Capacitor Filters
Ct,1
Φ1
C1
Φ2
Φ2
Φ1
Cb,1
C1
Φ1
Φ2
Φ1
Φ2
Virtual
ground
C1
Φ1
Φ2
Φ1
Virtual
ground
Φ2
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•
The left side capacitor is connected, during phase 1, to a voltage
(or equivalent) source.
•
The charge injected into virtual ground is important, not the one
furnished by the input source.
•
Structure A is equivalent to the toggle structure, but the injected
charge has opposite sign.
•
Equivalent negative resistance allows to implement non inverting
integrators.
•
It is possible to easily realize a stray insensitive bilinear resistor
with fully differential configuration.
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SC BIQUADRATIC FILTERS
Consider a (continuous-time) biquadratic transfer function
2
p 0 + sp 1 + s p 2
H ( s ) = ---------------------------------------ω0
2
2
s + s ------- + ω 0
Q0
If the bilinear transformation is applied, it results a z-biquadratic transfer function
2
a 0 + za 1 + z a 2
H ( s ) = ---------------------------------------2
b 0 + zb 1 + z b 2
where the coefficients are:
2
4
a 0 = p 0 – ---p 1 + -----2- p 2
T
T
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8
a 1 = 2p 0 – -----2- p 2
T
2
4
a 2 = p 0 + ---p 1 + -----2- p 2
T
T
b0 = ω0
2
2 ω0 4
– --- ------ + -----T Q T2
2
8
b 1 = 2ω 0 – -----2
T
b2 = ω0
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2
2 ω0 4
+ --- ------ + -----T Q T2
19
All the stable z-biquadratic transfer functions are realized by the topology:
E
C
F
D
1
G
B
-
A
H
+
V01
+
V02
I
J
F1
F2
Vin
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t
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Features:
•Loop of two integrators one inverting and the other noninverting.
•Damping around the loop provided by capacitor F or (and)
capacitor E (usually only E or F are included in the network).
•Two outputs available V0,1 V0,2.
•Denominator of the transfer function determined by the capacitors
along the loop (A, B, C, D, E, F).
•Transmission zeros (numerator) realized by the capacitors (G, H,
I, J).
•Input signal sampled during Φ1 and held for a full clock period
•Charge injected into the virtual ground during Φ1.
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Charge conservation equations:
DV0,1(n+1) = DV0,1(n) - GVin(n+1) + HVin(n) - CV0,2(n+1) - E[V0,2(n+1) - V0,2(n)]
(B + F)V0,2(n+1) = BV0,2(n) + AV0,1(n) - IVin(n+1) + JVin(n)
Taking the z-transform and solving, it results:
2
V 0, 1
( IC + IE – GF – GB )z + ( FH + BH + BG – JC – JE – IE )z + ( EJ – BH )
H 1 = ----------- = ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2
V in
( DB + DF )z + ( AC + AE – 2DB – DF )z + ( DB – AE )
2
V 0, 2
DIz + ( AG – DI – DJ )z + ( DJ – AH )
H 2 = ----------- = ------------------------------------------------------------------------------------------------------------------------------------------2
V in
( DB + DF )z + ( AC + AE – 2DB – DF )z + ( DB – AE )
•
10 Capacitors
•
6 Equations a0, a1, a2, b0, b1, b2
•
Dynamic range optimization
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•
Scaling for minimum total capacitance in the groups of capacitors
connected to the virtual ground of the op-amp1 and the op-amp2.
•
Since there are 9 conditions, one capacitor can be set equal to
zero
E=0
“F type”
F=0
“E type”
Firstly the 6 equations are satisfied. Later capacitors D and A
are adjusted in order to optimize the dynamic range. Finally all
the capacitor connected to the virtual ground of the op-amp are
normalized to the smaller of the group.
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Scaling for minimum total capacitance
Cn
C1
_
C2
+
C3
C4
Assume that C3 is the smallest capacitance of the group. In order to make
minimum the total capacitance C3 must be reduced to the smallest value allowed by the technology (Cmin)
•
Multiply all the capacitors of the group by
C min
k = -----------C3
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SC LADDER FILTERS
Orchard’s observation
Doubly-terminated LC ladder network that are designed to effect maximum power transfer from source to load over the filter passband feature very low sensitivities to value component variation.
Syntesis of SC Ladder Filters:
Symple approach
•
Replace every resistance Ri in an active ladder structure with a
switched capacitor Ci = T/Ri.
•
Use a full clock period delay along all the two integrator loop (it
results automatically verified in single ended schemes).
It results an LD equivalent, except for the terminations.
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Quasi LD transformation:
Attenuation
DESIRED SPECIFICATION
Asb
Apb
wpb
wsb
w
Attenuation
PREWARPED SPECIFICATION
Asb
Apb
sin( w pb T/2)
w
sin( w sb T/2)
Prewarp the specifications using sin(ωT/2)
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Effect of the terminations:
C3
R
C2
_R
1
_
C1
+
C2
_
+
R3
C1
H DI ( s ) = --------------------------------------- if R1 = T/ C1 and R3 = T/C3 we get: H DI ( s ) = ---------------------------sC 2 R 1 R 3 + R 1
sTC 2 + C 3
V out ( n + 1 ) ( C 2 + C 3 ) = V out ( n )C 2 + C 1 V in ( n )
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Taking the z-transform we get:
zV out ( C 2 + C 3 ) = C 2 V out + C 1 V in
–1 ⁄ 2
C1
C1 z
H DI ( z ) = ----------------------------------------- = --------------------------------------------------------------------1⁄2
–1 ⁄ 2
1⁄2
C 2 ( z – 1 ) + zC 3
C2 ( z
–z
) + z C3
along the unity circle z=ejωT
– j ωT ⁄ 2
H DI ( e
jωT
– j ωT ⁄ 2
C1 e
C1 e
) = ------------------------------------------------------------------------------------- = --------------------------------------------------------------------------------jωT ⁄ 2
– j ωT ⁄ 2
jωT ⁄ 2
ωT
ωT
C2 ( e
–e
)+e
C3
2j ( C 2 + C 3 ) sin -------- + C 3 cos -------2
2
The half clock period delay will be used in the cascaded integrator in
order to get the LD transformation
•
The termination is complex and frequency dependent.
•
The integrating capacitor C2 must be replaced by C2 + C3/2.
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Complex termination:
C3
C1
C2
_
F1
+
Note: the output voltage changes during Φ
2
C2
V out ( n + 1 )C 2 = V out ( n ) -------------------- + C 1 V in ( n )
C2 + C3
Taking the z-transform:
C2 C3 

zV out C 2 = V out C 2 – -------------------- + C 1 V in

C 2 + C 3
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–1 ⁄ 2
C1 z
C1
H DI ( z ) = ---------------------------------------------------- = ------------------------------------------------------------------------------------C2 C3
1⁄2
–1 ⁄ 2
–1 ⁄ 2 C2 C3
C 2 ( z – 1 ) + -------------------------------------C2 ( z
–z
)+z
C2 + C3
C2 + C3
along the unity circle z=ejωT
– j ωT ⁄ 2
C1 e
jωT
H DI ( e ) = ---------------------------------------------------------------------------------------------------------------C2 C3
ωT
1 C2 C3 
ωT

2j C 2 – --- -------------------- sin -------- + -------------------- cos -------
2
C2 + C3
2 C 2 + C 3
2
•
•
The imaginary part of the contribution of the termination is
negative
The integrating capacitor
F. Maloberti: Switched Capacitor Filters
C2
must be replaced by
1 C2 C3
C 2 – --- -------------------2 C2 + C3
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Example: 5th order filter
RS
IS
L2
L4
V1
V3
Vin
I2
Passive prototype
R6
_ V2
+
1
F. Maloberti: Switched Capacitor Filters
1
_ R/R
6
+
τ5
T
τ4
T
1
6
1
τ3
T
1
_V
+
1
τ2
T
+
-
1
V4
+
+
τ1
T
_1/s τ5
1
1
implementa-
_ 1/s τ
4
_
+
+
+
_ 1/s τ
3
_ V5
-
Vs
_1/s τ
2
_
+
_1/s τ1
R/Rs
_
-
+
V3
_
_
C5
+
_ V1
_
C3
-
Vin
SC
tion
I6
I4
C1
Flow diagram
Vout
V5
1
1
33
FINITE GAIN AND BANDWIDTH EFFECT
C2
C1
_
+
If the op-amp has finite gain A0 the “virtual ground” voltage is V0/A0
V0 ( n + 1 )
1
1


C 2 V 0 ( n + 1 ) 1 + ------ = C 2 V 0 ( n ) 1 + ------ – C 1 V in ( n + 1 ) + ------------------------

A 0
A 0
A0
z-transforming:
C1 z
Vo ( z )
H ( z ) = --------------- = – ---------------------------------------------------------------V in ( z )
C1
1

C 2 1 + ------ ( z – 1 ) + ------- z

A0
A 0
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Comparing H(z) with the transfer function with
A0 → ∞
C1 z
H id ( z ) = – -----------------------C2 ( z – 1 )
H id ( z )
H id ( z )
H id ( z )
H ( z ) = ---------------------------------------------------------- = ----------------------------------------------------------------------------------- = ---------------------------------------------------------------------------------------C1
C1
C1 
C1 z + 1

z
1
1 1
1
1
1
1


 1 + -----1 + ------- + --------------- ------------ + --- + --- + --------------- ----------- 1 + ------- + --- --------------- + ------------------- -----------

A 0 C 2 A 0  z – 1 2 2
A 0 C 2 A 0 z – 1
A 0 2 C 2 A 0 2C 2 A 0 z – 1

Substituting z = esT, on the imaginary axis
jωT
jωT
H id ( e )
H id ( e )
jωT
H ( e ) = ----------------------------------------------------------------------------------------------------- = ------------------------------------------C1
C1
1 – m ( ω ) – jθ ( ω )
1
1 + ------- + ------------------- – j --------------------------------------------------A0 2 C2 A
0 2C 2 A 0 tan ( ωT ⁄ 2 )
Magnitude error
Phase error
C1 
1
m ( ω ) = – ------  1 + -----------
A0 
2 C 2
C1
C1
θ ( ω ) = ------------------------------------------------ ≅ ----------------------2C 2 A 0 tan ( ωT ⁄ 2 ) C 2 A 0 ωT
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For the noninverting integrator
C2
C1
_
+
V0 ( n + 1 )
1
1
C 2 V 0 ( n + 1 )  1 + ------ = C 2 V 0 ( n )  1 + ------ + C 1 V in ( n ) + -----------------------

A 0
A 0
A0
z-transforming and solving
C1
Vo ( z )
H ( z ) = ---------------- = ---------------------------------------------------------------V in ( z )
C1
1

C 2 1 + ------ ( z – 1 ) + ------- z

A0
A 0
Same magnitude and phase error result
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FULLY DIFFERENTIAL CIRCUITS
•Fully differential configurations reduce the clock feedthrough
noise and increase the dynamic range.
•They allow an increase design flexibility
C2
C1
(Φ2)
_
Φ2
Φ1
Φ2
Φ1
(Φ1)
+
Φ2
Simple integrator (inverting and non inverting)
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Immediate sampling (inverting and non inverting) integrator:
Vin
-Vin
Φ1
Φ2
Φ1
Φ2
_
Φ1
-Vin
Vin
+
Φ1
Φ2
Φ1
Φ1
Φ2
Delayed sampling (inverting and non inverting) integrator:
Vin
-Vin
Φ1
Φ2
Φ1
Φ2
_
Φ2
-Vin
Vin
F. Maloberti: Switched Capacitor Filters
+
Φ1
Φ2
Φ1
Φ2
Φ2
67
•It is possible to reduce the op-amp finite bandwidth dependence
by the use of delayed sampling inverting and non inverting
integrators along a second order loop.
Φ1
Φ1
Φ2
Φ2
Φ1
Φ1
Φ2
Φ2
_
+
+
_
Φ2
Φ2
Φ1
Φ2
F. Maloberti: Switched Capacitor Filters
Φ1 Φ1
Φ1
Φ2
68
•The peaking in the frequency response due to the phase error is
strongly reduced
•It is easy to realize bilinear integrators
Vin
C1
C2
Φ1
Φ1
Φ2
Φ2
_
C1
_V
in
Φ2
+
Φ1
Φ1
Φ2
C2
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NOISE IN SC CIRCUITS
The noise sources in a SC network are:
•
Clock feedthrough noise
•
Noise coupled from power supply lines and substrate
•
kT/C noise
• Noise generators of the op-amp
The first two sources are the same as in mixed analog-digital circuits.
kT/C noise:
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Consider the simple network:
vin
S1
In the “on” state the switch can be
modeled with a noisy resitor
C
Noise equivalent circuit:
Ron
S1
C
4kTRon f
The white spectrum of the “on” resistance is shaped by the low pass
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75
action of the RonC filter.
The noise voltage across the capacitor C has spectrum:
4kTR on ∆f
2
2
S n,c = v n, c = 4kTR on H ( f ) ∆f = ---------------------------------------2
1 + ( 2πfR on C )
When the switch is turned “off” the noise voltage vn,c is sampled and
held onto C
S
F. Maloberti: Switched Capacitor Filters
f
76
The folding of the spectrum in band-base gives a white spectrum.
*
v n,c
f CK/2
f
It power (the dashed area) is equal to the integral of Sn,c
2
v n, c
∞
4kTR on ∆f
4kT
∞
kT
= ∫ ----------------------------------------2- df = ----------- ( atan x ) 0 = ------2πC
C
0 1 + ( 2πfR on C )
Procedure for the noise calculation in SC networks:
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