Download Resistor Voltage Coefficient

IC Transistors and Resistors
I.
II.
III.
IV.
Resistors
Bipolar Transistors
MOS
DMOS
Chris Kendrick
Jan. 29, 2003
BiCMOS Design
Resistor Voltage Coefficient
Figure 1 A p type region in an n type tub forms the resistor.
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Resistor Voltage Coefficient
% Change PHV Resistance vs. Body Bias
% Change Resistance
25.00%
30x300
20.00%
12x300
6x300
12x120
15.00%
12x30
10.00%
VApplied = 5V
5.00%
0.00%
0
10
20
30
Body Bias (V)
40
50
Resistor Temperature Coefficient
PHV Resistance vs. Temperature
% Change in Resistance
80.0%
VBody = 5V
60.0%
40.0%
30x300
12x300
20.0%
6x300
0.0%
-100
0
-50
50
-20.0%
-40.0%
Temperature (C)
100
150
200
Resistor Voltage limits
• The maximum resistor voltage is NOT
defined by the tub it’s sitting in!
Diffusion
Breakdown (V)
Buried Layer – Isolation
95
PWell – Epi
95
PHV – Epi
60
NHV - PWell
43
PSD - Epi
30
NSD - PWell
17.5
NSD – PHV
12
NSD – PSD (in PWell)
5.8
• The voltage rating of the tub determines
the spacing of PHV to Epi
Lateral PNP Saturation
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Low current NPN/PNP biasing
• What’s the lowest current bipolars can be biased at?
Lateral PNP
C
B
E
FOX
PSD PHV
PHV
FOX
FOX
PSD Epi
PSD
PHV
NSD
Substrate
PNP (PHV/Epi - Emitter 21x 21
UDR) cross-section
ICmin ~ 5uA
Low current NPN/PNP biasing
• What’s the lowest current bipolars can be biased at?
Vertical PNP
C
B
E
C
FOX
FOX
PWell
PSD
PSD
PHV
NSD
NHV Epi
NSD
PSD
PHV
Substrate
PNPV (PSD/NHV - Emitter 28 x 28
UDR) cross-section
ICmin ~ 20nA
Low current NPN/PNP biasing
• What’s the lowest current bipolars can be biased at?
NPN
E
C
B
FOX
FOX
FOX
PWell
PSD
PHV
NSD
Epi
PSD
PHV
NSD
Substrate
NPN (NSD/PWell - Emitter 21 x 21
UDR) cross-section
ICmin ~ 20nA
MOS Safe Operating Area
• Hot carrier injection limits NMOS operating voltage
S
Poly
D
G
BPSG
FOX
BPSG
FOX
PWell
Epi
NSD
Substrate
Low Voltage NMOS cross-section
4.0E-05
Bulk Current (A)
3.5E-05
3.0E-05
2.5E-05
2.0E-05
1.5E-05
1.0E-05
5.0E-06
0.0E+00
0
1
2
3
Gate Voltage (V)
4
5
6
LV NMOS Hot Carrier Injection
• Maximum Vds determined from HCI measurements 10% degradation in 10 yrs
• Transient Vds rating based on 10% duty cycle
LV LVT NMOS 100x6
Time to 10% IDlin degredation vs. Vds
Time @ 10% Idlin degredation
1.0E+09
1.0E+08
Measured Vds Max (V)
Device
LV NMOS 100x6
LV NMOS 100x16
LV LVT NMOS 100x6
LV LVT NMOS 100x16
Id 10%
1 yr.
5.5
6.8
5.1
6.4
10 yrs -> Vds=4.6V
10 yr.
5.1
6.5
4.6
6.1
1.0E+07
1.0E+06
1.0E+05
0.15
0.16
0.17
0.18
0.19
-1
1/Vds (V )
0.2
0.21
0.22
LV LVT PMOS drain-source leakage
• Drain-source leakage determines maximum Vds at high temperature
• Minimum channel length targeted based on process variation and independent
SEM measurement
LV LVT PMOS Leakage vs. Gate Length (Vds=5V)
L29894, wf #19
1.0E-06
4.5
5.0
5.5
6.0
6.5
7.0
7.5
1.0E-07
Flat_27
Leakage Current (A/um)
1.0E-08
1.0E-09
1.0E-10
Flat_150
Center_150
1.43um
150C
1.70um
Top_27
Top_150
Flat_poly1_27
1.0E-11
1.69um
1.0E-12
1.0E-13
1.0E-14
27C
1.0E-15
Minimum Poly2 CD = 1.57um
1.0E-16
Gate Length (UDR)
DMOS Specific Rdson
Active Area width
Rsp = Rdson x transistor active area
Active Area length
transistor active area = # cells x cell area
Rdson (W)
Area (cm2)
Rsp. (mW.cm2)
LV NLDMOS
0.66
5.19E-4
0.34
MV1 NLDMOS
1.93
7.32E-4
1.41
LV PLDMOS
2.58
5.19E-4
1.34
MV PLDMOS
4.92
7.32E-4
3.6
VDMOS_HEC
1.53
1.77E-3
2.7
Device
Ex : LDMOS transistor
DMOS Specific Rdson
S
G
D
N+ P+ N+
PHV
N+ P+
PHV PW
N+
Sinker
• More components to Rdson
than just channel resistance
RCH + REpi + RBL + RMetal
N-Epi
N-Buried Layer
• Series resistance causes ‘bend’
in ID vs. VG curve
P-substrate
6.0E-02
5.0E-02
IDS (A)
4.0E-02
3.0E-02
2.0E-02
1.0E-02
0.0E+00
0
2
4
6
VGS (V)
8
10
12
A useful way to extract DMOS series resistance
(1)
C W
I   ox (V  V )V 
D
GS T DS
L
(2)
V
DS
DS
G 

M V
(1  R  (V
 V )) 2
GS
S
GS T
V V
I R
DS
DS
D S
I
(3)
 
COX W
L
Device

VGS
Substituting (2) into (3) gives,
ID
 VT VDS  I D RS 
RS 
( I D  GM (VGS  VT ))VDS
I D2
size (cells)
R-series (Ohms)
Total rdson (OHMs)
% series resistance
NLDMOS_13V
5x20
0.37
0.69
54 %
NLDMOS_30V
5x20
NLDMOS_45V
5x20
1.44
1.99
72 %
PLDMOS_13V
5x20
1.25
2.66
47 %
PLDMOS_45V
5x20
2.8
5.0
36 %
VDMOS_HD
15x46
1.63
1.84
89 %
VDMOS_HEC
13x46
DMOS Clamped Inductive Switching
• Clamping the flyback voltage below the DMOS breakdown increases energy
capability.
• Power dissipation eventually allows parasitic bipolar to turn on, killing device
Energy Capability
Device Comparison
300
y = 2.8072x0.6032
Energy (mJ/mm2)
250
80
70
47V VDMOS_HD
150
47V VDMOS_HEC
47V MV2_NLDMOS
100
Power (47V VDMOS_HD)
Vd
1.5
60
Drain Voltage (V)
y = 1.9762x0.6223
200
2.0
Id
Power (47V VDMOS_HEC)
50
50
1.0
40
Power (47V MV2_NLDMOS)
to
30
0.5
20
0
10
0.0
0
0
-10
-4
-5.00x10
0.6421
y = 1.7849x
-2.50x10
-4
0.00
2.50x10
Time (sec.)
-4
5.00x10
-4
-0.5
-4
7.50x10
500
1000
1500
Time (uS)
2000
2500
Energy capability can determine device size
DMOS Rdson vs. Energy Capability
30.0
25.0
160.00
Rdson
Energy Capability
140.00
120.00
Rdson ( W )
20.0
100.00
15.0
80.00
60.00
10.0
40.00
5.0
20.00
0.0
0.0E+00
0.00
2.5E-03
5.0E-03
Area (cm 2)
7.5E-03
1.0E-02