Download Lecture 4 - Auburn Engineering

ELEC 5270/6270 Fall 2007
Low-Power Design of Electronic Circuits
Power Analysis: High-Level
Vishwani D. Agrawal
James J. Danaher Professor
Dept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Fall07/course.html
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 4
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Key Parameters
Power α Capacitance × Activity

Capacitance
Area
 Complexity


Activity
Dynamic behavior
 Operational characteristics

Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 4
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Architecture-Level Power Estimation

Analytical methods
Complexity-based models
 Activity-based models


Empirical methods
Fixed-activity models
 Activity-sensitive models

Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 4
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A Complexity-Based Model
Power =
Σ
GEk (Etyp + CLkVDD2) f Ak
All functional blocks k
where
 GEk =

Etyp

CLk =
f
=
VDD =
Ak
=



=
gate equivalent count for block k, e.g., estimated
number of 2-input NANDs.
average energy consumed per clock cycle by an
active typical 2-input NAND.
average capacitance of a gate in block k.
clock freqency.
supply voltage.
average fraction of gates switching per cycle in
block k.
Ref.: K. Müller-Glaser, K. Kirsch and K. Neusinger, “Estimating Essential
Design Characteristics to Support Project Planning for ASIC Design
Management,” Proc. IEEE Int. Conf. CAD, Nov. 1991, pp. 148-151.
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 4
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Improving Complexity Models
Treat logic, memory, interconnects and
clock tree, separately.
 For example, a memory array may not be
modeled as equivalent NAND gates, but
as memory cells.

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ELEC6270 Fall 07, Lecture 4
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An On-Chip SRAM
Ctrl
Memory
array
2n-k cells
word line
bit line
...
Row decode and drivers
...
Address bus
2k cells
Six-transistor
memory cell
...
Sense and column decode
...
Data
Address bus
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 4
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Power Consumed by SRAM
Power =
Where 2k
cint
lcol
2n-k
ctr
Vswing
2k
── (cint lcol + 2n-k ctr) VDD Vswing f
2
number of cells in a row
wire capacitance per unit length
memory column length
number of cells in a column
minimum size transistor drain capacitance
bitline voltage swing
Ref.: D. Liu and C. Svenson, “Power Consumption Estimation in
CMOS VLSI Chips,” IEEE J. Solid-State Circuits, June 1991,
pp. 663-670.
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 4
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Activity-Based Models




Power α
capacitance × activity
Capacitance α area
Both area and activity can be estimated from the
entropy of a Boolean function.
Definition: Entropy of a system with m states
having probabilities p1, p2, . . . , pm, is
m
H
=
– Σ
pk log2 pk bits
k=1
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 4
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Binary Signals

Entropy of a binary signal:
H(p1) = – p1 log2 p1 – (1– p1) log2(1– p1)

Entropy of an n-bit binary vector:
n
H(X) =
Σ
H(p1k)
k=1
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ELEC6270 Fall 07, Lecture 4
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Entropy and Activity
1.0
4 p1k(1-p1k)
Entropy
0.75
0.50
0.25
0.0
0.0
0.25
0.5
0.75
1.0
p1k
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 4
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Entropy of a Circuit
Y1
X1
X2
.
.
.
Combinational
Logic
Ym
Xn
Copyright Agrawal, 2007
.
.
.
Y2
ELEC6270 Fall 07, Lecture 4
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Input and Output Entropy
Hi
=
2n
– Σ
k=1
pk log2 pk
where pk = probability of kth input vector
Ho
=
2m
– Σ
j=1
pj log2 pj
where pj = probability of jth output vector
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ELEC6270 Fall 07, Lecture 4
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Average Acrivity
Average entropy
≈
2/3
─── (Hi + 2Ho)
n+m
Quadratic decay
Hi
Hi ≥ Ho
PI
Copyright Agrawal, 2007
Circuit depth →
ELEC6270 Fall 07, Lecture 4
Ho
PO
13
Area Estimate


K.-T. Cheng and V. D. Agrawal, “An Entropy Measure for the
Complexity of Multi-Output Boolean Functions,” Proc. 17th DAC,
1990, pp. 302-305.
M. Nemani and F. Najm, “Towards a High-Level Power Estimation
Capability,” IEEE Trans. CAD, vol. 15, no. 6, pp. 588-598, June
1996.
Area
Copyright Agrawal, 2007
=
2n Ho/n
for large n
=
2n Ho
for n ≤ 10
ELEC6270 Fall 07, Lecture 4
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Power
N
Power = K1 × Av. Activity × Σ Ck
k=1
=
K2 × Av. Activity × Area
where Ck is the capacitance of kth node in a circuit with N nodes
Power
2n+1
= K3 ────── Ho (Hi + Ho)
3n(n+m)
Constant K3 is determined by simulation of gate-level circuits.
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ELEC6270 Fall 07, Lecture 4
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Sequential Circuit
PI
PO
Hi
Combinational
Logic
Ho
Flip-flops
Hi and Ho are determined from high-level simulation.
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ELEC6270 Fall 07, Lecture 4
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Empirical Methods

Functional blocks are characterized for
power consumption in active and inactive
(standby) modes by
Analytical methods, or
 Simulation, or
 Measurement


A software simulator determines which
blocks become active and adds their
power consumption.
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 4
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Example: RISC Microprocessor
Clock cycles
add R1← R2+R3
1
2
3
4
5
IF
ID
EX
MEM
WB
mem rfile
pcadd bradd
lw R4 ← 4(R5)
IF
ALU
ID
mem rfile
pcadd bradd
6
. . .
rfile
EX
MEM
WB
ALU
mem
rfile
ALU
Power
profile
Copyright Agrawal, 2007
ALU
mem
mem
ALU
rfile
ALU
rfile
ALU
ELEC6270 Fall 07, Lecture 4
mem
ALU
rfile
rfile
time
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Additional References



P. E. Landman, “A Survey of High-Level Power
Estimation Techniques,” in Low-Power CMOS
Design, A. Chandrakasan and R. Brodersen
(Editors), New York: IEEE Press, 1998.
P. E. Landman and J. M. Rabaey, “ActivitySensitive Architectural Power Analysis,” IEEE
Trans. CAD, vol. 15, no. 6, pp. 571-587, June
1996.
A. Raghunathan, N. K. Jha, and S. Dey, Highlevel power analysis and optimization, Boston:
Springer, 1997.
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ELEC6270 Fall 07, Lecture 4
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