Download Band Gap

SOI Detector
(1) Mateusz Baszczyk, Piotr Dorosz, Sebastian Głąb,
Wojciech Kucewicz, Łukasz Mik, Maria Sapor
(2) Imran Ahmed, Tomasz Fiutowski, Marek Idzik, Jakub Moroń
(3) Piotr Kapusta
(1) Department of Electronics,
(2) Department of Particle Interaction and Detection Techniques
AGH – University of Science and Technology,
Al. Mickiewicza 30, 30-059 Krakow, Poland
(3) Institute of Nuclear Physics Polish Academy of Science
Radzikowskiego 152, 31-342 Krakow, Poland
Agenda
•
•
•
•
•
•
•
Chip topology
Pixel circuit;
Band Gap voltage source;
Analogue to digital converter;
Digital library;
Summary;
Future work.
2
Assumptions
• Detector has to work but it’s parameters are not so
important.
• Pixels with CDS and rolling shutter readout scheme.
• Possibility to measure wafer temperature.
• Functional 10 bit ADC with parallel data output (LVDS).
• We will take part in July submission.
3
Chip layout
• Detector has 32 pix x 32 pix;
• Two slightly different layouts of
pixel;
• Two Band Gaps;
• Two 10 bit SAR ADCs;
• Differential voltage signal.
4
Chip
5
Pixel
6
Designed by Piotr Kapusta
Pixel layout (30 um x 30 um)
Designed by Piotr Kapusta
7
Negative temperature coefficient
Forward voltage of p-n junction VBE has negative TC.
VBE VBE  4  mVT  Eg / q

T
T
3
2
Temperature exponent of mobility:
m
Thermal voltage:
VT 
Bandgap energy of silicon:
E g  1.12eV
kT
q
With VBE = 750 mV, T = 300 K:
VBE
mV
 1.5
T
K
8
Positive temperature coefficient
It was recognized in 1964 that if two bipolar transistors operate at unequal current
densities, then the difference between their base-emitter voltages is directly
proportional to the absolute temperature.
VBE  VT ln n  m
VT
mV
 0.087
T
K
9
Band Gap
10
Band Gap (280 um x 425 um)
11
Band Gap („cold” diode model)
12
Band Gap („hot” diode model)
13
ADC (theory)
+
VIN
-
Bn-1
111
110
101
100
011
010
001
000
Vin
SAR
DAC
VDA
Bn-2
B0
SAR register:
100
110
111
110
Shift register
14
ADC
15
Designed by Marek Idzik and Tomasz Fiutowski
ADC (100 um x 400 um)
16
Designed by Marek Idzik and Tomasz Fiutowski
Sampling circuit with bootstrap
17
Designed by Marek Idzik and Tomasz Fiutowski
Sampling circuit with bootstrap
M. Dessouky, A. Kaiser, Input switch configuration suitable for rail-to-rail operation of switched opamp circuits;
Elect. Lett., vol. 35, no. 1, pp. 8-10, Jan. 1999.
18
Sampling circuit with bootstrap
M. Dessouky, A. Kaiser, Input switch configuration suitable for rail-to-rail operation of switched opamp circuits;
Elect. Lett., vol. 35, no. 1, pp. 8-10, Jan. 1999.
19
Sampling circuit with bootstrap
20
Designed by Marek Idzik and Tomasz Fiutowski
9 bit DAC (segmented)
21
Designed by Marek Idzik and Tomasz Fiutowski
Dynamic comparator
22
Designed by Marek Idzik and Tomasz Fiutowski
Dynamic comparator
23
Designed by Marek Idzik and Tomasz Fiutowski
Delay based on thyristor
24
Designed by Marek Idzik and Tomasz Fiutowski
Delay based on thyristor
25
Designed by Marek Idzik and Tomasz Fiutowski
Digital library
94 Cells (81 completed, 13 missing layout).
Adders, AND, AndOrInvert, Buffer, Buffer with Enable, Tristate Buffer, D Flip-Flops,
D Latches, INV, JK Flip-Flops, Multiplexers, NAND, NOR, OR, T Flip-Flops, XNOR,
26
XOR.
DigitalLib
• Two libraries: Gates and DigitalLib.
Gates contains parameterized symbols and is used to draw
schematics of DigitalLib.
• HDF_DYNAMIC and DF_DYNAMIC were drawn by Tomasz
Fiutowski. These cells have different layout constraints.
MESH is a template for layout drawing.
• These cells do not have layout: D Flip-Flops with Enable,
all JK Flip-Flops, most of T Flip-Flops.
• All cells have passed simulation, DRC and LVS test. But I do not give
any guarantee for correct operation of digital circuit – you must test it
by yourself!!!
27
Conclusions
• We have designed first SOI detector in Lapis technology.
It is starting point for further improvements;
• Simulation results have shown correct operation of ADC
and Band gap voltage source;
• Digital library containing low height cells was made;
(not tested yet)
28
Future work
• IC will be measured immediately after shipment.
It is possible to use SeaBoard as acquisition system.
• We plan to use column ADC to increase readout
speed. Due to large amount of digital data we will
design serializer and phased locked loop.
• We would like to take part in January MPW run.
29
Thank you for your attention
30