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SN54LVC04A, SN74LVC04A HEX INVERTERS SCAS281I – JANUARY 1993 – REVISED OCTOBER 1998 D D D D D D EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Inputs Accept Voltages to 5.5 V Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, and Ceramic Chip Carriers (FK) SN54LVC04A . . . J OR W PACKAGE SN74LVC04A . . . D, DB, OR PW PACKAGE (TOP VIEW) 1A 1Y 2A 2Y 3A 3Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 6A 6Y 5A 5Y 4A 4Y SN54LVC04A . . . FK PACKAGE (TOP VIEW) 1Y 1A NC VCC 6A D 2A NC 2Y NC 3A description 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 6Y NC 5A NC 5Y 3Y GND NC 4Y 4A The SN54LVC04A hex inverter contains six independent inverters designed for 2.7-V to 3.6-V VCC operation and the SN74LVC04A hex inverter contains six independent inverters designed for 1.65-V to 3.6-V VCC operation. 4 The ’LVC04A devices perform the Boolean function Y = A. NC – No internal connection Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. The SN54LVC04A is characterized for operation over the full millitary temperature range from –55°C to 125°C. The SN74LVC04A is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each inverter) INPUT A OUTPUT Y H L L H Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LVC04A, SN74LVC04A HEX INVERTERS SCAS281I – JANUARY 1993 – REVISED OCTOBER 1998 logic symbol† 1A 2A 3A 4A 5A 6A 1 2 1 3 4 5 6 9 8 11 10 13 12 1Y 2Y 3Y 4Y 5Y 6Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, PW, and W packages. logic diagram, each inverter (positive logic) A Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVC04A, SN74LVC04A HEX INVERTERS SCAS281I – JANUARY 1993 – REVISED OCTOBER 1998 recommended operating conditions (see Note 4) SN54LVC04A VCC VIH Supply voltage High-level input voltage Operating Data retention only VIL VI VO IOH IOL Low-level input voltage MAX MIN MAX 2 3.6 1.65 3.6 1.5 1.5 UNIT V 0.65 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V SN74LVC04A MIN V 1.7 2 2 0.35 × VCC VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0.7 0.8 V 0.8 Input voltage 0 5.5 0 5.5 V Output voltage 0 VCC 0 VCC –4 V High level output current High-level Low level output current Low-level VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V –8 –12 –12 –24 –24 VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V mA 4 8 12 12 24 24 mA TA Operating free-air temperature –55 125 –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LVC04A, SN74LVC04A HEX INVERTERS SCAS281I – JANUARY 1993 – REVISED OCTOBER 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 2.7 V to 3.6 V IOH = –4 mA IOH = –8 mA ∆ICC VCC–0.2 1.2 V 1.7 2.7 V 2.2 2.2 3V 2.4 2.4 3V 2.2 2.2 1.65 V to 3.6 V IOL = 100 µA UNIT VCC–0.2 2.3 V IOH = –24 mA II ICC MIN 1.65 V IOH = –12 12 mA VOL SN74LVC04A TYP† MAX MIN 1.65 V to 3.6 V IOH = –100 100 µA VOH SN54LVC04A TYP† MAX VCC 0.2 2.7 V to 3.6 V 0.2 IOL = 4 mA IOL = 8 mA 1.65 V 0.45 2.3 V 0.7 IOL = 12 mA IOL = 24 mA 2.7 V 0.4 0.4 3V 0.55 0.55 VI = 5.5 V or GND VI = VCC or GND, 3.6 V ±5 ±5 µA 3.6 V 10 10 µA 500 500 µA IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V Ci VI = VCC or GND † All typical values are at VCC = 3.3 V, TA = 25°C. 3.3 V 5 5 V pF switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) SN54LVC04A PARAMETER FROM (INPUT) TO (OUTPUT) tpd A Y VCC = 2.7 V MIN VCC = 3.3 V ± 0.3 V MAX MIN MAX 5.5 0.5 4.5 UNIT ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) SN74LVC04A PARAMETER tpd FROM (INPUT) TO (OUTPUT) A VCC = 1.8 V Y VCC = 2.5 V ± 0.2 V TYP MIN MAX 13.5 1 7.5 VCC = 2.7 V MIN VCC = 3.3 V ± 0.3 V UNIT MAX MIN MAX 5.5 1 4.5 ns 1 ns tsk(o)‡ ‡ Skew between any two outputs of the same package switching in the same direction operating characteristics, TA = 25°C TEST CONDITIONS PARAMETER Cpd 4 Power dissipation capacitance per inverter VCC = 1.8 V TYP f = 10 MHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 6 VCC = 2.5 V TYP 7 VCC = 3.3 V TYP 8 UNIT pF SN54LVC04A, SN74LVC04A HEX INVERTERS SCAS281I – JANUARY 1993 – REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.15 V 2 × VCC S1 1 kΩ From Output Under Test Open GND CL = 30 pF (see Note A) 1 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at Open (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 0 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LVC04A, SN74LVC04A HEX INVERTERS SCAS281I – JANUARY 1993 – REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVC04A, SN74LVC04A HEX INVERTERS SCAS281I – JANUARY 1993 – REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open GND 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 2.7 V Output Control (low-level enabling) 1.5 V 1.5 V 0V tPLH tPHL VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) 1.5 V 0V tPZL 2.7 V Output Input 1.5 V 1.5 V tsu Input 1.5 V tPLZ 3V 1.5 V tPZH VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated Product Folder: SN74LVC04A, Hex Inverter Home | Company Info | Employment | TI Global | Contact Us | Site Map • Advanced Search PRODUCT FOLDER | PRODUCT INFO: FEATURES | DESCRIPTION | DATASHEETS | PRICING/AVAILABILITY/PKG | SAMPLES | APPLICATION NOTES | BLOCK DIAGRAMS | RELATED DOCUMENTS | MODELS PRODUCT SUPPORT: TRAINING SN74LVC04A, Hex Inverter DEVICE STATUS: ACTIVE PARAMETER NAME SN54LVC04A SN74LVC04A Voltage Nodes (V) 3.3, 2.7, 2.5, 1.8 3.3, 2.7, 2.5, 1.8 Vcc range (V) 2.0 to 3.6 2.0 to 3.6 Input Level TTL/CMOS TTL/CMOS Output Level LVTTL LVTTL Output Drive (mA) -24/24 -24/24 No. of Gates 6 6 Static Current 0.01 0.01 tpd max (ns) 4.5 4.5 FEATURES ● ● ● ● ● ● ● Back to Top EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Inputs Accept Voltages to 5.5 V Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, and Ceramic Chip Carriers (FK) EPIC is a trademark of Texas Instruments Incorporated. DESCRIPTION Back to Top The SN54LVC04A hex inverter contains six independent inverters designed for 2.7-V to 3.6-V VCC operation and the SN74LVC04A hex inverter contains six independent inverters designed for 1.65-V to 3.6-V VCC operation. The 'LVC04A devices perform the Boolean function Y = A\. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. The SN54LVC04A is characterized for operation over the full millitary temperature range from -55°C to 125°C. The SN74LVC04A is characterized for operation from -40°C to 85°C. TECHNICAL DOCUMENTS To view the following documents, Acrobat Reader 4.0 is required. To download a document to your hard drive, right-click on the link and choose 'Save'. file:///G|/imaging/BITTING/mail_pdf/cpl_rework/cpl_images/sn74lvc04a.html (1 of 3) [13-Mar-2002 4:51:31 PM] Back to Top Product Folder: SN74LVC04A, Hex Inverter Back to Top DATASHEET Full datasheet in Acrobat PDF: sn74lvc04a.pdf (125 KB,Rev.I) (Updated: 10/14/1998) Full datasheet in Zipped PostScript: scas281i.psz (117 KB) Back to Top APPLICATION NOTES View Application Reports for Digital Logic ● Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) (SCBA012A - Updated: 08/01/1997) ● ● ● ● ● ● ● ● ● ● ● ● CMOS Power Consumption and CPD Calculation (Rev. B) (SCAA035B - Updated: 06/01/1997) Evaluation of Nickel/Palladium/Gold-Finished Surface-Mount Integrated Circuits (SZZA026 - Updated: 06/20/2001) Implications of Slow or Floating CMOS Inputs (Rev. C) (SCBA004C - Updated: 02/01/1998) Input and Output Characteristics of Digital Integrated Circuits (SDYA010 - Updated: 10/01/1996) LVC Characterization Information (SCBA011 - Updated: 12/01/1996) Live Insertion (SDYA012 - Updated: 10/01/1996) Low Voltage Logic Families (Rev. A) (SCVAE01A - Updated: 06/01/1998) Low-Voltage Logic (LVC) Designer's Guide (SCBA010 - Updated: 09/01/1996) Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices (SCEA005 - Updated: 12/01/1997) Selecting the Right Texas Instruments Signal Switch (SZZA030 - Updated: 09/07/2001) Texas Instruments Voltage-Level-Translation Devices (SCEA021 - Updated: 02/15/2001) Understanding Advanced Bus-Interface Products Design Guide (SCAA029, 253 KB - Updated: 05/01/1996) Back to Top RELATED DOCUMENTS ● ● ● ● ● ● ● Advanced Bus Interface Logic Selection Guide (SCYT126, 448 KB - Updated: 01/09/2001) Documentation Rules (SAP) And Ordering Information (Rev. B) (SZZU001B, 13 KB - Updated: 05/06/1999) Logic Selection Guide First Half 2002 (Rev. Q) (SDYU001Q, 3368 KB - Updated: 12/17/2001) Low Voltage Solutions (SGYN139, 103 KB - Updated: 04/04/2001) MicroStar Junior BGA Design Summary (SCET004, 167 KB - Updated: 07/28/2000) More Power In Less Space - Technical Article (Rev. A) (SCAU001A, 850 KB - Updated: 03/01/1996) Overview of IEEE Std 91-1984, Explanation of Logic Symbols Training Booklet (Rev. A) (SDYZ001A, 138 KB - Updated: 07/01/1996) Back to Top BLOCK DIAGRAMS Network Security Camera Back to Top SAMPLES ORDERABLE DEVICE PACKAGE PINS TEMP (ºC) STATUS SAMPLES SN74LVC04AD D 14 -40 TO 85 ACTIVE Request Samples SN74LVC04ADBR DB 14 -40 TO 85 ACTIVE Request Samples SN74LVC04ADGVR DGV 14 ACTIVE Request Samples SN74LVC04ADR D 14 -40 TO 85 ACTIVE Request Samples SN74LVC04APWR PW 14 -40 TO 85 ACTIVE Request Samples Back to Top PRICING/AVAILABILITY/PKG ORDERABLE DEVICE PACKAGE PINS TEMP (ºC) STATUS BUDGETARY PRICE US$/UNIT QTY=1000+ SN74LVC04AD D 14 -40 TO 85 ACTIVE 0.18 50 Check stock or order SN74LVC04ADBLE DB 14 -40 TO 85 OBSOLETE SN74LVC04ADBR DB 14 -40 TO 85 ACTIVE 0.18 2000 Check stock or order SN74LVC04ADGVR DGV 14 ACTIVE 0.18 2000 Check stock or order PACK QTY PRICING/AVAILABILITY/PKG file:///G|/imaging/BITTING/mail_pdf/cpl_rework/cpl_images/sn74lvc04a.html (2 of 3) [13-Mar-2002 4:51:31 PM] Product Folder: SN74LVC04A, Hex Inverter SN74LVC04ADR D 14 SN74LVC04ANSR NS 14 SN74LVC04APWLE PW 14 -40 TO 85 OBSOLETE SN74LVC04APWR PW 14 -40 TO 85 ACTIVE -40 TO 85 ACTIVE 0.18 2500 Check stock or order ACTIVE 0.34 2000 Check stock or order 0.18 2000 Check stock or order Back to Top MODELS ● IBIS Model of SN74LVC04A (Rev. A) (SCEM008A, 186 KB - Updated: 11/01/2000) IBIS Model of SN74LVC04A (Rev. A) (SCEM008A, 34 KB, ZIP - Updated: 11/01/2000) Table Data Updated on: 3/5/2002 Products | Applications | Support | TI&ME © Copyright 1995-2002 Texas Instruments Incorporated. All rights reserved. Trademarks | Privacy Policy | Terms of Use file:///G|/imaging/BITTING/mail_pdf/cpl_rework/cpl_images/sn74lvc04a.html (3 of 3) [13-Mar-2002 4:51:31 PM]