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Programmable pulse generator based on programmable logic and direct
digital synthesis
M. Suchenek and T. Starecki
Citation: Rev. Sci. Instrum. 83, 124704 (2012); doi: 10.1063/1.4771921
View online: http://dx.doi.org/10.1063/1.4771921
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Published by the American Institute of Physics.
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REVIEW OF SCIENTIFIC INSTRUMENTS 83, 124704 (2012)
Programmable pulse generator based on programmable logic
and direct digital synthesis
M. Suchenek and T. Starecki
Institute of Electronic Systems, Warsaw University of Technology, Nowowiejska 15/19, 00-665 Warsaw, Poland
(Received 18 October 2012; accepted 27 November 2012; published online 20 December 2012)
The paper presents a new approach of pulse generation which results in both wide range tunability
and high accuracy of the output pulses. The concept is based on the use of programmable logic and
direct digital synthesis. The programmable logic works as a set of programmable counters, while
direct digital synthesis (DDS) as the clock source. Use of DDS as the clock source results in stability
of the output pulses comparable to the stability of crystal oscillators and quasi-continuous tuning of
the output frequency. © 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4771921]
INTRODUCTION
Electric pulse generators are used in many applications.
In many of them, pulse amplitude, repetition frequency,
pulse delay versus trigger signal, etc. must be changed in
a relatively wide range. This is usually obtained with programmable counters, monostable circuits,1, 2 delay lines3, 4 or
diode circuits.5, 6 Depending on the approach such pulse generators have different properties and features.
The simplest approach is based on programmable counters clocked with a fixed frequency. Unfortunately, such a solution has poor tunability, because all time dependencies of
the output pulses are expressed as integer periods of the input
counter signal. If, for example, the fixed frequency is 1 GHz,
the output signal can have maximum frequency of 1 GHz (division by 1), but the next available setting is 0.5 GHz (division
by 2), etc. As a result, such a solution is acceptable only in a
strongly limited application, and is not used in general purpose programmable pulse generators. The main advantage of
the method is high stability of the output pulse period, length
and trigger delay, as the input fixed frequency is usually produced in a crystal-based oscillator circuit.
Continuous or quasi-continuous tunability can be obtained in the pulse generators based on monostable circuits.
Such circuits are usually developed with a capacitor being
charged and discharged with constant currents.2 Length of
the output pulses can be fine-adjusted by appropriate change
of these currents, while range switching can be obtained by
means of changing the capacitance values. The capacitors
must be of high quality, so that their charging and discharging would produce stable and linear output ramp or triangle
signals. The main difficulty of this technique is a need for
high speed circuit for current switching. Such circuits are easier to implement as monolithic integrated circuits rather then
discrete circuits, so the technique is used mainly in commercial measuring instruments.7 Taking into consideration that
the pulses are produced in analog circuits, which are sensitive
to temperature and supply voltage changes, the resulting accuracy and stability are much worse than in the case of crystalreferenced generators.
Another method of pulse generation is based on delay
lines. In such a case resolution and/or range of the frequency,
0034-6748/2012/83(12)/124704/4/$30.00
pulse width, and trigger delay settings are usually strongly
limited, because these parameters depend directly on the time
of propagation thought the delay elements. The highest resolution (tens of picoseconds) can be obtained with the vernier
delay technique, in which resolution is determined by the
difference of propagation delay between two chains of delay elements.3 Total delay depends on propagation time of
a single delay element and number of such elements in the
chains, and is usually in the range of a few to a few hundreds
of nanoseconds. Similar to the previous case, accuracy and
stability are affected by the temperature and supply voltage
changes.
GENERAL CONCEPT OF THE GENERATOR
It was assumed that the pulse generator would have
two outputs. One of them would be the main signal output, where pulses of programmable repetition frequency and
length would be available. The second would be an output of
the trigger pulses.
The approach presented in this paper is a modification
of the programmable counters concept. The main idea in
our solution is to use direct digital synthesis for producing the clock signal, which would be further divided in programmable counters (Fig. 1). Taking into consideration that
modern direct digital synthesis (DDS) circuits can produce
signals with the frequencies above GHz with the resolution
of μHz or even better (e.g., AD99148 ) and their output signal can have stability comparable to crystal-based oscillators,
the main drawback of the basic programmable counters approach can be therefore at least partially eliminated. Partially,
because although with the DDS it is possible to set the input
frequency fIN of the counters, and as a result repetition frequency fOUT of the output pulse to virtually any value in the
range from less than 1 Hz up to several hundreds of MHz,
length of the output pulses is still subjected to the grain resulting from the input clock period TIN = 1/fIN . However, this
problem can be solved by means of circuits responsible for
fine adjustment of the width of the output pulses and fine adjustment of the trigger pulse delay.
83, 124704-1
© 2012 American Institute of Physics
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124704-2
M. Suchenek and T. Starecki
Rev. Sci. Instrum. 83, 124704 (2012)
FIG. 1. Basic idea of proposed pulse generation technique.
CLOCK SIGNAL GENERATION
The signal used as the field programmable gate array
(FPGA) clock was produced in a DDS circuit, which was
used as a high-stability frequency source. In the tested circuit AD98529 was used for this purpose. Its 48-bit frequency
control corresponds to 1 μHz tuning resolution at 300 MHz,
but even 24-bit frequency control word would be sufficient
for the discussed application. The circuit was controlled by
means of serial peripheral interface (SPI), commonly available in microcontrollers. For any given repetition frequency
of the output pulses fOUT , the frequency of the DDS fIN should
be adjusted in such a way that fIN = N ∗ fOUT , where N is
the biggest possible integer number at which DDS operates
correctly.
In the DDS circuits, the output signal is produced as digital samples, which are then sent to a digital-to-analog converter. Hence, spectrum of such a signal contains also some
unwanted harmonics, and a low pass filters are required to
remove them. The DDS circuits are usually dedicated to generation of sine signals. A common technique used in order
to obtain 50% duty square from DDS circuits is synthesis of
two complimentary sine waves, which are then applied to a
comparator (Fig. 2).
In the tested circuit, sine-to-square wave conversion was
obtained with 5th order Chebyshev LC filters and the internal AD9852 comparator, but in some applications even higher
filter orders may be required.10 It should be also noticed that
theoretically DDS can be used for producing sine waves up to
the Nyquist frequency, but in practical applications, in order
to preserve reasonable level of spectral purity of the output
sine wave signal and possibly low jitter, the upper limit of the
output frequencies should be set to not more than 25% and
the filter corner frequency should not exceed 40% of the DDS
reference clock frequency.11, 12
Prototype of programmable pulse generator based on
programmable logic and direct digital synthesis is presented
on Fig. 3.
FIG. 2. Block diagram of the fIN clock signal generator.
FIG. 3. Prototype of the programmable pulse generator.
PROGRAMMABLE COUNTERS
In the presented generator concept, programmable counters are used to control the period and duty factor of the output
pulses, as well as the trigger delay. The counters can be implemented as shown in Fig. 4.
All the counters shown in Fig. 4 work with synchronous
reset. Control (reload) values used by the counters are held
in the associated registers writable by a microcontroller via a
parallel interface (omitted in Fig. 4 for the purpose of clarity).
Period of the output pulses depends on the control value of
the period counter. Overflow of this counter results in setting
the flip-flop output to high logical level and also clears all the
counters. As already mentioned, fIN frequency is set to such
a value that output pulse period consists of integer number of
the DDS signal periods, hence no additional adjustment of the
output pulse period is required. Pulse length counter is used
for setting length of the output pulse (duty factor). When the
programmed number of fIN signal periods elapses, output of
the pulse length counter changes its state to high, thus clearing
the output flip-flop. As a result, resolution of the output pulse
length is limited to integer number of the fIN signal periods.
This in not acceptable in most of applications, hence width
FIG. 4. Block diagram of programmable counters.
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124704-3
M. Suchenek and T. Starecki
Rev. Sci. Instrum. 83, 124704 (2012)
FIG. 5. Adjustment of the pulse width based on the use of a delay circuit.
of the pulses output from the FPGA must be fine-adjusted to
the required values in additional (external) signal processing
stage. The last counter acts as a trigger delay controller, which
produces a pulse that ends after reaching the preprogrammed
value. It was assumed that width of the trigger pulse is not
critical and falling edge of the trigger signal would be used
as the time marker. Similar as with the output pulse length,
the presented circuit allows the trigger pulse delay to be set
to integer number of fIN signal periods. As this may be not
sufficient in many applications, delay of the trigger signal is
also fine-adjusted in an external circuit.
The counters can be implemented in FPGA or complex
programmable logic device (CPLD) structures. Such circuits
provide fast and very flexible logic at relatively low cost.
Some FPGA devices have internal phase-locked loops (PLLs)
which can be used for multiplication of the input clock signal,
thus substantially extending the frequency range of the output
signals. This is a very convenient feature, as with multiplication factors of 10–20 the DDS can work at tens instead of
hundreds of megahertz. The frequency locking range of such
PLLs can be easily determined with widely available simulation tools (e.g., Altera Quartus II). At low output frequencies
the PLLs can be bypassed, so that the programmable counters
can be fed with the signal taken directly from the DDS. In
the tested circuit, a low cost EP2C5–Cyclone II family FPGA
device from Altera was used.
OUTPUT PULSE WIDTH AND TRIGGER DELAY FINE
ADJUSTMENT
As already mentioned, width of the output pulse and delay of the trigger pulse produced in the FPGA needed additional, fine adjustments. At first it may seem as this would
require two different circuits, but the pulse width correction
can be easily implemented in a very simple circuit with a programmable delay (Fig. 5). Taking into consideration that performed in the FPGA rough adjustment of the pulse width and
trigger delay is done with the resolution of a single FPGA
clock period, range of the programmable delay circuits must
cover at least one such a period. If the PLL inside FPGA is
used, the period is equal TIN /M, where M is the PLL multiplication factor. However, it must be taken into account, that if
M is changed for different settings of the generator, the lowest
value of M must be used in calculations of the required delay
FIG. 6. Simulation of the programmable counters block with the reload values: period counter = 4, length counter = 2, trigger delay = 1.
FIG. 7. Real signals observed at the outputs of the programmable counters
working with the internal FPGA clock frequency of 20 MHz.
range. It should be also remembered, that fIN should be always
adjusted in such a way, that M ∗ fIN is an integer multiple of
the output pulse. This results in changes of the FPGA clock
within the range from TIN_MIN /M to (2 * TIN_MIN )/M, which finally means that range of the programmable delay must be at
least 2/(fIN_MAX ∗ M).
Programmable delays can be implemented in many ways.
The simplest approach is use of a programmable semiconductor delay line, e.g., NB6L295 (ON Semiconductor) or
DS1023 (Dallas Semiconductor), but in the tested circuit a
solution with changing of a threshold point on a ramp signal
was used.13
SIMULATIONS AND MEASUREMENTS
Before programming the FPGA, operation of the programmable counters block was analyzed in a simulator. The
simulations were performed with Altera Quartus II software
(Fig. 6). Real signals, obtained from the hardware were in
very good agreement with the simulation results (Figs. 7
FIG. 8. Real signals observed at the outputs of the programmable counters
working with the internal FPGA clock frequency of 600 MHz.
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124704-4
M. Suchenek and T. Starecki
and 8). Although the output signals observed at the internal
FPGA clock frequency of 600 MHz are distorted, they are
still in good accordance with the required time relationships.
The distortions result in part from the limited bandwidth of
the oscilloscope (observations were performed with Hewlett
Packard Infinium oscilloscope, with −3 dB bandwidth at 500
MHz and recording speed of 1 GSa/s), but mainly from the
very high frequency of operation–according to the simulations, maximum frequency of operation of the programmable
counters block should be 417 MHz, while in fact the circuit
was working up to 620 MHz. In addition to the examples
given below, the hardware was tested at many different settings, proving correct operation of the described solution.
CONCLUSIONS
In the paper we have described a new approach to the
pulse generation, based on the use of programmable logic and
direct digital synthesis. The hardware assembled for the purpose of testing of the presented solution has characteristics
comparable (or even better) to many commercial instruments,
while its implementation is substantially simpler, thus leading
to considerably lower costs. The performed tests proved that
the solution is featured with wide range of output frequencies
(from fraction of a hertz to hundreds of megahertz), quasi-
Rev. Sci. Instrum. 83, 124704 (2012)
continuous tuning, and high accuracy of the output pulse timing. Another advantage of the presented concept is stability
of the output pulses comparable to the stability of a crystal
oscillator.
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