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DIVISION OF CIRCUITS AND SYSTEMS
NANYANG TECHNOLOGICAL UNIVERSITY
SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING
DIVISION OF
CIRCUITS AND
SYSTEMS
Contents
21
DIVISION OF CIRCUITS AND SYSTEMS
NANYANG TECHNOLOGICAL UNIVERSITY
SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING
INTRODUCTION
The year 2009 is another fruitful year for the
division. It begins with the exciting news of a
research breakthrough by a team of researchers in
the division and Rice University. The project was led
by Professor Krishna Palem, Kenneth and Audrey
Kennedy Professor of Computing at the Department
of Computer Science at the George Brown School
of Engineering at Rice University and Professor Yeo
Kiat Seng, Head of Division of Circuits and Systems
and Interim Director of the new Integrated Circuit
Design Centre of Excellence at NTU, with team
members Associate Professor Goh Wang Ling and
Visiting Assistant Professor Kong Zhi Hui. They have
successfully developed a new super environmentallyfriendly green chip which uses thirty times less energy
while running seven times faster than existing chips.
The year also ends with the establishment of a S$50
million new Integrated Circuit Design Centre of
Excellence jointly funded by EDB and NTU. This new
centre will provide an excellent learning and research
environment to train more than 100 integrated
circuit (IC) designers and researchers to propel the
knowledge based sector in Singapore.
transmit digital temporal difference images wirelessly
to a receiver with high rates and reduced power
consumption. The sensor wakes up when it detects
enough scene changes and only communicates
meaningful frames. Hence, the power consumptions
for the sensor and the radio transmission are 0.9 mW
and 15 mW, respectively.
Image sensor chip testing platform
To scale greater heights in IC research, the division
has been actively looking for talented young
researchers worldwide to join the division. Dr Zheng
Yuanjin, a group leader in RFIC from the Institute
of Microelectronics; Dr Chen Shoushun, a post-doc
working in biosensor IC from Yale University; Dr Yu
Hao, a senior research staff specializing in VLSI from
Berkeley Design Automation; and Dr Tony Tae Hyoung
Kim, a post-doc working in low-power memory
circuit design from University of Minnesota, have
joined the division as Assistant Professors. They add
both depth and diversity in IC research activities in
the division and help to position NTU to become one
of the leading universities in the world for IC design
research.
Chip microphotograph
Fig. 1 Low power wireless motion sensor
The division has also done very well in bringing
in external research grants. One of them worthy
of mentioning is the research project, “New grid
array antennas and their integration method for an
innovative solution to 60-GHz radio devices”, led
by Professor Zhang Yue Ping who secured close to
$250,000 from the National Research Foundation
(NRF) under the highly competitive Proof of Concept
(POC) Grant Call. This project aims to demonstrate
new grid array antennas and their integration method
for an innovative solution of millimeter-wave radio
One of the new faculties, Dr Chen, has successfully
tested and characterized a low power wireless motion
sensor. The sensor features a 64 by 64 pixel array
and can report standard analog intensity images. An
ultra-wide-band (UWB) radio channel allows it to
Contents
Sample motion images
22
DIVISION OF CIRCUITS AND SYSTEMS
NANYANG TECHNOLOGICAL UNIVERSITY
SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING
devices based on locally-accessible low temperature
co-fired ceramic (LTCC) technology for emerging
low-power high-speed wireless personal area network
applications in the unlicensed millimeter-wave 60-GHz
band.
As part of the on-going effort to promote the
exchanges of research ideas in IC design, an
international symposium on integrated circuits (ISIC2009) was jointly organized by the division and IEEE
Singapore Section. The conference was supported
by the IEEE Solid-State Circuits Society Singapore
Chapter, Singapore Exhibition & Convention Bureau
and M.I.D.A.S. The symposium has received more
200 papers. The accepted papers are presented
in 14 Special Sessions, 16 Regular Oral Sessions,
and 2 Poster Sessions. The Symposium invites
two distinguished experts to deliver the keynotes
- Dr. Bram Nauta from the University of Twente,
the Netherlands and Mr. Frank P. Averdung, Chief
Executive Officer, SUSS MicroTec AG, Germany. Dr.
Bram Nauta and Mr. Frank P. Averdung will speak
on Analog and RF Circuits in Nanometer CMOS and
More than Moore - The Challenges of 3-Dimensional
IC Integration, respectively. In addition, one tutorial
on IC Design of Power Management Circuits is to
be conducted by Professor Ki Wing-Hung from the
Department of Electronic & Computer Engineering,
The Hong Kong University of Science and Technology.
Another project, “Batteryless Flexible Transceiver
for Biomedical Applications” led by Professor Boon
Chirn Chye, has secured $765,000 from MOE under
the competitive AcRF Tier 2 Grant Call. The project
aims to achieve our vision of the future wireless
communications, all RF transceiver application devices
(hand-phones, wireless identity card/cash cards, etc.)
and wireless biomedical sensors are ultra-miniature
and wearable-like accessories. In addition, they must
have low heat dissipation and low interference to
the extent that they could be used for biomedical
applications without causing any hazard.
Fig. 2 Applications of battery-free flexible transceiver
Contents
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DIVISION OF CIRCUITS AND SYSTEMS
NANYANG TECHNOLOGICAL UNIVERSITY
SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING
Power Aware Mixed-signal
System (PAMS) Programme
Power Management
System
Digital/Analog
Output Interface
Digital-to-Analog
Converter
Digital-to-Analog
Converter
Analog Signal
Processing
Input Interface
Low Power
Digital Processor
Fig. 3: Generic block diagram of PAMS
The programme aims to draw different expertise
of the members in the analog/mixed-signal IC
design group that makes advances in the design
of power aware mixed-signal system (PAMS).
With the emerging of advanced CMOS process
Contents
and technology together with traditional or new
applications in integrated circuits for use in consumer,
nanotechnology, biomedical, environmental and
health care, the PAMS becomes an important
programme platform that supports the urgent needs
and design challenges.
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DIVISION OF CIRCUITS AND SYSTEMS
NANYANG TECHNOLOGICAL UNIVERSITY
SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING
Input Interface – A/P Chan Pak Kwong
(Group Representative)
Analog and Digital Signal Processing
– Asst/P Zheng Yuanjin
The design challenge of an input interface is to ensure
sufficient quality of input signal amplification under
low power design. For a sensor interface example, the
objectives are to translate the minute sensing signal
to an electrical form, amplify the signal with sufficient
sensitivity with respect to noise and offsets, consume
low power whilst preserving adequate dynamic range.
One design example is the Electrical Capacitance
Tomography (ECT) Imaging Transducer IC. Besides low
power consumption, the precision design technique
offers sub-fF detection in tolerant to wiring parasitic
capacitances up to 150pF.
In this programme, the objective is to develop a system
on chip (SoC) or system in package (SiP) device for
wearable Wireless Body Area Networks (WBANs) for
biosensing applications. The device integrates analog
and digital building blocks to build a self-functional
low power integrated circuit platform. In this work, a
digital PHY baseband transceiver IC is proposed and
implemented as a core module to enable a WBAN
radio. The proposed transceiver is targeted at low data
rate, ultra low power to sustain long battery life (2-3
years). Implemented in a 0.18-µm CMOS technology,
the baseband chip consumes 240.24 µW for TX mode
and 202.34 µW for RX mode when working at a 250
kHz system clock and 1.8V supply.
Data Converters – A/P Siek Liter
Data Converters as in Analog-to-Digital converters
and Digital-to-Analog Converters are found before
and after the digital signal processing block.
One example of such a converter is the Dynamic
Reference ADC. It consists of the same number of
comparators as the number of output bits and each
of the comparator’s voltage reference is dynamically
controlled by its preceding bit stage in accordance
with the input signal magnitude, as this converter
computes in a serial manner. As such the Dynamic
Reference ADC can be easily synchronized with
its adjacent blocks using the timing clock of the
peripheral blocks adjacent to it.
Fig. 4:
ECT imaging transducer
Fig. 5:
WBAN digital PHY ASIC
Fig. 7:
Synchronous and
asynchronous DALUs
Fig. 6:
10-bit dynamic reference ADC
Contents
25
Fig. 8
Power management IC
DIVISION OF CIRCUITS AND SYSTEMS
NANYANG TECHNOLOGICAL UNIVERSITY
SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING
Low Power Digital Processor
– A/P Joseph Chang and
A/P Gwee Bah Hwee
Power Management System
– Asst/P Tan Meng Tong and
Asst/P Zheng Yuanjin
This project is part of the NTU - Linköping University
research collaboration on advanced Asynchronous
Logic Circuit Design. The IC chip was fabricated using
the IBM 130 nm CMOS process comprising regular-Vt
and low-power-Vt standard library cells. A comparison
of the performance of the two Data Arithmetic Logic
Units (DALUs) for 24-bit 56002 DSP shows that
the power dissipation of the asynchronous design
is superior (> 40% improvement) and the speed
comparable or less than the former, depending on the
algorithm.
The power management system provides regulated
voltage to each of the sub-systems in the mixed-signal
SOC system. To reduce the power consumption in
power management system (PMS), the supply voltage
of the digital processor will be made adjustable by a
programmable digital DC-DC converter. The voltage
will be adjusted according to the computation
requirement of the digital processor. For example,
when the digital processor is in the idle state, the
supply voltage will be reduced to near subthreshold
level. Otherwise, the supply voltage will be increased
to the nominal level for computationally intensive
operation.
Contents
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DIVISION OF CIRCUITS AND SYSTEMS
NANYANG TECHNOLOGICAL UNIVERSITY
SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING
RF Integrated Circuits and
Systems Programme
A Wideband Low-Power Low-Noise
Amplifier in CMOS Technology
The research activities of the RF Integrated Circuits
and Systems Programme cover the following
topics: Ultra Low Power Low Voltage RFIC Design;
RF Frequency Synthesis, Modelling of Nano-meter
Devices, Interconnects and Coupling of RFICs;
EMC/EMI for RFICs; Packaging for RFICs, Antenna
in Package and Antenna on Chip; RFIC Testing, and
EDA Tools for RFIC. Most projects explore novel
designs and analysis of devices, circuits, sub-systems
and RF SoC (System on Chip) products. The main
focuses are design challenges in high frequency,
broad-band, low power performance, and flexibility
& reconfigurability of the RF circuits and systems. The
ultimate achievement will be the flexible RF front-ends
and ultra low power circuits and systems which can
be powered by alternative energy harvesting storage
devices such as kinetic, electromagnetic and solar cells
for certain biomedical applications. With the push
for green electronics, research in energy harvesting
storage devices and circuits is expected to become
an important activity of the Programme. Some of the
latest projects and significant achievements in 2009
are described under this programme as follows.
Contents
Fig. 9: Die micrograph of the wideband LNA
A T-coil network can be implemented as a high order
filter for bandwidth extension. This technique is
incorporated into the design of the input matching
and output peaking networks of a low-noise amplifier.
The intrinsic capacitances from the transistors are
employed as part of the wideband structure to
extend the bandwidth. Using the proposed topology,
a wideband low-noise amplifier with a bandwidth
of 3-8 GHz, a maximum gain of 16.4 dB and noise
figure of 2.9 dB (min) is achieved. The total power
consumption of the wideband low-noise amplifier
from a 1.8 V power supply is 3.9 mW. The prototype
is fabricated in 0.18 µm CMOS technology. This work
will be published in IEEE TCAS-I on April. 2010.
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DIVISION OF CIRCUITS AND SYSTEMS
NANYANG TECHNOLOGICAL UNIVERSITY
SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING
Energy Aware RF Receiver
Front-End for Low-Power 2.4-GHz
Applications
of received signal strength and uses the optimum
power to receive the signal in a given situation. This
work presents the implementation of an energyaware RX front end for low power, low data-rate
applications. We propose to dynamically control the
power consumption of an RX front end based on the
real-time required noise figure (NF). In order to limit
the scope of our work, we will design around the IEEE
802.15.4 standard which operates in the 2.4-GHz
Industrial, Scientific and Medical (ISM) band. We focus
on the design of the RX front end which generally
consumes a large portion of the total RX power.
The standard features relaxed requirements in terms
of interference rejection, and noise performance
which simplifies front end design and will allow us to
implement dynamic power control circuitry. A receiver
front end designed in 0.18-µm CMOS consisting of an
LNA and IQ mixers has been designed. The front end’s
power consumption is controllable from 5.0 mA down
to 1.4 mA. It is proposed to control the front end’s
power consumption based on the real-time required
noise performance. We show that under typical
channel conditions, this front end can save up to 40%
of its nominal power consumption. Figure 10 shows
the micrograph of the fabricated design implemented
in a 0.18 µm CMOS process.
In the interests of longer battery life, ultra-low
power design has recently become a topic of intense
interest for applications such as wireless personal area
networks (WPAN), and wireless sensor nodes. The IEEE
802.15.4 standard has been specifically designed to
cater to such applications. Transceivers which follow
this standard have been designed to operate using
less than 10 mA of DC current. These designs have
relied on simplified circuit configurations to minimize
power consumption. Despite their relative successes,
we believe that significantly more power consumption
can be saved both by further simplifying the circuit
structures, and dynamically adjusting the performance
of the receiver (RX). The latter method is termed
energy-aware design.
While a radio is designed around its sensitivity,
it normally operates under significantly better
conditions. The average path loss varies depending
on the environment, availability of line of sight (LOS)
and distance between the RX and transmitter (TX),
among other things. An energy-aware transceiver
adjusts its performance according to the amount
Fig. 10: Micrograph of a CMOS energy-aware receiver
Contents
28
DIVISION OF CIRCUITS AND SYSTEMS
NANYANG TECHNOLOGICAL UNIVERSITY
SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING
VLSI Design Programme
The research projects in VLSI Design group cover a
broad spectrum of emerging and multi-disciplinary
topics from low power and fault tolerance arithmetic
circuits, subthreshold and current mode circuits
for artificial neural network, biologically inspired
imaging system, multi-voltage multi-frequency high
level synthesis, memetic computing with evolvable
hardware systems, dynamic energy and reliability
management for multi-processor system-on-chip
(SoC) architectures, 3D Network-on-Chip (NoC),
design methodologies of low-complexity fixed and
reconfigurable FIR filters, publicly authenticable
watermarking for VLSI intellectual property protection
to interconnect reliability analysis. The following
research projects are highlighted in this report.
the power supply and heat removal problems
are challenged. Collaboration with Intel circuit
lab at Oregon USA showed that TSVs are critical
components for power and temperature integrity.
With a compact and parametric physical model to
abstract the complicated 3D system, a TSV design tool
was developed to optimize the power and thermal
integrity simultaneously. At the system-level, a realtime adaptive many-core system configuration and
task distribution methodology is being developed
to optimally distribute the computation and
communication tasks onto the 3D many-cores under
the bandwidth, temperature and power constraints.
At the application-level, a currency discovering
algorithm under the frame-work of synchronous data
flow graph will be developed to optimally map the
stream multimedia application into a task set with the
maximum utilization of parallelism.
Three-dimensional Many-core
Integrated System
New multimedia applications such as surgical
simulation, visual reality visualization, city security
surveillance require real-time processing of a largevolume of data. The new requirements for the
design of high-performance VLSI systems, with
heterogeneous functionary component, concurrent
data processing and self-adaptive configuration, are
beyond the scope of the conventional 2D integration
due to the interconnect limitation. 3D integration
reduces the system size dramatically by vertically
connecting multiple device layers by either wirebonding or through-silicon via (TSV). The use of
‘device-stacking’ allows heterogeneous components
fabricated from imager process, MEMS process,
RF process, and logic process to be independently
optimized and integrated together with a low
fabrication-cost yet a high yield-rate. As there is a
significant boost in the communication bandwidth,
the 3D integration is suited for I/O-centric system
with the concurrent real-time data processing. At the
physical-level, as the many-core system consumes
more power with more integrated components,
Contents
(a)
Fig. 11 (a) A physicallevel view of 3D system
with through-silicon via
(TSV) for both power
supply and heat-removal
(b)
29
(b) A system-level view
of 3D system with manycores, NoC bus and
memory
DIVISION OF CIRCUITS AND SYSTEMS
NANYANG TECHNOLOGICAL UNIVERSITY
SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING
Dynamic Energy/Reliability
Management for Multi-Processor
System-on-Chip (MPSoC)
Statistical Modeling of
Electromigration Failures
In device reliability study, as there can be multiple
failure modes in today ultra-large scale integration, it
becomes imperative to identify the failure units with
different failures before failure analysis in order to
save time and also have an accurate assessment of
reliability. A novel approach to statistical modeling of
electromigration failure based on mixture distribution
probability density function has been formulated,
with the statistical observation confirmed by physical
analysis using high-resolution electron microscope.
Application-specific multi-core architectures with
8/16/32 or more homogeneous/ heterogeneous CPU
cores integrated on a single chip are the dominant
trend for advanced processor architectures. From
the technology integration perspective, it is relatively
well understood how to build VLSI devices consisting
of so many diverse building blocks. However, a key
challenge for the feasibility of today and future many
core Multi-Procoessor System-on-Chip (MPSoC)
architectures is power dissipation density and energy
consumption, which directly affects the robustness
and reliability of the device operation. The VLSI
research group has recently started a joint PhD
research program with Technological University of
Munich. The goal of this research is to investigate
strategies and techniques to dynamically manage
processor energy consumption in dependency to
workload and environmental operating conditions.
In general, processor resources are dimensioned
for worst case workload requirements. However,
worst case workload conditions typically apply only
temporarily, not in sustained, long-term fashion.
Hence, during normal or relaxed workload situations,
processing resources can either be switched off or put
into hot/cold stand-by in order to consume little or no
energy. Existing techniques for energy management
used in high-end mainframe computers will be
effectively scaled down to chip-level multi-processors
to optimize the trade-off between processing
performance, power dissipation and device reliability.
Fig. 12 Mixture distribution probability density function
Fig. 13 Physical analysis using high-resolution scanning
electron microscope to confirm the statistical observation.
Contents
30
DIVISION OF CIRCUITS AND SYSTEMS
NANYANG TECHNOLOGICAL UNIVERSITY
SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING
STAFF MEMBERS
Boon Chirn Chye
Assistant Professor
Alper Cabuk
Teaching Fellow
Chan Pak Kwong
Associate Professor
Chang Chip Hong
Associate Professor
Chen Shoushun
Assistant Professor
Do Manh Anh
Professor
Goh Wang Ling
Associate Professor
Gwee Bah Hwee
Associate Professor
Ho Duan Juat
Associate Professor
Jong Ching Chuen
Associate Professor
Kim Tae Hyoung
Assistant Professor
Kong Zhi Hui
Visiting Assistant
Professor
Yvonne Lam Ying Hung
Associate Professor
Head of Division
Yeo Kiat Seng
Professor
Contents
31
DIVISION OF CIRCUITS AND SYSTEMS
NANYANG TECHNOLOGICAL UNIVERSITY
SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING
STAFF MEMBERS
Lau Kim Teen
Associate Professor
Lim Meng Hiot
Associate Professor
Ng Lian Soon
Associate Professor
Ong Keng Sian, Vincent
Senior Teaching Fellow
See Kye Yak
Associate Professor
Shi Xiaomeng
Visiting Assistant
Professor
Siek Liter @ Hsueh Liter
Associate Professor
Tan Cher Ming
Associate Professor
Tan Meng Tong
Assistant Professor
Yu Hao
Assistant Professor
Yu Yajun
Assistant Professor
Zheng Yuanjin
Assistant Professor
Zhang Yue Ping
Associate Professor
Picture not available
Chang, Joseph Sylvester
Associate Professor
Contents
32
DIVISION OF CIRCUITS AND SYSTEMS
NANYANG TECHNOLOGICAL UNIVERSITY
SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING
Research InterestS
Boon Chirn Chye
Assistant Professor
[email protected]
RFIC devices, Circuits and systems design, RFIC biomedical consumer
electronic.
Alper Cabuk
Teaching Fellow
[email protected]
RF IC design, High frequency clock & data recovery circuits, SONET systems
Chan Pak Kwong
Associate Professor
[email protected]
Sensor circuits and systems, Analog/mixed-signal IC design,
Power management IC
Chang Chip Hong
Associate Professor
[email protected]
VLSI design, Digital filter design, Computer arithmetic, IP watermarking,
Brain-inspired computing.
Chang, Joseph
Sylvester
Associate Professor
[email protected]
Acoustics, Audiology, Electronics, IC design, Analogue and digital signal
processing, Biomedical engineering, Pyschophysics.
Chen Shoushun
Assistant Professor
[email protected]
Mixed-signal smart vision sensors, Feature extracting biomimetic sensors
for sensor networks, Energy-efficient algorithms for object recognition.
Do Manh Anh
Professor
[email protected]
R.F. circuits and systems, Mixed-signal IC design, Acoustics,
Intelligent transport systems.
Goh Wang Ling
Associate Professor
[email protected]
Device processing, Device characterization and Low-power digital IC
design.
Gwee Bah Hwee
Associate Professor
[email protected]
Asynchronous & digital Class-D amplifier IC designs,
Acoustic noise reduction.
Ho Duan Juat
Associate Professor
[email protected]
Video coding, System level digital design, ASIC design.
Jong Ching Chuen
Associate Professor
[email protected]
High-level synthesis, Parallel computation, Reconfigurable systems,
Arithmetic circuits.
Kim Tae Hyoung
Assistant Professor
[email protected]
Low power, High performance digital, Mixed-mode memory circuit design,
Ultra-low voltage sub-threshold circuit design for Energy efficient systems,
Variation & aging tolerant circuits & systems Circuit techniques for 3D ICs.
Kong Zhi Hui
Visiting Assistant
Professor
[email protected]
Design of memory circuits & systems, Low-voltage low-power VLSI
subsystem design, Probabilistic CMOS design.
Lam Ying Hung, Yvonne
Associate Professor
[email protected]
Mixed-signal IC design, Analogue design automation.
Lau Kim Teen
Associate Professor
[email protected]
Low power IC design, Self-timed CMOS circuits, Subthreshold CMOS
circuits.
Lim Meng Hiot
Associate Professor
[email protected]
Computational intelligence embedded systems, AI in finance, Fuzzy/neural
hardware, Combinatorial optimization.
Ng Lian Soon
Associate Professor
[email protected]
Analogue CMOS circuits, DAC/ADC, Micropower circuits,
Analogue bipolar circuits.
Ong Keng Sian, Vincent
Senior Teaching Fellow
[email protected]
Materials and device characterization, Analysis and modeling; Electron
beam techniques; EBIC metrology.
See Kye Yak
Associate Professor
[email protected]
Electromagnetic compatibility, Signal integrity and IC electromagnetic
immunity.
Shi Xiaomeng
Visiting Assistant
Professor
[email protected]
RF device modeling and IC packaging.
Siek Liter @ Hsueh Liter
Associate Professor
[email protected]
Low-power low-voltage analog/mixed signal CMOS/bipolar IC design.
Contents
33
DIVISION OF CIRCUITS AND SYSTEMS
NANYANG TECHNOLOGICAL UNIVERSITY
SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING
Research InterestS
Tan Cher Ming
Associate Professor
[email protected]
Materials and devices reliability physics, Reliability statistics, Nanomaterials, Nano-biology, Equipment maintainability.
Tan Meng Tong
Assistant Professor
[email protected]
VLSI design, Class D amplifiers, Analog and digital signal processing,
Biomedical engineering.
Yeo Kiat Seng
Professor
[email protected]
Device modeling, RFIC design, Low-voltage low-power IC design.
Yu Hao
Assistant Professor
[email protected]
RF IC design and analysis, Low-power and robust 3D system design,
Computer-aided design.
Yu Yajun
Assistant Professor
[email protected]
VLSI digital signal processing, VLSI circuits and systems design.
Zhang Yue Ping
Associate Professor
[email protected]
Wireless chip area network, Single-chip radio and Radio bioelectronics.
Zheng Yuanjin
Assistant Professor
[email protected]
Wideband high frequency RFIC and SoC design, UWB system and circuits,
Bio-IC system and circuits, Adaptive signal and image processing algorithm
and ASIC.
phd and MEng DEGREES Awarded in 2009
PhD – Circuits & Systems
Project Title
Student
Supervisor/Co-supervisor
An Intelligent ISFET Sensory System for Water Quality Monitoring
Chen Deyu
Chan Pak Kwong
A Study of Inter-chip Wireless Interconnect System
Chen Zhiming
Zhang Yue Ping
Efficient Sigma-delta Beamforming Techniques for Ultrasound Imaging
Application
Cheong Jia Hao
Lam Ying Hung Yvonne
Constraint-based Watermarking Techniques for VLSI Intellectual Property
Protection
Cui Aijiao
Chang Chip Hong
In-circuit RF Impedance Measurement for EMI filter Design in Switched Mode
Power Supplies
Deng Junhong
See Kye Yak
Design Methodologies for Low-power Asynchronous - Logic Digital Systems
Law Chong Fatt
Chang, Joseph Sylvester
Gwee Bah Hwee
Realistic Modeling of Electromigration in today ULSI Interconnections
Li Wei
Tan Cher Ming
Low-voltage Low-power Cmos Flip-flops
Phyu Myint Wai
Goh Wang Ling
Speech Enhancement Methods based on Perceptual Wavelet Filterbank
Shao Yu
Chang Chip Hong
Contents
34
DIVISION OF CIRCUITS AND SYSTEMS
NANYANG TECHNOLOGICAL UNIVERSITY
SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING
phd and MEng DEGREES Awarded in 2009
MEng – Circuits & Systems
Project Title
Student
Supervisor/Co-supervisor
Feasibility Study of Porous Aluminum for Electromagnetic Shielding Applications
Ling Yong
See Kye Yak
Design of Delta-sigma Modulator for Ultrasound Imaging
Song Pengyu
Lam Ying Hung Yvonne
Interface Characterization of Wafer Bonding
Sun Lina
Tan Cher Ming
Modeling of and Acoustic Feedback Cancellation in Hearing Instruments
Yang Jingbo
Chang, Joseph Sylvester
Design of Low-power High Speed Error-tolerant Adder and its Application in
Digital Signal Processing
Zhang Weijia
Goh Wang Ling
Selected Publications in 2009
1.
A. Meaamar, C. C. Boon, K. S. Yeo and M. A. Do, “A Wideband Low-noise Amplifier in CMOS Technology,” IEEE Transactions on Circuits and Systems,
Part I, vol. 57, no. 4, April. 2010.
2.
A. V. Do, C. C. Boon, M. A. Do, K. S. Yeo and A. Cabuk, “Weak-Inversion Low-power Active Mixer for 2.4GHz ISM Band Applications,” accepted,
IEEE Microwave and Wireless Components Letters, 2009.
3.
A. Meaamar, C. C. Boon, M. A. Do and K. S. Yeo, “A 3-8 GHz Low-noise CMOS Amplifier,” IEEE Microwave and Wireless Components Letters,
vol. 19, pp. 245-247, Apr. 2009.
4.
G. T. Ong and P. K. Chan, “A Low Quiescent Biased Regulator with High PSR Dedicated to Micropower Sensor Circuits,” accepted, IEEE Sensors Journal, 2009.
5.
X. P. Fan, P. K. Chan and P. Y. Chee, “A 150 MS/s 10 bit CMOS Pipelined Subranging ADC with Time Constant Reduction Technique,”
IEICE Trans. on Electronics, vol. E92-C, no. 5, pp. 719-727, May 2009.
6.
S. Chen, A. Bermak and W. Yan, “A Time-to-first-spike Digital Pixel Sensor with On-chip Image Compression based on Predictive Boundary Adaptation
and Least Memory QTD Algorithm,” accepted, IEEE Transactions on Very Large Scale Integration Systems, 2009.
7.
H. Chang and A. Cui, “Synthesis-for-testability Watermarking for Field Authentication of VLSI Intellectual Property,” accepted, IEEE Transactions on
Circuits and Systems, Part I, 2009.
8.
J. Chen and C. H. Chang, “High-level Synthesis Algorithm for the Design of Reconfigurable Constant Multiplier,” IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, vol. 28, no. 12, Dec. 2009.
9.
Y. He and C. H. Chang, “A New Redundant Binary Booth Encoding for Fast 2n-bit Multiplier Design,” IEEE Transactions on Circuits and Systems,
Part I, vol. 56, no. 6, pp. 1192-1201, June 2009.
10.
V. Adrian, J. S. Chang and B. H. Gwee, “A Low Voltage Micropower Digital Class D Amplifier Modulator for Hearing Aids,” IEEE Transactions on
Circuits and Systems, Part I, vol. 56, no. 2, pp. 337-349, Feb 2009.
11.
M. Vamshi Krishna, M. A. Do, K. S. Yeo, C. C. Boon and W. M. Lim “Design and Analysis of Ultra Low Power True Single Phase Clock CMOS
2/3 Prescaler,” accepted, IEEE Transactions of Circuits and Systems, 2009.
12.
H. Q. Liu, W. L. Goh, L. Siek, Y. P. Zhang and W. M. Lim, “A Low-noise Multi-GHz CMOS Multiloop Ring Oscillator with Coarse and
Fine Frequency Tuning,” IEEE Transactions on Very Large Scale Integration Systems, vol. 17, no. 4, pp. 571-577, April 2009.
13.
N. Zhu, W. L. Goh, W. Zhang, K. S. Yeo, and Z. H. Kong, “Design of Low-power High-speed Truncation-error-tolerant Adder and its Application in
Digital Signal Processing,” accepted, IEEE Transactions On Very Large Scale Intergration (VLSI) Systems, August 2009.
14.
C. F. Law, B. H. Gwee and J. S. Chang, “Modeling and Synthesis of Asynchronous Pipelines,” accepted, IEEE Transactions on Very Large Scale Integration
Systems, 2009.
15.
B. H. Gwee, J. S. Chang, Y. Shi, C. C. Chua and K. S. Chong, “A Low-voltage Micropower Asynchronous Multiplier with Shift-add
Multiplication Approach,” IEEE Transactions on Circuits and Systems, Part I, vol. 56, no.7, pp. 1349-1359, July 2009.
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DIVISION OF CIRCUITS AND SYSTEMS
NANYANG TECHNOLOGICAL UNIVERSITY
SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING
Selected Publications in 2009
16.
L. L. Wang, B. K. Tay, K. Y. See, Z. Sun and D. Lua, “Electromagnetic Interference Shielding Effectiveness of Carbon-based Materials Prepared
by Screen Printing,” Carbon, vol. 47, no. 8, pp. 1905-1910, July 2009.
17.
V. Tarateeraseth, B. Hu, K. Y. See and F. G. Canavero, “Accurate Extraction of Noise Source Impedance of an SMPS under Actual Operating Conditions,”
accepted, IEEE Trans. on Power Electronics, 2009.
18.
W. Y. Chang, K. Y. See and B. Hu, “Characterization of Component under DC Biasing Condition using an Inductive Coupling Approach,” accepted,
IEEE Trans. on Test & Instrumentation, 2009.
19.
M. Tan, G. Xu and Y. Liu, “Analysis of Humidity Effects on the Degradation of High-power White LEDs,” Microelectronics Reliability, vol. 49, no. 9-11,
pp. 1226-1230, Sept. 2009
20.
Y. Hou and C. M. Tan, “Comparison of Stress-induced Voiding Phenomena in Copper Line-via Structures with Different Dielectric Materials,”
Semiconductor Science and Technology, vol. 24, no 8, 2009.
21.
W. Li, C. M. Tan and N. Raghavan, “Dynamic Simulation of Void Nucleation during Electromigration in Narrow Integrated Circuit Interconnects,”
Journal of Applied Physics, vol. 105, no. 1, 2009.
22.
M. T. Tan, P. K. Chan, C. K. Lam and C. W. Ng, “AC-boosting Frequency Compensation with Double Pole-zero Cancellation for Multistage Amplifiers,”
accepted, Journal of Circuits, Systems and Signal Processing, 2009.
23.
O. Kurniawan and V. K. S. Ong, “Choice of Generation Volume Models for Electron Beam Induced Current Computation,” IEEE Transactions
on Electron Devices, vol. 56, no. 5, pp. 1094-1099, May 2009.
24.
A. F. Tong, W. M. Lim, K. S. Yeo, C. B. Sia and W. C. Zhou, “A Scalable RFCMOS Noise Model,” IEEE Transactions on Microwave Theory and Techniques,
vol. 57, no. 5, pp. 1009-1019, May 2009.
25.
H. Yu, C. Chu, Y. Shi, D. Smart, L. He and S. X. D. Tan, “Fast Analysis of Large Scale Inductive Interconnect by Block Structure Preserved Macromodeling,”
accepted, IEEE Transactions on Very Large Scale Integration Systems, 2009.
26.
H. Yu, L. He and M. C. F. Chang, “Robust On-chip Signaling using Staggered and Twisted Interconnect,” IEEE Design and Test of Computers, vol. 26,
no. 5, pp. 92-104, Sept. 2009. 
27.
H. Yu, J. Ho and L. He, “Allocating Power Ground Vias in 3D ICs for Simultaneous Power and Thermal Integrity” ACM Transactions on
Design Automation of Electronic Systems, vol. 14, no 3, pp. 41:1 – 41:33, May 2009.
28.
Y. J. Yu, Y. C. Lim and D. Shi, “Low Complexity Design of Variable Bandedge Linear Phase FIR Filters with Sharp Transition Band,” IEEE Trans.
Signal Processing, vol. 57, no. 4, pp. 1328-1338, April 2009.
29.
R. Bregovic, Y. J. Yu, A. Viholainen and Y. C.  Lim, “Implementation of Linear-Phase FIR Nearly Perfect-Reconstruction Cosine-Modulated Filterbanks
Utilizing the Coefficient Symmetry,” accepted, IEEE Transactions on Circuits and Systems, 2009.
30.
Y. J. Yu, D. Shi, and Y.C. Lim, “Design of Extrapolated Impulse Response FIR Filters with Residual Compensation in Subexpression Space,” accepted,
IEEE Transactions on Circuits and Systems, Part I, 2009.
31.
Y. P. Zhang, “Antenna-on-chip and Antenna-in-package Solutions to Highly-integrated Millimeter-wave Devices for Wireless Communications,”
IEEE Transactions on Antennas and Propagation, vol. 57, no. 10, pp. 2830-2841, Oct. 2009.
32.
M. Sun, Y. P. Zhang, G. X. Zheng and W. Y. Yin, “Performance of Intra-chip Wireless Interconnect using On-chip Antennas and UWB Radios,”
IEEE Transactions on Antennas and Propagation, vol. 57, no. 9, pp. 2756-2762, Sept. 2009
33.
Y. P. Zhang, “Enrichment of Package Antenna Approach with Dual Feeds, Guard Ring, and Fences of Vias,” IEEE Transactions on Advanced Packaging,
vol. 32, no. 3, pp. 612-618, Aug. 2009.
34.
Y. Zheng, J. N. Yan, and Y. P. Xu, “A CMOS VGA with DC Offset Cancellation for Direct-Conversion Receivers,” IEEE Transactions on Circuit and Systems,
Part I, vol. 56, no. 1, pp. 103-113, Jan 2009.
35.
S. Diao, Y. Zheng and C. H. Heng, “A CMOS Ultra Low-Power and Highly Efficient UWB-IR Transmitter for WPAN Applications,” IEEE Transactions
on Circuits and Systems, Part II, vol. 56, no. 3, pp. 200-204, March 2009.
36.
D. Han and Y. Zheng, “A Mixed-Signal GFSK Demodulator Based on Multi-Threshold Linear Phase Quantization,” IEEE Transactions on Circuits and
Systems, Part II, vol. 56, no. 9, pp. 719-723, Sep. 2009.
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