Download Chapter 3 Amplifiers with Active Loads – CMOS Amplifiers

Chapter 3 Amplifiers with Active Loads –
CMOS Amplifiers
Section 3.1
Amplifiers with Active Loads
In the last chapter, we noticed that the load RL must be large. There are two
problems here: (1) For IC design, this is not desirable because it is not cost effective
to fabricate a desired resistor, not mentioning the fact that a large resistor will require
a rather large space in the IC. (2) A large resistor may easily drive the transistor out
of saturation as shown in Fig. 3.1-1.
VDD
operating point
RL
IDS
A large RL
VGS increasing
G
D
S
AC
VDD/RL
VGS
VDD
Fig. 3.1-1
VDS=Vout
A large RL driving a transistor out of saturation
It will be desirable if we have a load curve, instead of a load line as shown in Fig.
3.1-2 below:
3-1
operating point
A particular VGS
load curve
IDS
Input signal
Vout = VDS
Output signal
Fig. 3.1-2
A desirable load curve
To achieve this desirable load curve, we may use an active load, instead of a
passive load, such as a resistor.
Let us consider the following PMOS and its I-V
curve as shown in Fig. 3.1-3. Its Vout vs I DS relationship is shown in Fig. 3.1-4.
ISD
VDD
For a certain VSG
VSG
S
G
VSD
D
VDD
Fig. 3.1-3
A PMOS transistor and its I-V curve
3-2
VSD
ISD
VDD
For a certain VSG
S
VSG
VDD
G
VSD
(b) ISD vs VSD
D
ISD
Vout
For a certain VSG
RL
(a) A PMOS transistor circuit
VDD
Vout
(c) ISD vs Vout
Fig. 3.1-4
A PMOS transistor circuit with its I-V diagrams
From Fig. 3.1-4, we can see that a PMOS circuit can be used as a load for an
NMOS amplifier, as shown in Fig. 3.1-5.
ISD2
VDD
VSG2
G
G
S
D
For a certain VSG2
Q2
I
D
Q1
S
VDD
(b) ISD2 vs Vout
I
AC
Vout
ISD2, for a certain VSG2. I , for a certain V .
DS1
GS1
Vout
A
VGS1
VB Vop
VA
Vout = VDS1
(a) A CMOS transistor circuit (c) I-V curves of Q1 and the load curve
Fig. 3.1-5
A CMOS transistor circuit with its I-V curves
It should be noted that both VGS1 and V SG 2 have to be proper. In Fig. 3.1-6,
we show improper VGS1 ’s and in Fig. 3.1-7, we show improper V SG 2 ’s.
3-3
I
VGS1 too high
VGS1 appropriate
VSG2
VGS1 too low
VDD
Fig. 3.1-6
Vout = VDS1
Different VGS1 ’s for a fixed V SG 2
I
VSG2 too high
VSG2 appropriate
VGS1
VSG2 too low
VDD
Fig. 3.1-7
Vout = VDS1
Different V SG 2 ’s for a fixed VGS1
Note that so far as Q1 is concerned, Q2 is its load and vice versa, as shown in the
above figures. Since NMOS and PMOS are complementary to each other, we
call this kind of circuits CMOS circuits.
For the CMOS amplifier shown in Fig. 3.1-5, let us assume that the circuit is
properly biased. Fig. 3.1-8 shows the diagram of the I-V curves of Q1 and its load
curve, which is the I-V curve of Q2.
VDD
IDS1 = ISD2
I2
ISD2 for a certain VSG2.
IDS1 for a certain VGS1.
VSG2
Q2
VGS1
vAC
in
Q1
Vout
VGS1
Vop
VA VDD
(ideal)
(b) I-V curves of Q1 and its load curve
VB
(a) A CMOS transistor circuit
Vout = VDS1
. Fig. 31-8 A CMOS transistor circuit with its I-V curves of Q1 and a load curve for Q1
3-4
Let us imagine that VGS1 increases. Initially, Vout decreases rather slowly.
After it reaches V A , it starts to drop quickly to VB . As can be seen, an ideal
1
(V A  VB ) .
operating point should be around
Fig. 3.1-9 shows the DC
2
input-output diagram and why it behaves as an amplifier..
IDS1 = ISD2
ISD2 for a certain VSG2.
IDS1 for a certain VGS1.
VGS1
VDD
I2
VSG2
Vout = VDS1
VB
Vop
VA
(ideal)
(b) I-V curves of Q1 and the load curve of Q1
Q2
Vout = VDS1
VA
Q1
vinAC
Vout
VGS1
(a) A CMOS amplifier
VB
VGS1
(c)
Fig. 3.1-9
The amplification of input signal
The small signal equivalent circuit of the CMOS amplifier is shown in Fig.
3.1-10. The impedances ro1 and ro 2 are the output impedances of Q1 and Q2
respectively. For ro1 and ro 2 , refer to Section 2.4.
3-5
VDD
I2
G1 `
D1 `
VSG2
Q2
gmvin
vin
Q1
vinAC
Vout
r01
r02
vout
S1
VGSI
(a) A CMOS transistor circuit
Fig. 3.1-10
(b) The small signal equivalent circuit of the CMOS amplifier
A CMOS transistor circuit and its small signal equivalent circuit
As can be seen,
vout   g m vin (r01 // r02 )
(3.1-1)
If r01  r02 , which is often the case, we have
AV 
vout
1
  g m r01
vin
2
(3.1-2)
If a passive load is used, AV  g m RL . Since r01 is much larger than RL which
can be used, we have obtained a larger gain. By passive loads, we mean loads such
as resistors, inductors and capacitors which do not require power supplies.
Section 3.2
Some Experiments about CMOS Amplifiers
The following circuit shown in Fig. 3.2-1 will be used in our SPICE simulation
experiments.
3-6
VDD
R1=0 (pseudo)
5u/0.35u
VSG2=0.9V
S
D
G
AC
G
5u/0.35u
Q2
I
D
Q1
S
Vout
VGS1=0.65V
Fig. 3.2-1
The CMOS amplifier circuit for the Experiments in Section 3.2
Experiment 3.2-1. The I-V Curve of Q1 and the its Load Curve.
In Table 3.2-1, we display the SPICE simulation program of the experiment and in Fig.
3.2-2, we show the I-V curve of Q1 and its load curve. Note that the load curve of Q1
is the I-V curve of Q2.
Table 3.2-1 Program of Experiment 3.2-1
simple
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VDD
11 0
3.3v
R1 11 1
0k
VSG2
11
2
0.9v
V3 3
0
0v
.param W1=5u
M1 3
4
0
0
+nch L=0.35u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 3
2
1
1
+pch L=0.35u
W='W1' m=1
3-7
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VGS1
4
0
0.65v
.DC V3 0 3.3v 0.1v
.PROBE I(M2) I(M1) I(R1)
.end
I-V curve of Q2(load curve of Q1)
IDS
Operating point
I-V curve of Q1
Fig. 3.2-2
VDD
Vout=VDS1
The operating points of the circuit in Fig 3.2-1
Experiment 3.2-2 The Operating Point with the Same VGS1 and a Smaller VSG2.
In this experiment, we lowered V SG 2 from 0.9V to 0.8V. The program is
shown in Table 3.2-2 and the resulting operating point can be seen in Fig. 3.2-3. In
fact, this operating point is close to the ohmic region, which is undesirable.
Table 3.2-2 Program of Experiment 3.2-2
simple
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VDD
11 0
3.3v
3-8
R1 11
1
0k
VSG2
11
2
0.8v
V3 3
0
0v
.param W1=5u
M1 3
4
0
0
+nch L=0.35u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 3
2
1
1
+pch L=0.35u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VGS1
4
0
0.65v
.DC V3 0 3.3v 0.1v
.PROBE I(M2) I(M1) I(R1)
.end
IDS
I-V curve of Q1
I-V curve of Q2(load curve of Q1)
Vout=VDS1
Fig. 3.2-3
The operating points of the amplifier circuit in Fig 3.2-1 with a smaller
VSG 2
Experiment 3.2-3 The Operating Point with the Same VGS1 and a Higher VSG2
3-9
In this experiment, we increased V SG 2 from 0.9V to 1.0V. The program is displayed
in Table 3.2-3 and the result is in Fig. 3.2-4. Again, as can be seen, this new
operating point is not ideal either.
Table 3.2-3 Program of Experiment 3.2-3
simple
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VDD
11 0
3.3v
R1 11 1
0k
VSG2
11
2
1v
V3 3
0
0v
.param W1=5u
M1 3
4
0
0
+nch L=0.35u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 3
2
1
1
+pch L=0.35u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VGS1
4
0
0.65v
.DC V3 0 3.3v 0.1v
.PROBE I(M2) I(M1) I(R1)
.end
3-10
I-V curve of Q2(load curve of Q1)
IDS
I-V curve of Q1
Vout=VDS1
Fig. 3.2-4
The operating points of the amplifier circuit in Fig 3.2-1 with a higher
VSG 2
From the above experiments, we first conclude that to achieve an
appropriate operating point, we must be careful in setting VGS1 and V SG 2 . We
also note that the I-V curves are not so flat as we wished. Therefore, we cannot
expect a very high gain with this kind of simple CMOS circuits. As we shall
learn in later chapters, the gain can be higher if we use a cascode design.
Experiment 3.2-4 The Gain with the Same Bias Voltages in Experiment 3.2-1
We used a signal with magnitude 0.001V and frequency 500kHz. The gain was
found to be 30. The program is shown in Table 3.2-4 and the result is shown in Fig.
3.2-5.
Table 3.2-4 Program of Experiment 3.2-4
simple
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VDD
11 0
3.3v
R1 11 1
0k
3-11
VSG
11
2
0.9v
.param W1=5u
M1 3
4
0
0
+nch L=0.35u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 3
2
1
1
+pch L=0.35u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VGS
Vin 5
4
0
5
0.65v
sin(0 0.001v 500k)
.tran 0.001us 15us
.end
Vin
Vout
Fig. 3.2-5
The gain of the CMOS amplifier for input signal with 500KHz
Experiment 3.2-5 The Gain with the Bias Voltages of Experiment 3.2-2
3-12
In this experiment, we used the bias voltages in Experiment 3.2-2. That is,
VGS1  0.65V and VSG 2  0.8V . The program is in Table 3.2-5 and the result is in
Fig. 3.2-6. As can be seen, the gain was reduced to 20.
Table 3.2-5 The program for Experiment 3.2-5 with VSG 2  0.8V
3.2-5
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VDD
R1 11
VSG2
11
1
0
0k
11
3.3v
2
0.8v
.param W1=5u
M1 3
4
0
0
+nch L=0.35u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 3
2
1
1
+pch L=0.35u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VGS1
4
5
0.65v
Vin 5
0
sin(0 0.001v 500k)
.tran 0.001us 15us
.end
3-13
Fig. 3.2-6 The result of the CMOS amplifier with VSG 2  0.8V
Section 3.3
A Desired Current Source
In a CMOS circuit, a V SG 2 has to be used, as shown in Fig. 3.3-1. In practice, it is
not desirable to have many such power supplies all over the integrated circuit. In this
section, we shall see how this can be replaced by a desired current source and a
current mirror.
VDD
VSG2
S
D
G
G
Q2
I
D
Q1
S
AC
Vout
VGS1
Fig. 3.3-1
A CMOS amplifier with V SG 2
The purpose of V SG 2 is to produce a desired load curve of Q1 as shown in Fig.
3.3-2.
3-14
VDD
VSG2
I
S Q2
D I
G
ISD2 for a certain VSG2
IDS1 for a certain VGS1.
A
DQ
S 1
G
AC
Vout
VGS1
VB
(a) A CMOS amplifier with VSG2
Fig. 3.3-2
Vop
VA
Vout = VDS1
(b) The I-V currents of Q1 and its load curve
A CMOS amplifier, its I-V curves and load lines
The load curve of Q1, which corresponds to a particular I-V curve of Q2, is
shown in Fig. 3.3-3. This load curve is determined by V SG 2 .
VDD
VSG2
G
G
S
D
Q2
ISD2
I
for a particular VSG2
D
Q1
S
AC
Vout
VGS1
VDD Vout
(a) A CMOS amplifier with a VSG2
Fig. 3.3-3
(b) ISD2 vs Vout for the fixed VSG2
A CMOS amplifier with a fixed VSG 2 and its I-V curves
It is natural for us to think that a proper VSG 2 is the only way to produce the
desired load curve for Q1. Actually, there is another way. Note each load curve
almost corresponds to a desired I SD2  I DS1 , as shown in Fig. 3.3-4. In other words,
we may think of a way to produce a desired current in Q2, which of course is also the
current in Q1.
3-15
VDD
VSG2
Q2
S
D
G
I
ISD2
D
Q1
S
G
For a VSG2
Idesired
AC
Vout
VSD2
VGS1
Fig. 3.3-4 An illustration of how a desired current determines the I-V curve
There are two problems here: (1) How can we generate a desired current?
How can we force Q2 to have the desired current?
(2)
To answer the first question, let us consider a typical NMOS circuit with a
resistive load as shown in Fig. 3.3-5.
VDD
IDS
G
RL
D
S
Vout
VGS
Fig. 3.3-5
An NMOS circuit with a resistive load
In the ohmic region, the relationship between the current I DS and different
voltages is expressed as below:
3-16
1
W 
2
I DS  k n '  ((VGS  Vt )VDS  VDS )
2
L
I DS 
(3.3-1)
VDD  VDS
RL
(3.3-2)
Suppose we want to have a desired current I DS . We may think that I DS is a
constant. But, from the above equations, we still have three variables, namely
VGS , VDS and RL . Since there are only two equations, we cannot find these three
variables for a given desired I DS .
In the boundary between ohmic and saturation regions where VDS  VGS  Vt ,
the two equations governing current and voltages in the transistor are as follows:
I DS 
and
1 W 
k n '  (VGS  Vt ) 2
2 L
I DS 
(3.3-3)
VDD  VDS
RL
(3.3-4)
As can be seen, there are still three variables and only two equations.
There is a trick to solve the above problem.
as shown in Fig. 3.3-6.
We may connect the drain to gate
VDD
Id
RL
D
G
S
Fig. 3.3-6
The connection of the drain and the gate
After this is done, we have
3-17
VGS  VDS
(3.3-5)
We have successfully eliminated one variable.
VGS  Vt  VDS  Vt
Besides,
(3.3-6)
From Equation (3.3-6), we have
VDS  VGS  Vt
(3.3-7)
Thus, this connection makes sure that the transistor is in saturation region. Since it
is in the saturation region, we have
I DS 
and
1 W
kn '
2 L
I DS 

2
(VGS  Vt )

(3.3-8)
VDD  VGS
RL
(3.3-9)
Although we often say that a transistor is in saturation if its drain is connected to
its gate, we must understand it is in a very peculiar situation. Traditionally, a
transistor has a family of IV -curves, each of which corresponds to a specified gate
bias voltage VGS and besides, the V DS can be any value as illustrated in Fig. 3.3-2.
Once the drain is connected to the gate, we note the following:
(1) We have lost VDS because it is always equal to VGS . Therefore, we do not have
the traditional IV -curves any more.
(2) For each VGS , since VDS  VGS , we have VDS  VGS  Vt . This transistor is in
saturation. But it is rather close to the boundary between the ohmic region and the
saturation region.
(3) Because of the above point, the relationship between current I DS and voltage
VGS is the dotted line illustrated in Fig. 3.3-7.
3-18
IDS (mA)
VDS  VGS  Vt
Triode
Region
VDS  VGS  Vt
Saturation Region
VGS increasing
D
G
S
VDS (V)
Fig. 3.3-7
The current in an NMOS transistor
(4) We may safely say that the transistor is no longer a transistor. It can be now
viewed as a diode with only two terminals. The relationship between current I DS
and voltage VGS is hyperbolic expressed in Equation 3.3-8.
(5) For a traditional transistor, VGS is supplied by a bias voltage. Since there is no
bias voltage, how do we determine VGS ? Note that the desired current is related to
VGS . This will be discussed in below.
Given a certain desired I DS , VGS can be determined by using Equations (3.3-8).
Thus RL can be found by using Equation (3.3-9). We can also determine VGS and
RL graphically as shown in Fig. 3.3-8. This means that we can design a desired
current source by using the circuit shown in Fig. 3.3-6. By adjusting the value of
RL , we can get the desired current.
Vdd
RL
Id
IDS
IDS1
RL2
D
RL1
IDS2
RL3
G
S
IDS3
VDD
(a) A transistor with drain and gate connected
VGS
(b) The determination of current in a transistor
with drain and gate connected
3-19
Fig. 3.3-8
The generation of a desired current
Let us examine Fig. 3.3-6 again. We do not have to provide a bias voltage VGS
any more. This is a very desirable property which will become clear as we
introduce current mirror. But, the reader should note that a VGS does exist and it
is produced.
In this section, we have discussed how to generate a desired current. In the next
section, we shall show how we can force Q2 to have this desired current. This is
done by the current mirror.
Section 3.4
The Current Mirror
Let us consider the circuit in Fig. 3.4-1.
VDD
Id
VDD
RL
RL
D
Q1
D
G
Q2
G
S
S
Fig. 3.4-1
I2
A current mirror
Assume Q1 and Q2 have the same Vt . Note that Q1 is in the saturation region
and has a desired current I d in it. Assume Q2 is also in the saturation region.
Since VGS1  VGS 2 , by using Equation (3.3-3), we have
 W2 
I 2  L2 

Id
W1 
 L 
1

(3.4-1)
If W1  W2 and L1  L2 , from Equation (3.4-1), we have I 2  I d . Q1 is called a
3-20
current mirror for Q2.
As indicated before, Q2 must be in the saturation region. So our question is:
Under what condition would Q2 be out of saturation I 2  I d . Note that Q2 must be
connected to a load. If the load is too high, this will cause it to be out of
saturation as illustrated in Fig. 3.4-2. Of course, if an improper bias voltage is
used, out of saturation may also occur.
Id
VDD
VDD
RL
RL
IDS2
I2
D
Q1
Current is almost constant
with respect to VDS2
D
G
S
Current changes
with VDS2.
Q2
G
For a fixed VGS2.
(This VGS2 is determined by Id)
S
VDD
Active region
Fig. 3.4-2
VDS2
Saturation region
The out of saturation of Q2
The reader may be puzzled about one thing. We know that if an NMOS
transistor is in the saturation region, its current is determined by VGS . Is this
still true in this case? Our answer is “Yes”. That is, for the circuit in Fig. 3.4-1,
I (Q2 ) is still determined by VGS 2 . This will be shown below.
Note that VDS1  VGS1 , I (Q2 )  I (Q1 ) and VGS 2  VGS1 .
I (Q2 )  I (Q1 ) 
VDD  VDS1
RL
V  VGS1 VDD  VGS 2
 DD

RL
RL
Thus,
(3.4-2)
From Equation (3.4-2), we conclude that I (Q2 ) is determined by VGS 2 .
The advantage of using the current mirror is that no biasing voltage is needed to
give a proper VGS 2 . There is still a VGS 2 . But this VGS 2 is equal to VGS1 which
is in turn determined by I (Q1 ) . I (Q1 ) is determined by selecting a proper RL , as
3-21
illustrated in Fig. 3.4-3.
Id
VDD
VDD
RL
RL
I2
IDS1
VDD/RL
D
D
Q1
G
Q2
G
Id
S
S
Vop=VGS1
=VGS2
Fig. 3.4-3
case.
VDD
VDS1
The determination of the biasing voltage in a current mirror
A current mirror can be based upon a PMOS transistor as in the CMOS amplifier
Fig. 3.4-4 shows a CMOS amplifier with a current mirror.
VDD
VDD
I2
Q3
Id
Q2
RL
Q1
vinAC
Vout
VGS1
Fig. 3.4-4 A PMOS current mirror
We must remember that the purpose of using a current mirror is to generate
a proper I-V curve of Q2. This I-V curve serves as a load curve for Q1 as shown
in Fig. 3.4-5. From Equation (3.3-8) and (3.3-9), we know that by adjusting the
value of RL , we can obtain different current values in Q3, which mean different
I-V curves in Q2. In other words, if we want a different load curve of Q 1, we
may simply change the value of RL .
3-22
Although the above discussed circuit is usually called current mirror, it is
meaningful to call this as a gate voltage mirror. If the current mirror consists of two
NMOS transistors, then VGS1  VGs 2 because the source terminals are connected
together to the ground and the gates are connected to each other. If the current
mirror consists of two PMOS transistors, then VSG1  VSG 2 because the drain
terminals are connected together to VDD and the gates are connected to each other.
VDD
VDD
IDS1 = ISD2
I2
Load curves of Q1 produced
by different RL's
Q3
Q2
For a fixed VGS1
Id
RL
vinAC
Q1
Vout
VGS1
Vop
(ideal)
(a) A current mirror
Fig. 3.4-5
VDD
Vout
(b) Different RL's producing different I-V curves for Q1
The obtaining of different I-V curves for an NMOS transistor through a
current mirror
Section 3.5
Experiments for the CMOS Amplifiers with
Current Mirrors
In this set of experiments, we used the circuit shown in Fig. 3.5-1.
3-23
VDD=3.3V
VDD=3.3V
1
L=0.35u
M3
W3=10u
L=0.35u
M2 W2=10u
4
2
R4=40k
3
M1
VGS1=0.7V
out
L=0.35u
W1=10u
5
Vin
Fig. 3.5-1
The current mirror used in the experiments of Section 3.5
Experiment 3.5-1 The Operating Points of M1 and M3.
In this experiment, we like to find out whether I(M1) is equal to I(M3) or not.
We first try to find the characteristics of M1. The program is shown in Table 3.5-1.
We then do the same thing to M3. The program is shown in Table 3.5-2. The
curves related to M1 are shown in Fig. 3.5-2. The curves related to M3 are shown in
Fig. 3.5-3. Note the I-V curve of M3 is not a typical one for a transistor because the
gate of M3 is connected to the drain of M3.
Table 3.5-1
Program for Experiment 3.5-1
Ex3.5-11
.protect
.lib 'C:\model\tsmc\MIXED035\mm0355v.l' TT
.unprotect
.op
.options nomod post
VDD
R4 4
1
0
0
3.3v
30k
Rdm 1
.param
M1 2
1_1 0
W1=10u W2=10u W3=10u W4=10u
3
0
0
3-24
+nch L=0.35u
W='W1' m=1 AD='0.95u*W1'
+PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 2
4
1_1 1
+pch L=0.35u
+W='W2' m=1 AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M3 4
4
1
1
+pch L=0.35u
+W='W3' m=1 AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
V2 2
VGS1
Vin 5
0
3
0
0v
5
0v
0.7v
.DC V2 0 3.3v 0.1v
.PROBE I(M1) I(Rdm)
.end
Table 3.5-2
Another program for Experiment 3.5-1
Ex3.5-12
.protect
.lib 'c:\mm0355v.l' TT
.unprotect
.op
.options nomod post
VDD
R4 4
1
0
0
3.3v
30k
Rdm 1
1_1 0
.param W1=10u W2=10u W3=10u W4=10u
M1 2
3
0
0
+nch L=0.35u
W='W1' m=1 AD='0.95u*W1'
+PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 2
4
1
1
+pch L=0.35u
3-25
+W='W2' m=1 AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M3 4
4
1_1 1
+pch L=0.35u
+W='W3' m=1 AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
V3 4
VGS1
Vin 5
0
3
0
0v
5
0v
0.7v
.DC V3 0 3.3v 0.1v
.PROBE I(R4) I(Rdm)
.end
IDS1
Load Curve of M1(I-V Curve of M2)
7.9x10-5
I-V Curve of M1
Vout
Fig. 3.5-2
I-V curve and load curve for M1
3-26
I-V Curve of M3
Load Line of R4
7.6x10-5
VDS
Fig. 3.5-3
I-V curve and load line for M3 of the circuit in Fig 3.5-1
From this experiment, we conclude that I(M3)=I(M1) as expected.
Experiment 3.5-2 The Operating Point of M2
The I-V curve of M2 is the load curve of M1. The I-V curve of M2 is
determined by the current mirror mechanism. We were told that the current mirror
works only when M2 is in the saturation region. In this experiment, we first show
the characteristics of M1. The program is shown in Table 3.5-3. The I-V curve of
M2 and its load curve (M1 is the load of M2) are shown in Fig. 3.5-4.
Table 3.5-3
Program for Experiment 3.5-2
Ex3.5-2
.protect
.lib 'c:\mm0355v.l' TT
.unprotect
.op
.options nomod post
VDD
R4 4
1
0
0
3.3v
30k
3-27
.param
W1=10u W2=10u W3=10u W4=10u
M1 2
3
0
0
+nch L=0.35u
W='W1' m=1 AD='0.95u*W1'
+PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 2
4
1_1 1
+pch L=0.35u
+W='W2' m=1 AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M3 4
4
1
1
+pch L=0.35u
+W='W3' m=1 AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
V2 2
VGS1
Vin 5
0
3
0
0v
5
0v
0.7v
.DC V2 0 3.3v 0.1v
.PROBE I(M1) I(Rdm)
Rdm 1
1_1 0
.end
3-28
IDS2
I-V Curve of M2
Load Curve of M2(I-V Curve of M1)
Vout
Fig. 3.5-4
Operating points of M2 of the circuit in Fig 3.5-1
As shown in Fig. 3.5-4, M2 is in the saturation region.
To drive M2 out of the saturation region, we lowered VGS1 from 0.7V to 0.6V.
The program is shown in Table 3.5-4 and the curves are shown in Fig. 3.5-5.
Table 3.5-4
The program to drive M2 out of saturation
Ex3.5-2b
.protect
.lib 'c:\mm0355v.l' TT
.unprotect
.op
.options nomod post
VDD
R4 4
1
0
0
3.3v
30k
.param W1=10u W2=10u W3=10u W4=10u
M1 2
3
0
0
+nch L=0.35u
W='W1' m=1 AD='0.95u*W1'
+PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'
3-29
M2 2
4
1_1 1
+pch L=0.35u
+W='W2' m=1 AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M3 4
4
1
1
+pch L=0.35u
+W='W3' m=1 AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
V2 2
VGS1
0
3
0v
5
Vin 5
0
0v
0.6v
.DC V2 0 3.3v 0.1v
.PROBE I(M1) I(Rdm)
Rdm 1
1_1 0
.end
IDS2
I-V Curve of M2
A smaller VGS1.
Load Curve of M2(I-V Curve of M1)
Vout
Fig. 3.5-5
The out of saturation of M2
3-30
From Fig. 3.5-5, we can see that M2 is now out of saturation. We then printed
the essential data by using the SPICE simulation program in Table 3.5-5. We can see
that I(M2) is quite different from I(M3) now. This is due to the fact that M2 is out of
saturation.
Table 3.5-5 Experimental data for Experiment 3.5-2
subckt
element
model
region
id
ibs
0:m1
0:m2
0:m3
0:nch.3
0:pch.3
0:pch.3
Saturati
Linear Saturati
25.4028u -26.2672u -75.8881u
-3.880e-17 6.373e-18 1.832e-17
ibd
-864.4522n
1.0916f
1.1504f
vgs
600.0000m
-1.0234
-1.0234
vds
3.2166
-83.3759m
-1.0234
vbs
0.
0.
0.
vth
545.8793m -719.8174m -688.8560m
vdsat
85.3814m -293.2779m -318.3382m
beta
6.7003m
1.3100m
1.3166m
gam eff 591.1171m 485.8319m 485.8388m
gm
441.4749u
97.6517u 411.0201u
gds
8.7037u 268.5247u 18.5395u
gmb
cdtot
cgtot
cstot
cbtot
cgs
cgd
111.6472u
11.3338f
10.2012f
21.1660f
27.1028f
5.6263f
2.0774f
22.6467u
28.6456f
16.2693f
31.1152f
38.9009f
8.8368f
7.2706f
87.7975u
14.4251f
12.7341f
30.5144f
33.8541f
9.9096f
1.8392f
The reader must be aware of one important thing. Even a current mirror pair
transistors are both in saturation, they may have different currents.
Suppose two
transistors form a current mirror pair. Their currents will be equal when they have
roughly the same load. To put it in another way, we may say that they will have the
same current when their V sd ’s are roughly the same.
Consider the circuit in Fig.
3.5-1.
Transistors M2 and M3 are a current mirror pair. We do the following two
experiments :
Experiment 3.5-3 The Current Mirror with Roughly the Same Load
We set V gs1  0.7V . The program is in Table 3.5-6 and the result is in Table
3-31
3.5-7. From Table 3.5-7, we can see that Vsd 2  Vsd 3 . Thus the currents of M2 and
M3 are roughly the same.
Table 3.5-6 Program for Experiment 3.5-3 with V gs1  0.7V
.protect
.lib 'C:\mm0355v.l' TT
.unprotect
.op
.options nomod post
VDD
1
0
3.3v
R4 4
0
30k
.param W1=10u W2=10u W3=10u W4=10u
M1 2
3
0
0
+nch L=0.35u
W='W1' m=1 AD='0.95u*W1'
+PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 2
4
1
1
+pch L=0.35u
+W='W2' m=1 AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M3 4
4
1
1
+pch L=0.35u
+W='W3' m=1 AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
VGS1
Vin 5
3
0
5
0v
0.7v
.end
Table 3.5-7 The result of Experiment 3.5-3 with V gs1  0.7V
subckt
element
model
region
id
ibs
0:m1
0:nch.3
0:m2
0:pch.3
0:m3
0:pch.3
Saturati
Saturati
Saturati
79.5086u -79.5373u -75.8881u
-1.211e-16 1.919e-17 1.832e-17
3-32
ibd
-28.6617n
5.6104f
1.1504f
vgs
700.0000m
-1.0234
-1.0234
vds
2.0764
-1.2236
-1.0234
vbs
0.
0.
0.
vth
555.9314m -682.2505m -688.8560m
vdsat
143.4528m -323.6750m -318.3382m
beta
6.6571m
1.3180m
1.3166m
gam eff 591.1204m 485.8393m 485.8388m
gm
894.0008u 422.7631u 411.0201u
gds
14.3304u
18.0766u 18.5395u
gmb
229.7740u
90.3057u 87.7975u
cdtot
cgtot
cstot
12.1394f
13.6902f
27.3788f
13.8074f
12.7341f
30.5142f
14.4251f
12.7341f
30.5144f
cbtot
cgs
cgd
28.2726f
10.1826f
2.0774f
33.2362f
9.9096f
1.8392f
33.8541f
9.9096f
1.8392f
Experiment 3.5-4
The Current Mirror with Different Loads
In this experiment, we set V gs1  0.75V .
The program is the same as in
Experiment 3.5-3. The result is Table 3.5-8. This higher V gs1 makes sure that M2
still in saturation. But now, Vsd 2  2.6  Vsd 3  1.0 . A higher V sd of a PMOS
transistor represents a lower load of it Thus M2 has a smaller load than M3. Thus
M2 has a larger current as can be seen In Table 3.5-8.
subckt
element
model
region
id
ibs
ibd
vgs
vds
vbs
vth
Table 3.5-8
Program for Experiment 3.5-4 with V gs1  0.75V
0:m1
0:nch.3
0:m2
0:pch.3
0:m3
0:pch.3
Saturati
Saturati Saturati
104.3858u -104.3836u -75.8881u
-1.587e-16 2.512e-17 1.832e-17
-13.2955f
2.2633n
1.1504f
750.0000m
-1.0234
-1.0234
688.8019m
-2.6112
-1.0234
0.
0.
0.
568.1324m -636.4667m -688.8560m
3-33
vdsat
169.9490m -360.2912m -318.3382m
beta
6.6283m
1.3277m
1.3166m
gam eff 591.1219m 485.8428m 485.8388m
gm
991.7799u 487.5038u 411.0201u
gds
19.7567u
18.3672u 18.5395u
gmb
262.4467u 104.1232u 87.7975u
cdtot
14.0246f 11.0626f 14.4251f
cgtot
14.0367f
12.7340f 12.7341f
cstot
27.9954f 30.5126f 30.5144f
cbtot
30.1844f 30.4899f 33.8541f
cgs
10.6443f
9.9096f
9.9096f
cgd
2.0774f
1.8392f
1.8392f
When two identical transistors form a current mirror pair are both in saturation
region, according to Equation (3.4-1), they should have the same current. But, from
the above experiment, we know that they may have different currents. What is
wrong? Is Equation (3.4-1) wrong?
We must understand that Equation (3.4-1) is based upon one assumption: The
IV curves of the transistors are absolutely flat as illustrated in Fig. 3.5-6(a). If this is
indeed the case, then we can see that different loads will produce the same current.
But in reality, most transistors do not have such kind of flat I-V curves. Instead,
their I-V curves are as illustrated in Fig. 3.5-6(b). In such a situation, different loads
will produce different currents.
3-34
Ids
(a)
Vds
Ids
Vds
(b)
Fig. 3.5-6
Two I-V curves
A better equation for the currents in a current mirror is as follows:
W2 1  V 
DS 2
I 2  L2 

Id
W1 1  V 
 L 
DS 2
1

(3.5-1)
In the above equation,  is related to the slope of the I-V curve.
curve is flat,  is small and  cannot be ignored if otherwise.
If the I-V
From Equation (3.5-1), we can see that for a current mirror pair, I 2  I1 if 
is small or VDS 2  VDs1 . Note that VDS 2  VDs1 means that the two transistors have
the same load.
In the later chapters, we shall introduce the cascoded transistors. They have
very flat I-V curves.
3-35
Experiment 3.5-5 The DC Input-Output Relationship of M1.
In this experiment, we plotted VDS1 versus VGS1 . The program is in Table
3.5-9 and the DC input-output relationship is shown in Fig. 3.5-7.
Table 3.5-9 Program of Experiment 3.5-3
.protect
.lib 'c:\mm0355v.l' TT
.unprotect
.op
.options nomod post
VDD
R4 4
1
0
0
3.3v
30k
.param W1=10u W2=10u W3=10u W4=10u
M1 2
3
0
0
+nch L=0.35u
W='W1' m=1 AD='0.95u*W1'
+PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 2
4
1
1
+pch L=0.35u
+W='W2' m=1 AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M3 4
4
1
1
+pch L=0.35u
+W='W3' m=1 AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
VGS1
3
0
0v
.DC VGS1 0 3.3v 0.1v
.PROBE I(M1)
.end
3-36
VDS1
VGS1
Fig. 3.5-7
Section 3.6
VDS1 vs VGS1
The Current Mirror with an Active Load
In the above sections, the current mirror has a resistive load. As we indicated before,
a resistive load is not practical in VLSI design. Therefore, it can be replaced by an
active load, namely a transistor. Fig. 3.6-1 shows a typical CMOS amplifier whose
current mirror has an active load.
VDD
VDD
Q3
Q2
Q4
Q1
0.7v
Vout
Vin
0.7v
Fig. 3.6-1
A current mirror with an active load
3-37
In the above circuit, Q3 is a current mirror while Q4 is its load. Note that the
main purpose of having a current mirror is to produce a desired basing current in Q2
which is equal to the current in Q3. To generate such a desired current, we use the
I-V curve of Q3 and its load curve, which is the I-V curve of Q4. These curves are
shown in Fig. 3.6-2.
I
IQ3
IQ4 for a fixed VGS4
Vop4
VDS4
Idesired
Fig. 3.6-2
The determination of operating point for M4 in Fig. 3.6-1
Note that we have a desired current in our mind. So we just have to adjust
VGS 4 such that its corresponding I-V curve intersects the I-V curve of Q3 at the proper
place which gives us the desired current in Q4, which is also the current in Q3.
We indicated before that we like to use current mirrors because we do not like to
have two biases as required in a CMOS circuit shown in Fig. 3.1-5. One may
wonder at this point that we need two power supplies (constant voltage sources) for
this current mirror circuit in the circuit shown in Fig. 3.6-1. Note that in this circuit,
although there are two biases, they can be designed to be the same. Thus, actually,
we only need one bias.
Besides, it will be shown in the next chapter that the current mirror actually has
an entirely different function. That is, it provides a feedback in the differential
amplifier which gives us a high gain.
Section 3.7
Experiments with the Current Mirror with an
Active Load
In the following experiments, we used the amplifier circuit shown in Fig. 3.7-1.
3-38
VDD=3.3V
L=0.35u
M3
W3=10u
M2
L=0.35u
W2=10u
out
Vbias=0.7V
M4
L=0.35u
W4=10u
M1
0.7V
L=0.35u
W1=10u
Vin
Fig. 3.7-1
The current mirror circuit for experiments in Section 3.7
Experiment 3.7-1 The Operating Point of M4.
The program for this experiment is shown in Table 3.7-1. The curves are
shown in Fig. 3.7-2. We like to point out again that the load curve of M4 is the I-V
curve of M3. This I-V curve of M3 is hyperbola because the gate of M3 is
connected to the drain of M3. The result shows that the current is 100u, a quite
small value.
Table 3.7-1 Program for Experiment 3.7-1
.protect
.lib 'c:\mm0355v.l' TT
.unprotect
.op
.options nomod post
VDD
1
0
3.3v
.param
M1 2
W1=10u W2=10u W3=10u W4=10u
3
0
0
+nch L=0.35u
W='W1' m=1 AD='0.95u*W1'
+PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 2
4
1_1 1
+pch L=0.35u
+W='W2' m=1
AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M3 4
4
3_1 1
+pch L=0.35u
3-39
+W='W3' m=1
AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
M4 4
5
0
0
+nch L=0.35u
+W='W4' m=1
AD='0.95u*W4' PD='2*(0.95u+W4)'
+AS='0.95u*W4' PS='2*(0.95u+W4)'
V4
VGS1
VGS4
Vin
4
3
5
6
6
0
0
0.7v
0.7v
0
0v
0v
.DC V4 0 3.3v 0.1v
.PROBE I(M4) I(Rm3)
Rdm
1
1_1 0
Rm3
1
3_1 0
.end
IDS4
VDS4
Fig. 3.7-2 Operating point of M4
The gain of this amplifier was found to be 30. The program for this testing is in
Table 3.7-2 and the signals are shown in Fig. 3.7-3.
3-40
Table 3.7-2
Program of the gain in Experiment 3.7-1
.protect
.lib 'c:\mm0355v.l' TT
.unprotect
.op
.options nomod post
VDD
1
0
3.3v
.param
W1=10u W2=10u W3=10u W4=10u
M1 2
3
0
0
+nch L=0.35u
W='W1' m=1 AD='0.95u*W1'
+PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 2
4
1
1
+pch L=0.35u
+W='W2' m=1 AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M3 4
4
1
1
+pch L=0.35u
+W='W3' m=1 AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
M4 4
5
0
0
+nch L=0.35u
+W='W4' m=1 AD='0.95u*W4' PD='2*(0.95u+W4)'
+AS='0.95u*W4' PS='2*(0.95u+W4)'
VGS1
VGS4
Vin 6
3
5
0
.tran 0.1ns
.end
6
0.7v
0
0.7v
sin(0v 0.01v 10Meg)
600ns
3-41
Fig. 3.7-3
The gain of the amplifier in Experiment 3.7-1
Experiment 3.7-2 The Influence of VGS4
In this experiment, we increased VGS 4 from 0.7V to 0.75V. This will raise the
current in M3 and consequently that of M2. The program to test the gain is shown in
Table 3.7-3 and the signals are shown in Fig. 3.7-4. The gain was reduced to 6.
Table 3.7-3
Program for Experiment 3.7-2
.protect
.lib 'c:\mm0355v.l' TT
.unprotect
.op
.options nomod post
VDD
1
0
3.3v
.param W1=10u W2=10u W3=10u W4=10u
M1 2
3
0
0
+nch L=0.35u
W='W1' m=1 AD='0.95u*W1'
+PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'
3-42
M2 2
4
1
1
+pch L=0.35u
+W='W2' m=1 AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M3 4
4
1
1
+pch L=0.35u
+W='W3' m=1 AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
M4 4
5
0
0
+nch L=0.35u
+W='W4' m=1 AD='0.95u*W4' PD='2*(0.95u+W4)'
+AS='0.95u*W4' PS='2*(0.95u+W4)'
VGS1
VGS4
Vin 6
3
5
0
.tran 0.1ns
.end
6
0.7v
0
0.75v
sin(0v 0.01v 10Meg)
600ns
Fig. 3.7-4
The gain in Experiment 3.7-2
3-43
Section 3.8 A Summary of the Current Mirror Technology
To make the idea of the current mirror clear, let us make a summary of it as
follows. Consider the CMOS transistor circuit as shown in Fig. 3.8-1.
VDD
VSG2
Q2
Q1
Vout
VGS1
Fig. 3.8-1 A CMOS transistor circuit
Suppose we have already selected a certain VGS1 for Q1. This VGS1 will
produce an I  V - curve as shown in Fig. 3.8-2. This VGS1 can be so selected that
it will produce a desired current in Q1.
IDS1
For a VGS1
Idesired
Vout=VDS1
Fig. 3.8-2 The I  V curve of the NMOS transistor in Fig. 3.8-1 under the
assumption that I desired is specified
We now need to select an appropriate V SG 2 for Q2. This V SG 2 needs to
produce an I  V - curve for Q2 as shown in Fig. 3.8-3. In other words, these two
I  V - curves must match.
3-44
IDS1=ISD2
For an appropriate VSG2
For a VGS1
Idesired
VDD Vout=VDS1
Fig. 3.8-3 The matching of the IV curves of the two transistors
A well-experienced reader will understand that V SG 2 is usually not equal to
VGS1 . Therefore, we have to use two different power supplies to bias our transistors.
The current mirror technology tries to avoid the necessity of having two power
supplies. Instead of thinking giving Q2 an appropriate bias voltage, we shall give it
an appropriate current because we all know that a bias voltage will correspond to a
current if the transistor is in the saturation region.. This appropriate current must be
the desired current for Q1. Consider Fig. 3.8-4.
VDD
Q4
Q3
VGS3=VGS1
Fig. 3.8-4 A CMOS transistor where the gate and the drain of the PMOS transistor
are connected together
Suppose Q3 is identical to Q1 in Fig. 3.8-1 and we have VGS 3  VGS1 . Then the
I  V - curve for Q3 will be identical to that for Q1. Furthermore, since Q4 is in the
saturation region because of the connection of its drain to gate, the IV - curve for
Q4 will be a hyperbola curve. Fig. 3.8-5 shows that we will have the desired current
3-45
in Q3 and Q4 .
IDS3=ISD4
Load curve of Q3 (I-V curve of Q4)
I-V curve for VGS3=VGS1
Idesired
VDS3
Fig. 3.8-5 The current in Q3
We now connect these two circuits together to construct a current mirror as
shown in Fig. 3.8-6.
VDD
Q4
Q2
Q3
Q1
VGS3
Fig. 3.8-6
VGS3=VGS1
Q3=Q1
Q4=Q2
Vout
VGS1
A complete current mirror circuit
Assuming that Q4 and Q2 are identical, we shall have a desired current in Q2
which is also the desired current for Q1 . Thus we have avoided having two
different power supplies. But, we must realize that we still have given Q2 an
appropriate VSG 2 . Note that VSG 2  VSG 4 . V SG 4 is created, not supplied. This
can be understood by considering the I  V - curves of Q4 shown in Fig. 3.8-7.
We can now see that once we have the desired current for Q2 , we have also got the
desired bias voltage for Q2 . Thus we may really call the current mirror circuit a
“bias voltage mirror”.
3-46
IDS4
I-V curve of Q4
Load curve of Q4
(I-V curve of Q3)
Idesired
VDD VSG4
VSG4 = VSG2
Fig. 3.8-7
The current and V SG 4 in Q4
Section 3.9 A Further Discussion of Current Mirror
In the previous sections, we assumed that for a current mirror pair with identical
transistors, if they are both in the saturation region, the currents will be the same.
This was actually under the assumption that the I  V curves are absolutely flat.
Let us consider the current mirror pair as shown in Fig. 3.9-1. In the figure, the
determination of the current in Q1 is also shown.
Id
VDD
VDD
RL
RL
I2
IDS1
VDD/RL
D
Q1
D
G
S
Q2
G
Id
S
Vop=VGS1
=VGS2
VDD
VDS1
Fig. 3.9-1 A current mirror pair and the determination of current in Q1
The determination of current in Q2 is shown in Fig. 3.9-2.
In Fig. 3.9-2(a),
we assume that the I  V curve of Q2 is absolutely flat. Under such condition,
different of loads will produce the same current. In Fig. 3.9-2(b), we assume that the
3-47
I  V curve of Q2 is not absolutely flat.
produce different currents.
As can be seen, different loads will
IDS
VDS
(a)
IDS
(b)
VDS
Fig. 3.9-2 The determination of current in Q2
Different load lines determine different V DS ’s. We therefore may say that for a
current pair with identical transistors, the currents will be the same if and only if the
two transistors are both in saturation region and have the same V DS , Thus a more
refined equation for the currents of a current mirror pair is as follows:
I 2 1  VDS 2

I1 1  VDS1
(3.9-1)
The parameter  in Equation (3.9-1) reflects the slope of the I  V curve of
the transistor. If the I  V curve is very flat,  will be very small and the two
currents will be almost the same.
Let us consider Fig. 3.9-3.
This is a rather unusual case because the two
3-48
transistors in the current mirror pair are fed with constant current sources. But it is
used in the rail to rail comparator circuit introduced when we discuss operational
amplifier. In this circuit, if I 2  I1 , by using Equation (3.9-1), we will have
VDS 2  VDs1 and vice versa. To put it in another way, if I 2 is large(small), Vout
will be high(low).
I1
I2
Vout
D
D
Q1
G
Q2
G
S
S
Fig. 3.9-3
A current mirror fed with different current sources
Experiment 3.9-1 An Experiment to Confirm Equation (3.9-1)
In this experiment, we set I1  1ma and I 2  0.95ma . The program is in
Table 3.9-1 and the result is in Table 3.9-2. As shown in Table 3.9-2,
VDS1  1.031v  VDS 2  0.578v which confirms Equation (3.9-1)
I1
I2
Vout
D
Q1
D
G
Q2
G
S
S
3-49
Table 3.9-1 The program for Experiment 3.9-1
Exp0325
.protect
.lib ‘c:\mm0355v.l’ TT
.unprotect
.op
.options nomod post
VDD
VDD!
0
3.3v
M1 1
M2 2
1
1
0
0
NCH
NCH
0
0
L=0.35U W=10U M=2
L=0.35U W=10U M=2
i1 VDD! 1 1000u
i2 VDD! 2 950u
.end
Table 3.9-2 The result of Experiment 3.9-1
subckt
element
model
region
id
ibs
ibd
vgs
vds
0:m1
0:m2
0:nch.3
0:nch.3
Saturati
Saturati
1.0000m 950.0000u
-1.4627f -1.3916f
-26.6812f -26.1682f
1.0310
1.0310
1.0310 578.8480m
vbs
0.
0.
vth
565.4705m 569.4205m
vdsat
343.8641m 341.7802m
beta
12.9697m 12.9654m
gam eff 591.1455m 591.1440m
gm
3.2988m
3.1402m
gds
84.2507u 172.9488u
gmb
859.3150u 828.1345u
3-50
cdtot
23.7543f
25.2259f
cgtot
cstot
cbtot
cgs
cgd
28.4759f
28.4760f
52.6396f 52.6405f
51.9305f 53.4031f
21.9311f
21.9311f
4.1549f
4.1549f
Section 3.10 A Rail to Rail Comparator Which Is Suitable
for High and Low Inputs
In this section, we will introduce a comparator.
comparator is shown in Fig. 3.10-1
The schematic diagram of a
INP
Comparator
VOUT
INN
Fig. 3.10-1 The schematic diagram of a comparator
If INP  INN , Vout is
high and if INP  INN , Vout is low. For a rail to rail comparator, we insist that the
input voltages can be of any value. In other words, they can be very high or very
low. Fig. 3.10-2 shows such a comparator.
The comparator compares the inputs INP and INN.
M13
M8
M7
M1
M9
M2
M17
M14
M18
M10
VOUT
INN
INP
M16
M5
M3
M6
M11
M12
M4
Fig. 3.10-2
A rail to rail comparator
3-51
M15
The basic ideas of the above circuit are as follows:
1. M8 and M12 are constant current sources while M7 and M11 determine the
currents.
2. Because of the constant current sources, if I(M2) is large (small), I(M1) will be
small (large). Similar argument applies to I(M10) and I(M9).
3. The following pairs of transistors are current mirrors: (M3,M4), (M5,M6),
(M13,M17) and (M14,M18).
4. M17 and M18 constitute a pair of PMOS’s to have a Vout either high or low.
We shall show that if INP  INN , I ( M 18)  I ( M 17) and Vout will be high and if
INP  INN , I ( M 18)  I ( M 17) and Vout will be low.
5. The inputs INP and INN are gate voltages of M10 and M 9 respectively.
There are the following two cases:
Case 1: At least one of M10 and M 9 is turned on. This happens when at least
one of them is high enough. In this case, among M 13 and M 14 , one of them will
have larger current.
Suppose
INP  INN , we can see that
I ( M 14)  I ( M 10)  I ( M 13)  I ( M 9) . Because of the current pair effect, we can
see that in this case, I ( M 18)  I ( M 14)  I ( M 17)  I ( M 13) . Using the same
argument, we can see if INP  INN . I ( M 18)  I ( M 17) .
Let us redraw the last stage of the circuit involving M 13 to M18 as shown in
Fig. 3.10-3. The currents of M17 and M18 are the same as the currents of M 13
and M 14 respectively. We may consider M17 and M18 as constant current
sources feeding constant currents into the current mirror pair M15 and M16 . As
discussed above, if I ( M 18)  I ( M 17) , VDS16  VDS15 . In other words, Vout will be
high. Using the same argument, we can see that if I ( M 18)  I ( M 17) , Vout will be
low.
3-52
M13
M17
M14
M18
VOUT
M16
M15
Fig. 3.10-3 The last stage of the rail to rail comparator
There is an important point to be noted here. As experiments will show later,
the currents in our circuits are all very small, around 2  . As shown in Fig. 3.10-4,
if I ( M 18)  I ( M 17) , Vout will be very high and if I ( M 18)  I ( M 17) , Vout will be
very low. If the current in the constant current source is not that small, we will not
have this effect.
I(M16)
Load curve of M16
when I(M18) is high
IV-curve of M16 Load curve of M16
when I(M18) is low
Vout=VDS16
3-53
Fig. 10.3-4 The V out of the rail to rail comparator
In conclusion, for Case 1 where at least one of M 9 and M10 is turned on, if
INP  INN , Vout will be very high and if INP  INN , Vout will be very low.
Case 2: Both M 9 and M10 are cutoff. This happens when both input voltages
are very low. Note that the two input voltages are also input gate voltages of M 1
and M 2 . Since both inputs are of low voltages, at least one of M 1 and M 2 will
be turned on.
Let us suppose INP  INN .
In this case, I ( M 1)  I ( M 2) .
Thus
I ( M 3)  I ( M 6) . But I ( M 3)  I ( M 4) and I ( M 6)  I ( M 5) due to the current
mirror effect. Therefore, I ( M 4)  I ( M 5) . But I (M 4) is supplied by M 14
and I (M 5) is supplied by M 13 . Therefore, I ( M 14)  I ( M 13) . Due to the
current pair effect, I ( M 18)  I ( M 17) and Vout will be high which is correct.
The same argument will give us the following conclusion: When both M 9 and
M10 are cutoff and INP  INN , Vout will be high which is correct.
Experiment 3.10-1
The Testing of a Rail to Rail Comparator
In this experiment, we tested the rail to rail comparator in Fig. 3.10-2. The
program is in Table 3.10-1 and the result is in Fig. 3.10-5. As can be seen, it is
indeed a rail to rail comparator. It works when both inputs are high and when both
inputs are low.
Table 3.10-1
The program for the rail to rail comparator testing
Rail_to_Rail_Comparator
.PROTECT
.OPTION POST
.lib "d:\model\tsmc\MIXED035\mm0355v.l" TT
.UNPROTECT
.op
M6
M3
M8
M1
N1N322 N1N322 VSS VSS NCH L=2U W=3U M=2
N1N320 N1N320 VSS VSS NCH L=2U W=3U M=2
VVG I2U_S VDD VDD PCH L=5U W=6U M=2
N1N320 INN VVG VDD PCH L=2U W=6U M=2
3-54
M2
N1N322 INP VVG VDD PCH L=2U W=6U M=2
M7
M5
M4
I2U_S I2U_S VDD VDD PCH L=5U W=6U M=2
N1N365 N1N322 VSS VSS NCH L=2U W=3U M=2
N1N362 N1N320 VSS VSS NCH L=2U W=3U M=2
M10 N1N362 INP N1N372 VSS NCH L=2U W=3U M=2
M11
I2U I2U VSS VSS NCH L=5U W=5U M=2
M12 N1N372 I2U VSS VSS NCH L=5U W=5U M=2
M9 N1N365 INN N1N372 VSS NCH L=2U W=3U M=2
M14 N1N362 N1N362 VDD VDD PCH L=2U W=6U M=2
M13 N1N365 N1N365 VDD VDD PCH L=2U W=6U M=2
M17
M18
N1N431 N1N365 VDD VDD PCH L=2U W=6U M=2
VOUT N1N362 VDD VDD PCH L=2U W=6U M=2
M15
M16
N1N431 N1N431 VSS VSS NCH L=2U W=3U M=2
VOUT N1N431 VSS VSS NCH L=2U W=3U M=2
vdd vdd gnd 1.5
vss vss gnd -1.5
v01 inn gnd -1.2
v02 inp gnd pwl(0 -1.5 0.5m 1.5 1m -1.5)
i01 i2u_s vss 2u
i02 vdd i2u 2u
.tran 0.1u 1m
.probe v(VOUT)
.END
3-55
INN
INP
VOUT
VOUT
INP
INN
Fig. 3.10-5
Experiment 3.10-2
The performance of the rail to rail comparator
The First Analysis of the New Comparator
In this experiment, we set INN  1.2V and INP  1.2V . This case belongs
to Case 1. Note that M10 is turned off by INP which is too low. But M 9 is
turned on by INN which is high enough Since we have INP  INN , we should
have Vout to be low. The experimental result shows that it is indeed the case.
The program and the results are all in Table 3.10-2.
Table 3.10-2
Program and Results for INN  1.2V and INP  1.2V .
****** Star-HSPICE -- 2001.4 (20011215) 16:53:22 02/01/2014 pcnt
Copyright (C) 1985-2001 by Avant! Corporation.
3-56
Unpublished-rights reserved under US copyright laws.
This program is protected by law and is subject to the
terms and conditions of the license agreement found in:
C:\avanti\Hspice2001.4\license.txt
Use of this program is your acceptance to be bound by this
license agreement. Star-HSPICE is the trademark of
Avant! Corporation.
Input File: c:\work\test.sp
lic:
lic: FLEXlm:v7.2
USER:cwlu
HOSTNAME:cwlu-PC
PID:1023756
lic: Using FLEXlm license file:
lic: c:\flexlm\license.dat
lic: Checkout hspicewin; Encryption code: 26F03DEB9F8B
lic: License/Maintenance for hspicewin will expire on 1-jan-0/2020.0
lic: NODE LOCKED DEMO license on host cwlu-PC
lic:
Init: read install configuration file: C:\avanti\Hspice2001.4\meta.cfg
Init: hspice initialization file: C:\avanti\Hspice2001.4\hspice.ini
* hspice.ini
*
* use ascii only for initial pc star-hspice release
*
.option post = 2
.op
m6
m3
m8
m1
m2
m7
m5
m4
m10
m11
m12
n1n322 n1n322 vss vss nch l=2u w=3u m=2
n1n320 n1n320 vss vss nch l=2u w=3u m=2
vvg i2u_s vdd vdd pch l=5u w=6u m=2
n1n320 inn vvg vdd pch l=2u w=6u m=2
n1n322 inp vvg vdd pch l=2u w=6u m=2
i2u_s i2u_s vdd vdd pch l=5u w=6u m=2
n1n365 n1n322 vss vss nch l=2u w=3u m=2
n1n362 n1n320 vss vss nch l=2u w=3u m=2
n1n362 inp n1n372 vss nch l=2u w=3u m=2
i2u i2u vss vss nch l=5u w=5u m=2
n1n372 i2u vss vss nch l=5u w=5u m=2
3-57
HOSTID:
m9
n1n365 inn n1n372 vss
nch l=2u w=3u m=2
m14
m13
n1n362 n1n362 vdd vdd pch l=2u w=6u m=2
n1n365 n1n365 vdd vdd pch l=2u w=6u m=2
m17
m18
m15
m16
n1n431 n1n365 vdd vdd pch l=2u w=6u m=2
vout n1n362 vdd vdd pch l=2u w=6u m=2
n1n431 n1n431 vss vss nch l=2u w=3u m=2
vout n1n431 vss vss nch l=2u w=3u m=2
vdd vdd gnd 1.5
vss vss gnd -1.5
v01 inn gnd 1.2
v02 inp gnd pwl(0 -1.2 0.5m -1.2 1m -1.2)
i01 i2u_s vss 2u
i02 vdd i2u 2u
.tran 0.1u 1m
.probe v(vout)
.end
1 ******
Star-HSPICE -- 2001.4
(20011215) 16:53:22
02/01/2014
pcnt
******
rail_to_rail_comparator
****** operating point information
tnom= 25.000 temp= 25.000
******
***** operating point status is all
simulation time is
0.
node
=voltage
node
=voltage
node
=voltage
+0:i2u
=-891.2839m 0:i2u_s = 616.5880m 0:inn
= 1.2000
+0:inp
= -1.2000 0:n1n320 = -1.3953 0:n1n322 =-906.5721m
+0:n1n362 = 1.2007 0:n1n365 = 626.2582m 0:n1n372 = 219.5969m
+0:n1n431 =-850.6398m 0:vdd
= 1.5000 0:vout
= -1.5000
+0:vss
= -1.5000 0:vvg
=-113.5773m
**** voltage sources
3-58
subckt
element 0:vdd
0:vss
0:v01
volts
1.5000
-1.5000
1.2000
current -14.8383u
14.8383u
0.
power
22.2575u
22.2575u
0.
0:v02
-1.2000
0.
0.
total voltage source power dissipation=
44.5150u
watts
***** current sources
subckt
element
0:i01
volts
current
power
0:i02
2.1166
2.0000u
-4.2332u
2.3913
2.0000u
-4.7826u
total current source power dissipation=
-9.0157u
watts
**** mosfets
subckt
element
model
region
id
ibs
ibd
0:m6
0:nch.1
Saturati
2.0365u
0:m3
0:nch.1
0:m1
0:pch.1
Cutoff
0:pch.1
Saturati
7.9269p
-3.505e-18 -1.401e-23
-9.2878f
0:m8
Cutoff
-2.0365u
4.073e-19
-9.1303f
18.3741f
vds
593.4279m 104.7496m
vth
vdsat
beta
0.
0.
606.5518u
Saturati
Saturati
0.
1.3136
-2.0365u
1.1318f
1.1318f
-1.0864
-1.2817
0.
1.6136
1.6136
-1.0135
-1.0153
41.6315m -177.7796m
609.4420u 155.7470u
-2.0000u
4.000e-19
-1.6136
543.2795m 543.9419m -748.1164m
96.6985m
0:pch.1
1.1318f
593.4279m 104.7496m -883.4120m
0:m7
0:pch.1
1.1318f
vgs
vbs
0:m2
1.1318f
-883.4120m
-792.9949m -883.4120m
0.
-749.3364m
-50.1839m -133.9215m -176.8155m
349.2394u
3-59
344.2959u
155.7131u
gam eff
gm
gds
454.9560m 454.9563m 412.0847m 407.8679m 407.8679m 412.0847m
32.9696u
93.0728n
gmb
233.1712p
3.9594p
9.6691u
8.3255f
cgtot
33.0035f
cstot
38.7243f
9.4240f
cbtot
29.9577f
31.7010f
cgs
23.2469f
cgd
1.2667f
0.
46.4605n
78.2604p
cdtot
21.0827u
9.1574f
29.4172u
0.
4.9809u
155.3928n
0.
20.7946u
55.4900n
3.8780u
4.9129u
13.7487f
11.5579f
12.2445f
18.1864f 187.9780f
30.4049f
62.5419f 187.9781f
224.9786f
13.7487f
71.2622f
224.9787f
92.8041f
46.8543f
36.1089f
94.9632f
1.2667f 161.4899f
2.2143f
1.2667f
2.2143f
2.2143f
15.9078f
52.3653f 161.4900f
2.2143f
2.2143f
0:m12
0:m9
subckt
element
model
region
id
0:m5
0:nch.1
0:m4
0:nch.1
Saturati
2.1777u
ibd
-209.3898p
2.7007
vbs
0.
0.
vdsat
Saturati
0:nch.1
0:nch.1
Saturati
Saturati
2.0000u
2.0438u
-9.2878f -3.199e-18 -3.269e-18
593.4279m 104.7496m
2.1263
0:nch.1
0.
-23.3231f
vds
0:m11
Cutoff
10.2317p
-3.748e-18 -2.691e-23
vth
0:nch.1
Cutoff
ibs
vgs
0:m10
-9.2878f
-14.1098f
-1.4196
2.0439u
-9.2878f
-4.1553p
-9.2878f
608.7161m 608.7161m 980.4031m
981.0581m 608.7161m
-1.7196
0.
1.7196
406.6613m
0.
-1.7196
541.1929m 540.4078m 929.3768m 537.8483m 536.8917m 930.1489m
97.8961m
41.6315m
44.7769m 114.9326m 115.5472m 103.5167m
beta
606.6705u
gam eff
454.9560m 454.9563m 419.4380m 462.0946m 462.0946m 419.4378m
gm
gds
34.6402u
118.4587n
609.7366u 580.1696u
300.9120p
1.8632p
402.3561u
0.
0.
402.3913u
28.8390u
42.2651n
0.
575.8428u
29.2914u
39.8855n
102.3707n
gmb
10.1640u
100.9692p
cdtot
7.1737f
6.9351f
6.9351f
13.1056f
11.6350f
7.1737f
cgtot
33.0033f
18.1864f
16.9216f
144.5955f
144.5954f
37.9447f
cstot
38.7240f
9.4240f
7.3834f 163.3203f
163.3201f
43.4977f
cbtot
28.8059f
29.4787f
85.4179f
83.9473f
21.6511f
26.1734f
8.6615u
33.6203u
8.7988u
6.1839u
cgs
23.2466f
1.2667f
1.2667f
112.9988f
112.9987f
31.9434f
cgd
1.2667f
1.2667f
1.2667f
2.0919f
2.0919f
1.2667f
subckt
3-60
element
model
region
0:m14
0:pch.1
0:m13
0:pch.1
Cutoff
Saturati
0:m17
0:m18
0:pch.1
0:pch.1
Saturati
-27.2318p
-4.2217u
-4.5800u
ibs
5.567e-24
8.441e-19
9.157e-19
ibd
1.1318f
1.1319f
0:m16
0:nch.1
Cutoff
id
0:m15
0:nch.1
Saturati
-38.1010p
Linear
4.5800u
50.1032p
8.821e-24 -7.882e-18 -8.626e-23
10.6560p
2.1810f
-9.2878f -2.894e-19
vgs
-299.3450m -873.7418m -873.7418m -299.3450m 649.3602m 649.3602m
vds
-299.3450m -873.7418m
vbs
vth
0.
-2.3506
0.
-3.0000
0.
649.3602m 800.8438n
0.
0.
0.
-755.5812m -753.3571m -747.6275m -745.1034m 543.2070m 544.0845m
vdsat
-47.7563m -168.6889m -173.2276m
-47.7570m 132.4373m 131.8442m
beta
379.0230u
380.2017u
gam eff
405.5279m 405.5279m 405.5279m 405.5279m 454.9557m 454.9563m
371.9200u 372.2863u
46.7282u
49.6449u
604.5423u
1.0583n
604.4957u
gm
757.9553p
gds
4.4157p
gmb
212.0479p
cdtot
18.8069f
15.9447f
12.3327f
11.4275f
8.2566f
51.5858f
cgtot
30.4154f
74.7540f
74.7538f
30.4154f
39.9154f
53.8147f
cstot
21.1724f
98.3694f
98.3690f
21.1724f
50.4498f
54.2498f
cbtot
61.5375f
56.4639f
52.8519f
54.1581f
30.4686f
32.3148f
277.6103n 227.4293n
10.6467u
4.4269p
58.5379u
166.2485n
11.3100u 294.2883p
398.8819p
62.6001u
17.0758u 119.8347p
cgs
2.2143f
62.8709f
62.8706f
2.2143f
32.0807f
25.4730f
cgd
2.2143f
2.2143f
2.2143f
2.2143f
1.2667f
25.4728f
Opening plot unit= 79
file=c:\work\test.tr0
***** job concluded
1 ******
Star-HSPICE -- 2001.4
(20011215) 16:53:22 02/01/2014
pcnt
******
rail_to_rail_comparator
******
job statistics summary
tnom=
25.000 temp=
******
total memory used
475 kbytes
3-61
25.000
# nodes =
51 # elements=
# diodes=
0 # bjts
analysis
24
=
0 # jfets
time
op point
transient
readin
errchk
setup
output
=
0 # mosfets =
18
# points tot. iter conv.iter
0.02
0.18
0.48
0.03
0.01
0.00
1
10001
29
4006
2003 rev=
0
total cpu time
0.75 seconds
job started at 16:53:22 02/01/2014
job ended at 16:53:23 02/01/2014
lic: Release hspicewin token(s)
For the convenience of discussion, we displayed the new comparator circuit below.
M13
M8
M7
M1
M9
M2
M17
M14
M18
M10
VOUT
INN
INP
M16
M5
M3
M6
M11
M12
M15
M4
From Table 3.10-2, we can see that M10 is turned off and M 9 is turned on.
We can also note that M 14 is turned off and M 13 is turned on. . That M 13 is
turned on will cause M17 to be on and M15 to have a reasonable gate voltage
equal to 0.649V. But, since M 14 is turned off and M18 is also turned off, VDS16
will be very low as illustrated in Fig. 3.10-4. This is proved to be true. From Table
3.10-2, we can see that VDS16  0.8m which is very low.
3-62
Experiment 3.10-3 The Second Analysis of the New Comparator with M9 and
M10 both on.
In the above experiment, M9 is on and M10 is cut off. There is current in M15
and no current in M16. In this experiment, both M9 and M10 are turned on.
Besides, there will be currents in both M15 and M16. But they are not equal. Note
that M15 and M16 form a current mirror pair. So, we have to figure out the value of
the output voltage.
In this experiment, we set INN  1.23 and INP  1.25. We can see that both
M9 and M10 will be turned on. Since INP  INN , we expect that Vout to be high.
The program is in Table 3.10-3 and the result is in Table 3.10-4.
Table 3.10-3
Program for Experiment 3.10-3
Rail_to_Rail_Comparator
.PROTECT
.OPTION POST
.lib "d:\model\tsmc\MIXED035\mm0355v.l" TT
.UNPROTECT
.op
M6
N1N322 N1N322 VSS VSS
NCH L=2U W=3U M=2
M3
N1N320 N1N320 VSS VSS
NCH L=2U W=3U M=2
M8
VVG I2U_S VDD VDD
PCH L=5U W=6U M=2
M1
N1N320 INN VVG VDD
PCH L=2U W=6U M=2
M2
N1N322 INP VVG VDD
PCH L=2U W=6U M=2
M7
I2U_S I2U_S VDD VDD
PCH L=5U W=6U M=2
M5
N1N365 N1N322 VSS VSS
NCH L=2U W=3U M=2
M4
N1N362 N1N320 VSS VSS
NCH L=2U W=3U M=2
M10
N1N362 INP N1N372 VSS
NCH L=2U W=3U M=2
M11
I2U I2U VSS VSS
M12
N1N372 I2U VSS VSS
M9
NCH L=5U W=5U M=2
NCH L=5U W=5U M=2
N1N365 INN N1N372 VSS
NCH L=2U W=3U M=2
M14
N1N362 N1N362 VDD VDD
PCH L=2U W=6U M=2
M13
N1N365 N1N365 VDD VDD
PCH L=2U W=6U M=2
M17
N1N431 N1N365 VDD VDD
PCH L=2U W=6U M=2
3-63
M18
VOUT N1N362 VDD VDD
PCH L=2U W=6U M=2
M15
N1N431 N1N431 VSS VSS
NCH L=2U W=3U M=2
M16
VOUT N1N431 VSS VSS
NCH L=2U W=3U M=2
vdd vdd gnd 1.5
vss vss gnd -1.5
v01 inn gnd 1.23
v02 inp gnd pwl(0 1.25 0.5m 1.25 1m 1.25)
i01 i2u_s vss 2u
i02 vdd i2u 2u
.tran 0.1u 1m
.probe v(VOUT)
.END
Table 3.10-4 Result of Experiment 3.10-3
subckt
element
model
region
id
ibs
ibd
0:m6
0:nch.1
0:m3
0:m8
0:nch.1
0:m1
0:pch.1
0:pch.1
0:m2
0:pch.1
0:m7
0:pch.1
Cutoff
Cutoff
Linear
Cutoff
Cutoff
20.3665p
27.3597p
-37.4396p
-16.5393p
-9.4663p
-3.553e-23 -4.761e-23
-9.2420f
7.488e-24
-9.2568f
7.885e-20
7.884e-20
7.885e-20
1.4467f
Saturati
-2.0000u
4.000e-19
1.3168f
1.1318f
vgs
136.4823m 146.4637m -883.4120m -269.9982m -249.9982m -883.4120m
vds
136.4823m 146.4637m
vbs
vth
vdsat
0.
0.
-1.7898u
-2.8535
-2.8635
-883.4120m
0.
1.7898u
1.7898u
0.
543.8987m 543.8851m -750.8104m -745.6720m -745.6333m -749.3364m
41.6323m
41.6328m -175.6604m
609.4467u 155.6720u
-47.7549m
-47.7542m -176.8155m
beta
609.4455u
380.1378u
380.1422u
155.7131u
gam eff
454.9563m 454.9563m 412.0847m 405.5279m 405.5279m 412.0847m
gm
597.8749p
802.4829p
232.4841p
461.8119p
264.9798p
gds
5.0595p
5.8219p
20.9219u
1.9351p
1.1099p
gmb
198.2757p
265.1281p
131.2395p
76.4010p
cdtot
9.0853f
9.0633f 232.7812f
11.6113f
11.5984f
cgtot
17.9555f
17.8851f 261.0278f
30.9014f
31.2499f 187.9781f
cstot
9.4240f
244.5662f
21.1723f
21.1723f
224.9787f
cbtot
31.3980f
31.3057f 102.9165f
54.8279f
55.1635f
94.9632f
9.4240f
57.3248p
3-64
20.7946u
55.4900n
4.9129u
15.9078f
cgs
1.2667f
1.2667f 126.5434f
2.2143f
2.2143f 161.4900f
cgd
1.2667f
1.2667f 126.5421f
2.2143f
2.2143f
2.2143f
0:m12
0:m9
subckt
element
model
region
id
ibs
0:m5
0:nch.1
0:m4
0:m10
0:nch.1
Cutoff
Cutoff
24.4179p
32.6435p
0:m11
0:nch.1
0:nch.1
Saturati
Saturati
1.2150u
-4.977e-23 -6.385e-23
0:nch.1
0:nch.1
Saturati
Saturati
2.0000u
2.0466u
-9.2878f -3.199e-18 -3.274e-18
-16.0858f
-14.9904f
vgs
136.4823m 146.4637m 962.8506m 608.7161m 608.7161m 942.8506m
2.2448
2.2207
vbs
0.
0.
vth
vdsat
-14.1098f
-9.2878f
ibd
vds
-9.2878f
831.6196n
-7.2861p
433.5150m 608.7161m
-1.7871
-9.2878f
1.7871
0.
457.6929m
0.
-1.7871
541.0283m 541.0612m 942.3986m 537.8483m 536.8336m 942.3659m
41.6324m
41.6329m
86.5622m 114.9326m 115.5846m
609.6822u 576.0724u
402.3561u
beta
609.6850u
gam eff
454.9563m 454.9563m 418.3443m 462.0946m 462.0946m 418.3443m
22.3626u
402.3935u
76.9069m
28.8390u
576.7799u
gm
716.6385p
957.2058p
gds
2.5381p
3.3164p
gmb
237.6224p
316.1995p
cdtot
7.1196f
7.1304f
7.1304f
13.1056f
11.5748f
7.1196f
cgtot
17.9555f
17.8851f
34.3782f
144.5955f
144.5954f
30.3227f
cstot
9.4240f
9.4240f
38.5898f 163.3203f
163.3201f
33.0862f
cbtot
29.4324f
29.3728f
85.4179f
83.8871f
21.2625f
62.7341n
42.2651n
4.0704u
21.3791f
29.3188u
16.3132u
40.5671n
8.6615u
44.3415n
8.8071u
2.9704u
cgs
1.2667f
1.2667f
27.8610f
112.9988f
112.9987f
23.1740f
cgd
1.2667f
1.2667f
1.2667f
2.0919f
2.0919f
1.2667f
subckt
element
model
region
id
0:m14
0:pch.1
Saturati
0:m13
0:m17
0:pch.1
0:pch.1
Saturati
Saturati
0:m18
0:pch.1
Saturati
-1.2150u -831.6554n -944.0701n
ibs
2.430e-19
1.663e-19
ibd
1.1318f
1.1318f
0:m15
1.888e-19
4.4359p
0:nch.1
Saturati
-1.1144u
0:m16
0:nch.1
Saturati
944.0821n
1.1122u
2.229e-19 -1.625e-18 -1.915e-18
1.1271f
-9.2878f
-2.2270n
vgs
-779.3356m -755.1576m -755.1576m -779.3356m 549.7193m 549.7193m
vds
-779.3356m -755.1576m
-2.4503
-140.7207m 549.7193m
3-65
2.8593
vbs
0.
0.
0.
0.
0.
0.
vth
-753.7202m -753.8136m -747.2371m -756.1978m 543.3375m 540.1934m
vdsat
-103.8531m
beta
375.8266u
gam eff
405.5279m 405.5279m 405.5279m 405.5279m
gm
gds
18.3972u
100.5750n
gmb
4.2936u
-91.3506m
-94.5463m -102.4894m
376.5760u 377.1212u
13.3282u
375.6311u
14.9116u
72.0932n
65.2785n
3.1335u
74.6185m
607.7514u
16.6440u
822.9689n
3.5027u
75.9963m
607.9492u
454.9562m 454.9561m
17.7910u
51.2357n
3.8885u
20.4097u
209.3923n
5.2414u
6.0184u
cdtot
16.3192f
16.4198f
12.1772f
19.9484f
8.3821f
6.8781f
cgtot
45.1908f
25.3103f
25.3103f
45.1912f
18.6641f
18.6635f
cstot
52.2239f
21.1723f
21.1723f
52.2245f
14.3984f
14.3975f
cbtot
55.1472f
54.0453f
49.8026f
58.7765f
28.7367f
27.2327f
cgs
26.5665f
2.2143f
2.2143f
26.5670f
4.9948f
4.9941f
cgd
2.2143f
2.2143f
2.2143f
2.2143f
1.2667f
1.2667f
Again we display the comparator circuit in below for the convenience of discussion.
M13
M8
M7
M1
M9
M2
M17
M14
M18
M10
VOUT
INN
INP
M16
M5
M3
M6
M11
M12
M15
M4
Since both INN and INP are quite high, they turn on both M9 and M10. As
seen in Table 3.10-4, both M9 and M10 are in saturation condition. This makes both
M13 and M14 in saturation condition. Since INN  1.23 and INP  1.25 ,
INP  INN . Therefore, I ( M 14)  I ( M 13) . Because of the current pair effect,
I ( M 18)  I ( M 17) . This makes I ( M 16)  I ( M 15) . But, M15 and M16 are a
current mirror pair. . This further means that M16 will have a large V DS . From
VDS16  2.86
Table
3.10-4.
we
can
see
that
.
Thus
Vout  Vd 16  1.5V  2.86V  1.36V which is high and correct because INP  INN .
3-66
Experiment 3.10-4 The Third Experiment of the New Comparator with Both
M9 and M10 both off.
In this experiment, INN  1.2V and INP  1.25V . As can be seen, both
input voltages are low and both M 9 and M10 are turned off. Yet INP  INN .
Therefore, we expect Vout to be low.
The program is in Table 3.10-5 and the result is in Table 3.10-6.
Table 3.10-5 Program for Experiment 3.10-4
Rail_to_Rail_Comparator
.PROTECT
.OPTION POST
.lib “d:\model\tsmc\MIXED035\mm0355v.l” TT
.UNPROTECT
.op
M6
N1N322 N1N322 VSS VSS
NCH L=2U W=3U M=2
M3
N1N320 N1N320 VSS VSS
NCH L=2U W=3U M=2
M8
VVG I2U_S VDD VDD
PCH L=5U W=6U M=2
M1
N1N320 INN VVG VDD
PCH L=2U W=6U M=2
M2
N1N322 INP VVG VDD
PCH L=2U W=6U M=2
M7
I2U_S I2U_S VDD VDD
PCH L=5U W=6U M=2
M5
N1N365 N1N322 VSS VSS
NCH L=2U W=3U M=2
M4
N1N362 N1N320 VSS VSS
NCH L=2U W=3U M=2
M10
N1N362 INP N1N372 VSS
NCH L=2U W=3U M=2
M11
I2U I2U VSS VSS
M12
N1N372 I2U VSS VSS
M9
NCH L=5U W=5U M=2
NCH L=5U W=5U M=2
N1N365 INN N1N372 VSS
NCH L=2U W=3U M=2
M14
N1N362 N1N362 VDD VDD
PCH L=2U W=6U M=2
M13
N1N365 N1N365 VDD VDD
PCH L=2U W=6U M=2
M17
N1N431 N1N365 VDD VDD
PCH L=2U W=6U M=2
M18
VOUT N1N362 VDD VDD
PCH L=2U W=6U M=2
M15
N1N431 N1N431 VSS VSS
NCH L=2U W=3U M=2
M16
VOUT N1N431 VSS VSS
NCH L=2U W=3U M=2
3-67
vdd vdd gnd 1.5
vss vss gnd -1.5
v01 inn gnd -1.2
v02 inp gnd pwl(0 -1.25 0.5m -1.25 1m -1.25)
i01 i2u_s vss 2u
i02 vdd i2u 2u
.tran 0.1u 1m
.probe v(VOUT)
.END
Table 3.10-6
The Result of Experiment 3.10-4
subckt
element
model
region
id
ibs
ibd
0:m6
0:m3
0:nch.1
0:m8
0:nch.1
Saturati
1.4269u
Cutoff
0:pch.1
Saturati
612.5813n
-2.456e-18 -1.055e-18
-9.2878f
0:pch.1
0:m1
Cutoff
4.079e-19
-9.2878f
vds
572.3731m 527.5418m
vth
vdsat
Saturati
0.
-1.4269u
1.1318f
-1.6784
1.1318f
-1.0716
-883.4120m
1.6784
1.6784
-1.0235
-1.0237
0.
-749.3364m
-88.3247m -117.3678m -176.8155m
beta
607.1749u
gam eff
454.9561m 454.9562m 412.0847m 407.9415m 407.9415m 412.0847m
gm
gds
gmb
24.9772u
71.0035n
7.3410u
608.2183u 155.7500u
4.000e-19
-794.0722m -749.2409m -883.4120m
0.
65.8550m -177.8653m
-2.0000u
1.1318f
-1.0216
543.3073m 543.3672m -748.0081m
85.3051m
Saturati
1.1318f
572.3731m 527.5418m -883.4120m
0.
0:pch.1
1.1318f
32.0797f
0:m7
0:pch.1
-2.0395u -612.5769n
vgs
vbs
0:m2
12.2686u
35.9353n
cdtot
8.3525f
cgtot
27.6282f
cstot
29.6055f
9.4240f
cbtot
29.5114f
28.5713f
cgs
16.3993f
cgd
1.2667f
8.4118f
21.1053u
46.0825n
3.6233u
345.9420u
344.2817u
11.0512u
54.0013n
4.9862u
155.7131u
22.5051u
116.7956n
1.4621u
20.7946u
55.4900n
2.9397u
4.9129u
13.6010f
12.1435f
12.2119f
15.8023f 187.9780f
18.0203f
52.7873f 187.9781f
224.9786f
13.6010f
58.5044f
224.9787f
92.6564f
34.9076f
35.5964f
94.9632f
1.2667f 161.4899f
2.2143f
1.2667f
2.2143f
2.2143f
3-68
15.9078f
41.4400f 161.4900f
2.2143f
2.2143f
subckt
element
model
region
id
0:m5
0:m4
0:nch.1
0:nch.1
Saturati
0:m10
0:nch.1
Cutoff
1.5441u
0:m11
0:nch.1
Cutoff
0:m12
0:nch.1
Saturati
676.7954n 662.1709p
0:m9
0:nch.1
Linear
2.0000u
Cutoff
3.3861n
2.7150n
ibs
-2.658e-18 -1.165e-18 -3.861e-17 -3.199e-18 -5.417e-21 -3.861e-17
ibd
-238.2998p -149.0853p -173.1472f
vgs
572.3731m 527.5418m 249.8930m 608.7161m 608.7161m 299.8930m
vds
2.2044
2.2574
vbs
0.
0.
vth
vdsat
-14.1098f -5.864e-17 -531.4258f
2.2573
608.7161m 107.0099u
-107.0099u
0.
0.
2.2043
-107.0099u
541.0855m 541.0122m 541.0432m 537.8483m 538.3706m 541.1153m
86.4417m
66.7030m
41.6697m 114.9326m 114.6016m
beta
607.3074u
gam eff
454.9561m 454.9562m 454.9533m 462.0946m 462.0947m 454.9533m
gm
gds
gmb
608.3750u 609.6824u
26.5428u
99.3345n
13.3367u
53.4127n
7.8053u
402.3561u
18.9907n
69.0381p
3.9412u
402.3366u
41.7883m
28.8390u
42.2651n
6.0328n
8.6615u
609.6703u
31.5634n
31.6327u
75.7517n
266.2652p
9.7016n
23.6264n
cdtot
7.1377f
7.1141f
7.1141f
13.1056f
167.1387f
7.1377f
cgtot
27.6280f
15.8023f
17.2131f
144.5955f
194.5720f
16.9216f
cstot
29.6051f
9.4240f
9.4237f 163.3203f
176.9682f
9.4237f
cbtot
28.2966f
27.2736f
89.6365f
28.4163f
28.6841f
85.4179f
cgs
16.3990f
1.2667f
1.2667f
112.9988f
89.3943f
1.2667f
cgd
1.2667f
1.2667f
1.2667f
2.0919f
89.2912f
1.2667f
0:m15
0:m16
subckt
element
model
region
0:m14
0:pch.1
Cutoff
0:m13
0:pch.1
Saturati
id
-677.6219n
-1.5471u
ibs
1.355e-19
3.094e-19
ibd
1.1318f
1.1318f
0:m17
0:pch.1
0:m18
0:pch.1
Saturati
0:nch.1
Cutoff
Saturati
-1.7287u -800.9205n
3.457e-19
0:nch.1
Linear
1.7287u 800.9508n
1.602e-19 -2.976e-18 -1.379e-18
6.5751p
18.5384p
-9.2878f
-6.2942f
vgs
-742.6043m -795.5597m -795.5597m -742.6043m 583.5252m 583.5252m
vds
-742.6043m -795.5597m
vbs
vth
0.
0.
-2.4165
-2.9709
0.
0.
583.5252m
0.
29.0923m
0.
-753.8622m -753.6576m -747.3691m -745.2171m 543.2925m 544.0460m
vdsat
-85.6282m -113.3005m -117.1631m
-89.4961m
91.1744m
beta
376.9182u
377.6553u
606.8550u
gam eff
405.5279m 405.5279m 405.5279m 405.5279m 454.9561m 454.9562m
375.2592u 375.7309u
3-69
90.7688m
606.8108u
gm
gds
11.1316u
22.4021u
24.5703u
59.9847n 123.6645n 108.5950n
gmb
2.6268u
5.2030u
12.9311u
29.0643u
55.6181n
5.7022u
82.2642n
3.0483u
10.2253u
22.0000u
8.5324u
3.0453u
cdtot
16.4729f
16.2527f
12.2292f
11.4632f
8.3381f
17.5648f
cgtot
25.4104f
54.8434f
54.8429f
25.4104f
30.7551f
34.5483f
cstot
21.1723f
67.2908f
67.2900f
21.1723f
34.9100f
34.8575f
cbtot
54.1985f
55.6586f
51.6350f
49.1887f
29.7736f
30.9459f
cgs
2.2143f
38.3946f
38.3940f
2.2143f
20.3813f
20.4770f
cgd
2.2143f
2.2143f
2.2143f
2.2143f
1.2667f
5.9859f
Again we display the comparator circuit in below for the convenience of
discussion.
M13
M8
M7
M1
M9
M2
M17
M14
M18
M10
VOUT
INN
INP
M16
M5
M3
M6
M11
M12
M15
M4
Since INN  1.2V and INP  1.25V , they are both low and thus both M9
and M10 are turned off. Note that INP  INN and both M1 and M2 are PMOS
transistors, one of them will be turned on. From Table 3.10-6, we can see that M2 is
turned on and M1 is turned off. Since M2 is on, M6 has current which makes M5
have current. The current of M5 is supplied by M13. Therefore, M13 has current
while M14 is cutoff. This makes M17 have current and M18 cutoff. Thus, M15
has current and M16 has no current. Since M15 and M16 are a current mirror pair,
M16 is forced to be in linear mode and VDS16  0.03V which is very small. Finally,
Vout  1.5V  VDS16  1.5V  0.03V  1.47V which is low as expected because
INP  1.25V  INN  1.2V .
Constant Current Source
3-70
In the comparator, we need two constant current sources, one from a PMOS
transistor and one from an NMOS transistor. Fig. 3.10-7 presents such a circuit.
The currents can be identical if the loads are identical or the IV-curves are absolutely
flat.
VDD
MPO
MP1
R
IP
I1
N1
MN1
Fig.3.10-7
IN
I2
MN 2
MNO
A constant current source which produces currents flowing out from a
PMOS transistor an current flowing out from an NMOS transistor
The circuit in Fig. 3.10-7 is easy to understand. We have to understand that
MP1 is load of MN2. The circuit works only when the IV-curve of MN2 matches
with the IV-curve of MP1 as shown in Fig. 3.10-8. If the IV-curve of MP1 is too low
or too high, the circuit will not work as I1 will not be equal to I2.
IMN2
IV curve of MN2
IV curve of MP1
VDSMN2
Fig. 3.10-8 A good matching of the IV curves of MN2 and MP1
Note that there is no bias voltage in the circuit.
3-71
The only parameter which we
can use to adjust the location of an IV curve is the parameter W/L of the gate. A
smaller W/L of MP1 will lower its IV-curve. It is easy to see that if the IV-curve of
MP1 is too low, MN2 will be in the triode region. The circuit will not work in this
case. If W/L of the gate of MP1 is large, it will not be ideal. But the situation will
not be too bad.
Experiment 3-10-5
A Testing of W / L of the gate of MP1 in Fig. 3.10-7.
In the first test, for NMOs, W=5u and L=0.35u.
The program is in Table 3.10-7.
For PMOS, W=17.4u and L=0.35u.
.Table 3.10-7 The program for Experiment 3.10-5
protect
.lib 'mm0355v.l' TT
.unprotect
.op
.options nomod post
**source**
VDD VDD 0 1.8
R VDD N1 10k
MN1 N1 N1 0 0 nch W=5u L=0.35u
MN2 P1 N1 0 0 nch W=5u L=0.35u
MP1 P1 P1 VDD VDD pch W=17.4u L=0.35u
MNO N N1 0 0 nch W=5u L=0.35u
MPO P P1 VDD VDD pch W=17.4u L=0.35u
VP P 0 829.5532m
VN N 0 829.5643m
.print I(MNO)
.end
Table 3.10-8 shows the result.
perfectly.
As seen in Table 3.10-8, the circuit works
3-72
Table 3.10-8 The result of W equal to 17.4u for PM1
We then change W=0.5u for PM1. The result is shown in Table 3.10-9.
can that the circuit is not working at all. Ip is not equal to IN
3-73
We
Table 3.10-9 The result of W equal to 0.5u for PM1
We then enlarge W to 100u. The result is shown in Table 3.10-10. The circuit
is not working.
But the situation is not that bad.
3-74
Table 3.10-10 The result of W equal to 100u for PM1
Experiment 3.10-11
M16
An Experiment to Show the Flatness of the IV-curve of
As we indicated before, the rail to rail comparator works because of one important
characteristics of the circuit: The current must be small and as indicated in Fig.
3.10-4, the IV-curve of M16 must be quite flat. This experiment confirms this. The
program is shown in Table.3.10-11 and the result is in Fig. 3.10-9. We can see that
the IV-curve is indeed very flat.. It changes only for 0.2  which is very small.
The current is so small because the length of the transistor is very long, 2  .
Table 3.10-11 The program for Experiment 3.10-6
0505
.protect
.lib ‘C:\mm0355v.l’ TT
.unprotect
.op
3-75
.options nomod post
VDD
R1
1
1
0
3.3v
2
M1 2
3
0
0
V2
VGS1
2
3
0
0
0.549v
280k
NCH L=2U W=3U M=2
0v
.DC V2 0 3.3v 0.1v
.PROBE I(R1) I(M1)
.end
Fig. 3.10-9
An IV-curve of M16
3-76