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ISSN 2322-0929 Vol.04, Issue.10, October-2016, Pages:1066-1069 www.ijvdcs.org High Speed Low Power MTCMOS D-Latch Based 32-Bit Carry Select Adder using 10-T Full Adder SAMBARAJU SNEHA1, P.KALYANI2, DR. D.NAGESHWAR RAO3 1 2 PG Scholar, Dept of ECE, TKR College of Engineering, Hyderabad, India. Assistant Professor, Dept of ECE, TKR College of Engineering, Hyderabad, India. 2 Professor, Dept of ECE, TKR College of Engineering, Hyderabad, India. Abstract: The market demand and efficient portable electronic equipment have pushed the industry to produce circuit designs operating at low voltage and for low power consumption. Power consumption in digital systems is an Important issue in nanoscale technologies. Area and power reduction in data path logic systems are main area of research in VLSI system. The high speed adders are always been the fundamental requirement for high performance processes and systems. In this paper we propose the use of power reduction technique MTCMOS D-latch and area efficient fulladder in evaluating the 8-bit, 16-bit and 32-bit carry select adder. . Overall 33% of power is reduced and 14% of delay is reduced by using MTCMOS D-Latch CSLA when compared to the conventional D-Latch CSLA. Keywords: RCA, CSLA, BEC, MTCMOS D-latch. I. INTRODUCTION The main objective in designing the high speed processing systems is to reduce the propagation delay in adders. Ripple Carry Adder (RCA) which is the complex adder having less area and more delay, where as the Carry Look Ahead Adder (CLA) which is designed to overcome the propagation delay in RCA has more area[1]. Carry Select Adder(CSLA) is proposed which is having the compromised architecture which satisfies the criteria of less delay and less area. Therefore CSLA is used in many processing systems for faster applications. II. CARRY SELECT ADDER (CSLA) The carry-select adder[2] generally consists of two ripple carry adders and a multiplexer. Adding two n-bit numbers with a carry-select adder is done with two adders (therefore two ripple carry adders) in order to perform the calculation twice, one time with the assumption of the carry-in being zero and the other assuming it will be one. Fig.1. Basic Carry Select Adder. After the two results are calculated, the correct sum, as well as the correct carry-out, is then selected with the multiplexer once the correct carry-in is known. But when the large number of bits are considered the usage of more number of RCA’s results in large delay, therefore for Cin=1 the RCA is replaced with the Binary to Excess -1(BEC) minimizes the area and power. III. BINARY TO EXCESS-1 CONVERTER The basic idea to use Binary to Excess-1converter [3] instead of RCA with Cin=1 in regular CSLA is to achieve lower area and power consumption and as well as lesser delay when compared to conventional one. The main advantage of the BEC logic comes from lesser number of logic gates than the n-bit Fulladder. Fig.2. Regular Binary to Excess -1 Converter. Copyright @ 2016 IJVDCS. All rights reserved. SAMBARAJU SNEHA, P.KALYANI, DR. D.NAGESHWAR RAO leakage currents in low voltage circuits in the stand by mode III. 8-BIT CSLA USING BEC-1 CONVERTER This 8-bit CSLA using BEC structure[4] is again divided with the use of two different threshold voltages(Vt) as sleep sections of different bit size RCAs and BECs. One input to the transistors in the circuit. High Vt transistors are connected multiplexer goes from the RCA with Cin=0 and other input near the power rails i.e. Vdd and Ground. During active mode, from the BEC. the high threshold Vt transistors are turned on, thereby normal operation of circuit and exists direct path from Vdd and ground. During Stand-by-mode, the transistors are turned off creating virtual power supply and ground rail and cutting off the circuit from supply. Fig.3 8-bit CSLA using BEC-1 Converter. Even though there is a reduction in area and power still there is a slight increase in delay when compared to the regular CSLA[5]. The increasing size of multiplexers results in increase in delay. To overcome this, the BEC or RCA is replaced with D-Latch in order to reduce delay and to have high speed. IV. D-LATCH Latch is an electronic device that can be used to store one bit of information. The D latch is used to capture, or 'latch' the logic level which is present on the Data line when the Clock/Enable input is high. If the data on the D line changes state while the Clock/Enable pulse is high, then the output, Q, follows the input, D. When the Clock/Enable input falls to logic 0, the last state of the D input is trapped and held in the latch. Fig.5.MTCMOS D-Latch. V. 10-TRANSISTOR FULLADDER The Full adder cell uses 28 transistor based on regular CMOS structure (pull-up and pull-down networks). Complementary transistor pairs make the circuit layout straight forward. CCMOS generates carry through a static gate. The advantage of using CCMOS is that it has layout regularity, high noise margins and stability at low voltage due to complementary transistor pair and smaller number of interconnecting wires and disadvantage is that it uses Cout signal to generate sum which produces an unwanted additional delay. It has weak o/p driving capability due to series transistors in output stage and consumes more power and large silicon area. Therefore the adder is replaced with 10 transistor fulladder[8] which results in less area and low power dissipation. VI. 8-BIT MTCMOS DLATCH CSLA The 8 bit MTCMOS D-Latch[4] based Carry Select Adder s designed in order to reduce the delay. Fig4. D-Latch. V. D-LATCH USING POWER REDUCTION TECHNIQUE - MTCMOS As technology scaling continues to push transistors to smaller and smaller sizes, leakage power has become a significant portion of total power dissipation in ICs. The two major types of power dissipation are Dynamic and Static power dissipation. Dynamic power dissipation is observed during active mode and Static power dissipation is observed during stand-by-mode.Multiple Threshold CMOS (MTCMOS) [4][6][7] circuit techniques are applied for reducing the Fig6. 8-Bit MTCMOS D Latch CSLA. International Journal of VLSI System Design and Communication Systems Volume.04, IssueNo.10, October-2016, Pages: 1066-1069 High Speed Low Power MTCMOS D-Latch Based 32-Bit Carry Select Adder using 10-T Full Adder The power reduction technique MTCMOS which is applied MTCMOS D-Latch CSLA when compared to the conventional for the D-Latch block plays important role in the reduction of D-Latch CSLA. power when compared with the conventional 8 Bit D-Latch IX. REFERENCES CSLA design. The Fulladder which was replaced with 10 [1] R.Uma, Vidya Vijayan, M.Mohanapriya, and Sharon Paul, transistor also results in reduction of area as the transistor Area, Delay and Power Comparison of Adder Topologies, count gets decreased. International Journal of VLSI Design & Communication Systems, vol.3, no.1, pp.153-168,Feb2012. [2] International Journal of Scientific and Research Table1. Comparative Analysis of 8 bit CSLA using BEC, Publications, Volume 3, Issue 8, August 2013 1 ISSN 2250D-Latch, MTCMOS D-Latch 3153 www.ijsrp.org Low-Power and High Speed Carry SelectAdderLaxman Shanigarapu*, Bhavana P. Shrivastava**. [3] International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering(An ISO 3297: 2007 Certified Organization)Vol. 4, Issue 1, January 2015.A Low Power Binary to Excess-1 Code Converter. [4] International Conference on Electrical, Electronics, Signals, Communication and Optimization (EESCO) – 2015 VII. PROPOSED STRUCTURE 978-1-4799-7678-2/15/$31.00 ©2015 IEEE High Speed In this proposed structure, we explore a 32-bit MTCMOS Square Root Carry Select Adder Using MTCMOS D-Latch in D-Latch based Carry Select Adder using 10Transistor Full 45nm Technology 1Adyasha Das , 2Sushanta K. Mandal , adder s designed and related results are calculated. 3Jitendra K. Das’ [5] International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue 9- Sep 2013 ISSN: 2231-5381 http://www.ijettjournal.org Page 3766 An Efficient Carry Select Adder with Less Delay and Reduced Area Application. [6] International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169 Volume: 3 Issue: 2 554 - 558 554 IJRITCC | February 2015, Available @ http://www.ijritcc.org A Literature Review on Leakage and Power Reduction Techniques in CMOS VLSI Design [7] Volume 3, Issue 5, May 2013 ISSN: 2277 128X International Journal of Advanced Research in Computer Fig7. Science and Software Engineering Research Paper .A New Approach For Leakage Power Reduction Techniques In Deep Table2. Results of 32-bit MTCMOS D-Latch based CSLA Submicron Technologies In Cmos Circuit For Vlsi Applications . Hina Malviya* Sudha Nayar C.M Roy ,Rkdf Bhopal, India. Rkdf Bhopal, India. Manit Bhopal, India. [8] Low Power CMOS VLSI Design. Digtal Electronics. Table3. Analysis of 8-bit, 16-bit and 32-bit MTCMOS K.Roy D-Latch based CSLA Design Total Static Delay Author’s Profile: Power Power S.Sneha received B.Tech degree in Electronics 3.82nW 0.541nW 1.80ns 8-Bit and Communication Engineering from Bharath 9.36nW 1.07nW 2.00ns 16-Bit Institute of Technology and Sciences for 19.98nW 2.099nW 2.44ns Women in 2014, and currently pursuing 32-Bit M.Tech in VLSI-SD from TKRCET VIII. CONCLUSION Hyderabad. Power, delay and area are the constituent factors in vlsi design that limit the performance of any circuit. This work P.Kalyani received her B.Tech in Electronics presents a simple approach to reduce the area, delay and power and communication Engineering from Scient of CSLA architecture. The conventional CSLA has the Institute of Engineering and technology, in disadvantage of more power consumption and occupying more 2007 and M.Tech in VLSI system Design chip area. All the three models of CSLA are designed and from CVR college of Engineering, in 2010. implemented in Cadence tool and their results are compared in She is currently pursuing the Ph.D. degree terms of power and delay. The CSLA with MTCMOS D-Latch with the Jawaharlal Nehru Technological University, proves to be the High speed and Low power CSLA. Overall Hyderabad, India. She currently serves as an Assistant 33% of power is reduced and 14% of delay is reduced by using Professor in ECE department, at TKR college of Engineering International Journal of VLSI System Design and Communication Systems Volume.04, IssueNo.10, October-2016, Pages: 1066-1069 SAMBARAJU SNEHA, P.KALYANI, DR. D.NAGESHWAR RAO and Technology, Hyderabad. She has 8 years of teaching experience in the field of Academic. Her research interests include VLSI design, Low power VLSI, Power reduction techniques and Leakage power reduction. Dr.D.Nageshwar Rao HOD,ECE, He is a distinguished academician with 13years of teaching experience. He pursued Masters from JNTU Hyderabad and Ph.D in VLSI from GITAM University, Vishakhapatnam. He published several research papers in National and International journals. He has guided and also presently guiding several projects at graduate and post graduate levels. He attended as well as organized several workshops and seminars. He is also been invited as guest lecturer and resource person for various reputed institutions. He has been awarded “Certificate of Merit” in NIET for two consecutive years of 2007 and 2008. International Journal of VLSI System Design and Communication Systems Volume.04, IssueNo.10, October-2016, Pages: 1066-1069