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Transcript
A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler Abstract A high-speed CMOS TSPC divide-by-16/17 dual modulus prescaler is proposed. The speed of the prescaler is improved in two aspects. First, by adopting a new pseudo divide-by-2/3 prescaler, the minimum working period is effectively reduced by half a NOR gate's delay. Second, by changing the connection of TSPC D-Flip-Flops, the minimum working period is further reduced by half an inverter's delay. Simulation results show that the maximum operating frequency of the proposed circuit is improved by ~40% compared with conventional circuit. Fabricated in 0.18-μm CMOS process, the proposed circuit is capable of operating up to 5.8 GHz. The power consumption is 2.6 mW at the maximum operating frequency under 1.6 V supply voltage.
