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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 6, JUNE 2001
A 1.25-GHz 0.35-m Monolithic CMOS PLL
Based on a Multiphase Ring Oscillator
Lizhong Sun and Tadeusz A. Kwasniewski, Member, IEEE
Abstract—A general ring oscillator topology for multiphase outputs is presented and analyzed. The topology uses the interpolating
inverter stages to construct fast subfeedback loops for long chain
rings to obtain both multiphase outputs and higher speed operation. There exists an optimum number of inverter stages inside a
subfeedback loop which gives the highest oscillation frequency. A
fully integrated 1.25-GHz 0.35- m CMOS phase-locked-loop clock
generator that incorporates the proposed voltage-controlled oscillator topology was designed and implemented for a data transceiver. It provides eight-phase outputs and achieves RMS tracking
jitter of 11 ps from a 3.3-V power supply.
Fig. 1. Simplified block diagram of a data transceiver.
Index Terms—Analog integrated circuits, clock generation, frequency synthesizer, phase-locked loop.
I. INTRODUCTION
T
HE phenomenal growth in information transport has
created greater demand for very high-speed integrated
circuits. Important components for the high-capacity networks
include transceivers which incorporate clock generators,
clock/data recovery circuits (CDR), multiplexers (MUX)/demultiplexers (DMUX) and I/O buffers. Fig. 1 shows the
simplified block diagram of a data transceiver. In the transmitter, the MUX converts the internal byte-wide (parallel) data
stream to a bit serial stream and drives a high-speed output
buffer. In the receiver, the clock recovery circuit regenerates the
clock and defines the best time to sample the data in terms of
the received signal-to-noise ratio. Data is then demultiplexed.
The multiphase outputs from the phase-locked loop (PLL) and
CDR for MUX/DMUX allow the voltage-controlled oscillator
(VCO) to operate at the relative lower parallel data stream
rate instead of the much higher bit serial stream rate. For
example, eight-phase 1.25-GHz clocks can be used to recover
a serial data at 10 Gb/s for SONET systems. It has advantages
including larger VCO jitter tolerance and ease of circuit design
in a low-cost digital CMOS process instead of a Si bipolar or
GaAs MESFET process.
This paper presents a general ring oscillator topology for multiphase output and high-speed oscillation. A 0.35- m CMOS
PLL clock generator that incorporated the proposed VCO
topology is designed to operate at 1.25 GHz with eight-phase
outputs. The functional block diagram is shown in Fig. 2. The
PLL includes a phase and frequency detector (PFD), charge
pump, loop filter, VCO, and prescaler/divider. The output
Manuscript received June 7, 2000; revised January 9, 2001. This work was
supported by NSERC and CITO in Canada.
L. Sun is with Lucent Technologies, Bell Labs, Allentown, PA 18103 USA.
T. Kwasniewski is with the Department of Electronics, Carleton University,
Ottawa, ON K1S 5B6, Canada.
Publisher Item Identifier S 0018-9200(01)04133-6.
Fig. 2. Functional block diagram of the PLL clock generator.
clock frequency (1244.16 MHz) can be synthesized from a
77.76 or 19.44 MHz reference clock with a corresponding
feedback divider ratio of 8 or 32. Design considerations include
low-voltage operation, low power consumption, monolithic
integration, low timing jitter, and good process/temperature
variation tolerance.
In the next section of this paper, a general ring oscillator
topology for high-speed operation and multiphase outputs
is presented and analyzed. Section III describes a four-stage
(eight-phase) subfeedback-loop-based differential ring oscillator. The PLL design and measurement results are presented
in Section IV. Concluding remarks follow in Section V.
II. MULTIPHASE OUTPUT RING OSCILLATORS
The VCO is a critical building block in PLLs. High-frequency and RF voltage/current controlled oscillators can be
implemented monolithically as LC oscillators, relaxation oscillators or ring oscillators. Although ring oscillators have poor
phase noise characteristics compared to high- LC oscillators,
they have the advantage of wider oscillation frequency range
and a smaller die size. Ring oscillators are particularly attractive
for multiphase clock signal generation required by many clock
recovery circuits and high-speed sampling systems [1], [2].
For an -stage ring oscillator, the oscillation period of the
, where is the delay of each inverter stage. The
ring is
minimum delay of each stage depends on the circuit structure,
process parameters, and the size of transistors. The size of transistors affects the delay through its effect on driving strength,
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SUN AND KWASNIEWSKI: MONOLITHIC CMOS PLL BASED ON A MULTIPHASE RING OSCILLATOR
911
Fig. 3. General topology of ring oscillator with subfeedback loops.
Fig. 5. Block diagram of a five-stage ring oscillator with subfeedback loops
(i
x
3 case).
= =
Fig. 4.
Redraw of Fig. 3 demonstrating the feedforward paths.
self-loading, and loading to the previous stage. The improvement in speed can be obtained by a circuit optimization. However, the achievable improvement in speed is limited, especially
for an oscillator with a long chain of inverters. To solve the conflict between speed (or tap-to-tap delay) and multiphase output,
several techniques have been proposed [3]–[6]. A VCO based
on two-taps delay interpolating was proposed to provide largerange tuning without providing uniform tap-to-tap delay [3]. In
[4], a two-dimensional coupled ring oscillator was developed to
produce precise delays with subgate-delay resolution. Recently,
a multiple-feedback-loop ring architecture was used for a threestage and four-stage ring oscillator design [5]. A single-ended
multiphase ring oscillator was proposed using a negative skew
delay scheme, suggesting an optimum skew delay of two inverter delays [6]. However, as will be shown later, the two-inverter skew delay is not always the optimum for long-chain ring
oscillators.
Fig. 6.
Combined single-stage equivalent circuit.
of major loop inverters
that the interpolating inverters
pass over. The topologies of Figs. 3 and 4 are equivalent. The
.
relation between and is
The block diagram of a five-stage single-ended ring oscillator
is shown in Fig. 5 as an example of the topology for the
(or
) case. The circuit contains a single
slow loop and five subfeedback fast loops. Each subfeedback
loop contains three inverter stages. Equivalently, the circuit can
also be understood as a scheme where the delay of stages is the
weighted sum of the delay through the slow path and the fast
to node
is the
path. For example, the delay from node
and
weighted sum of the slow path delay
the fast path delay .
B. Model of Oscillation
A. A General Topology of Multiphase Ring Oscillators
Fig. 3 shows a general topology of multiphase ring oscillators with subfeedback loops [7]. The nodes and their interconnections have been correspondingly labeled. The fundamental
interidea is to use the interpolating inverters to construct
coupled subfeedback loops. Each subfeedback loop contains an
optimum number of inverters that keeps the circuit reliably oscillating at a higher speed. The phase relationship between inverter stages remains unchanged due to the symmetrical structure. Thus, reduced tap-to-tap delay can be achieved. We define
as the feedback index. It is an integer
representing the number of inverter stages in each subfeedback loop
, there are three inverters in a subfeedback
(e.g., when
can be incorporated into
loop). The interpolating inverter
circuitry with a separate input. The
the major loop inverter
topology in Fig. 3 can be redrawn in Fig. 4 where the interpolating inverters are used to construct the fast paths (short cuts).
We define as the feed-forward index in contrast to the feedback
representing the number
index . It is an integer
For an -stage ring oscillator in a stable oscillation mode,
there exists a fixed phase relation between stages. Each stage
for a total
, where
contributes a phase delay of
is an odd integer with value smaller than
. It represents a
possible mode of oscillation. Another phase inversion required
around the loop is
for the total phase shift of multiple of
provided by phase inversion in each inverter stage. For the differential ring oscillators with even number of stages, the phase
inversion required for the total phase shift of a multiple of
around the loop can be achieved by simply interchanging the
differential outputs of the last inverter before feeding them back
to the inputs.
To find the optimum feedback index for a long-chain ring
and the relative frequency variation, we model the signal path
in the VCO with a first-order approximation, assuming its oscillation amplitude remains small and the waveform is sinusoidal-like. Fig. 6 shows a combined single-stage equivalent cirand
represent the equivalent output resiscuit diagram.
,
tance and the total parasitic loading capacitance at node
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 6, JUNE 2001
respectively.
and
represent the equivalent transconductance of the inverters in the main loop and subfeedback loop,
respectively. We define as the phase difference between two
, for
and
) and
adjacent nodes (e.g.,
as the phase difference between node
and node
. Assuming all stages are the same, we have
. Thus, the transfer function
of
a single stage can be found as
(1)
According to the Barkhausen criterion of oscillation [8], the
ring oscillator would oscillate if the loop has unity voltage
or a multiple of . Although there
gain and phase shift of
may exist some possible modes for long-chain ring, only those
modes with enough loop gain can sustain oscillation. Since we
want single-mode operation, loop gain should be designed to
be smaller than one for all the undesired modes. From (1), the
minimum required gain of each stage can be written as
(2)
Fig. 7. Seven-stage ring oscillator transient waveforms for different feedback
index i.
and the approximate oscillation frequency can be expressed as
C. Increasing the Oscillation Frequency
(3)
where
(4)
The first term of (3) is the oscillation frequency of a conventional ring oscillator. The second term corresponds to the
frequency increment or decrement. Considering that an oscillator is a large signal nonlinear system, as the amplitude grows,
transconductance degrades; furthermore, output resistance and
capacitance deviate from their value near the quiescent biasing
point. Equation (3) actually overestimates the real oscillation
frequency. However, we are more interested in comparing the
relative frequency improvement between different topologies
rather than calculating the absolute oscillation frequency. Equation (3) can be used to qualitatively estimate the relative frequency increase/decrease ( ) compared to the conventional
ring topology. We have
(5)
are the total loading capacitance of each stage
where and
for the subfeedback based topology and the conventional single
represents the avloop topology, respectively.
is the operating
erage strength of the interpolating inverters.
frequency for the conventional single loop topology. We have
assumed that remains the same.
To achieve a large relative frequency increment, the interpolating inverters should be introduced without a significant increase of the loading capacitance. Furthermore, in (4) should
be positive. Since is fixed for an -stage ring oscillator during
stable oscillation, whether oscillation frequency is increased or
decreased depends on the feedback index , which is the number
of inverters in a subfeedback loop. The subfeedback loop can
) or odd (
) number
contain an even (
of inverters. An odd number of inverters inside a subfeedback
value, thus increases the operating freloop has a positive
) causes a decrease in
quency, while an even number (
the operating frequency. For a long-chain ring, there exists an
optimum feedback index which gives the highest operating frequency. This can be easily confirmed with HSPICE large-signal
transient simulations.
A simple single-ended inverter was used as a delay stage in
the large-signal simulations. The device sizes of inverters in
) and 10 m/0.6 m
the major loop are 30 m/0.6 m (
for pMOS and nMOS, respectively, while the device sizes
of the interpolating inverters are 15 m/0.6 m (pMOS) and
5 m/0.6 m (nMOS), respectively. The simulations were run
with 0.5 m digital CMOS process parameters and a power
. Fig. 7 shows the
supply of 3.3 V for
corresponding to different
oscillation waveforms for
values. When the subfeedback loop contains three (
)
) inverters,
, and the frequency is inor five (
creased compared to a conventional seven-stage single-loop
ring oscillator. However, when the subfeedback loop contains
) or six (
) inverters, frequency is decreased
four (
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SUN AND KWASNIEWSKI: MONOLITHIC CMOS PLL BASED ON A MULTIPHASE RING OSCILLATOR
TABLE I
OSCILLATION FREQUENCY CORRESPONDING TO PARAMETERS i, ,
k
FOR
N = 7 AND 9
x
AND
Fig. 9.
case).
Fig. 10.
Fig. 8. Oscillation frequency versus stage number
parameter.
913
N with feedback index i as
due to the fact that
is negative. Since
for
has a
, a higher oscillation
larger value compared to that for
frequency is achieved. Table I lists the corresponding values
of the simulated oscillation frequency and parameters , , and
for
and . As explained earlier, is the feedforward
and corresponding frequency
index. The positive values of
are highlighted.
Fig. 8 summarizes the simulation results illustrating oscillawith as a parameter. For
,
tion frequency versus
. However,
the highest oscillation frequency is achieved at
, the highest oscillation frequency is achieved at
for
. For
, we get the highest frequency at
. The
magresults confirm the prediction from the calculation of
nitude. From Fig. 7 we found that although the circuit achieves
, it produces a sinusoidal-like wavehighest speed when
(
). Similar phenomenon can be obform when
case,
served for other values, but all corresponding to
as shown in Fig. 9. Since its total power consumption is actually lower than the case corresponding to the highest frequency,
a higher equivalent quality factor is expected for the
case.
Interpolating inverter
S
x
pass over three major loop inverters ( = 3
Combined single stage with multiple feedback.
For
, improved speed is achieved when
or . If
two feedback indices are combined in one circuit as shown in
Fig. 10, an even higher oscillation frequency can be obtained.
This can be extended to a longer chain ring to form multifeedin the nine stages
back loops, for example, combining
) ring.
(
It should be noted that the improved speed for a constant
output voltage swing comes at the expense of greater power
consumption due to the time overlap when both nMOS and
pMOS are on. We are more interested in power efficiency rather
than power consumption in comparison of oscillators running
at different speed. The power efficiency can be measured by
the product of the oscillation period and power consumption.
as example, the period–power product for
Taking
are 13.2, 27.7, and 26.1 pJ, respectively. The conven) single-ring structure has highest power efficiency
tional (
overall. Among the subfeedback-loop-based structure,
(
,
) case has the highest efficiency.
D. Frequency Tuning
In additional to the feature of improved speed, we observe
from (3) that the oscillation frequency of an -stage ring
oscillator with a fixed feedback index can be tuned by varying
any one of three parameters: loading capacitance , loading
resistance , and relative strength of interpolating inverters
. Capacitive tuning has the drawback of lowering the
maximum speed of operation because the minimum value of
capacitor still loads the circuit. Although a resistive tuning can
provide a large frequency variation, it causes a voltage swing
and voltage gain variation [9]. When transistors operating in
the triode region are used as loading resistors, their nonlinearity
degrades the common-mode noise rejection for a differential
circuit. According to (3), the oscillation frequency of the
subfeedback-loop-based ring oscillators linearly depends on
. When
is controlled by an external voltage, the tuning
. This tuning scheme is especially
range is
useful when loading resistors in the delay stages are implemented with linear resistors (e.g., poly resistors) to improve the
common-mode noise rejection.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 6, JUNE 2001
Fig. 11. Eight-phase-output ring oscillator based on three-stage (i
subfeedback loops.
Fig. 12.
=
3)
Fig. 14.
ICO differential stage, V –I , and bias circuit.
Fig. 15.
PFD, charge pump, and loop filter.
Three-dimensional representation of the ring oscillator from Fig. 11.
Fig. 13. Phase relationship of the circuit in Fig. 11.
III. DESIGN OF AN EIGHT-PHASE-OUTPUT RING OSCILLATOR
The topology in Fig. 3 was used to design a four-stage differential ring oscillator as shown in Fig. 11. Compared with
conventional ring oscillators, four inverters are interpolated to
,
construct the subfeedback loops. With feedback index
each subfeedback loop contains three inverters (M1–M2–S4;
M3–M4–S2; M2–M3–S1; M4–M1–S3) and is established as a
fast loop. The main feedback loop with four stages is the slow
loop. By redrawing the circuit in three dimensions as shown
in Fig. 12, the subfeedback loops can be more easily viewed
(single-ended inverters are plotted for simplicity). It should be
noted that stages in altitude and latitude are designed not to oscillate in a two-stage ring oscillator mode to ensure reliable oscillation and reduction of phase noise. Fig. 13 shows the phase
relationship of eight output signals (when matched delay stages
and loading are used). Imposing these phase relations to (3), the
, which can be used
minimum required dc gain is
to calculate the initial value of transistors for design and simu, it is much
lation. Since minimum dc gain is not related to
is controlled with an exeasier to maintain oscillation when
ternal control signal.
A combined single delay stage of the ICO core circuit is
shown in Fig. 14. It consists of a major loop inverter and an
interpolating inverter. Fully differential inverters are used to reduce the sensitivity to power supply fluctuation and substrate
noise and to reduce the distortion of the duty cycle. The two
nMOS source-coupled differential pairs share the same loads,
but have separated tail current sources. Frequency tuning can
controlled by a single-ended signal or
be accomplished with
controlled (push–pull) by a differential signal. In
both
is connected to a proportional-to-absolute temthis design,
is controlled by the
perature (PTAT) current reference and
charge pump/loop filter output signal through a voltage-to-current ( – ) converter for frequency and phase locking. The oscillator is optimized to operate at the required output frequency
. The – circuit is also shown in Fig. 14.
when
The PTAT reference circuit reduces the VCO’s sensitivity to
temperature and process variation. In the PTAT bias reference,
to the pMOS source and tying the source
placing resistor
and n-well of each pMOS transistors eliminate body effect. By
connecting a diode-connected pMOS transistor in shunt with an
equal size biased pMOS transistor, the linearity of loading can
be improved [10]. 200 ppm/ C of temperature sensitivity and
6%/V of power supply sensitivity without the use of a regulator
is achieved with a good frequency control linearity.
IV. PLL DESIGN AND MEASUREMENT RESULTS
The PFD is based on a conventional three-state phase detector
(PD) shown in Fig. 15. The circuit consists of two edge-triggered resettable D-flip-flops which were implemented using dynamic logic circuitry. In order to minimize the dead zone associated with the three-state PFD, extra delay is introduced in the
reset path through inverters.
The charge pump and loop filter are also shown in Fig. 15.
The UP and DN signals from the PFD switch the corresponding
, thus delivering a charge to adcurrent sources onto node
up or down. Both current sources are mirrored from a
just
,
bandgap current. When neither nor is connected to
they are biased by the unity-gain amplifier [11]. It suppresses
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SUN AND KWASNIEWSKI: MONOLITHIC CMOS PLL BASED ON A MULTIPHASE RING OSCILLATOR
Fig. 16.
Die photograph of the PLL clock generator.
Fig. 18.
915
PLL jitter histogram.
TABLE II
SUMMARY OF MEASURED PLL CLOCK GENERATOR PERFORMANCE
power consumption of 109 mW for a 3.3-V supply (Fig. 18).
Table II summarizes the measurement results.
Fig. 17.
Measurement result of the ICO (in PLL) transfer characteristic.
V. CONCLUSION
the charge sharing from the parasitic capacitance on node or
, thus reducing the spike on the loop filter.
The prescaler used to divide the VCO output by factor 2 is
designed using a true-single-phase clock (TSPC) D-flip-flops
[12]. The transistors’ size is optimized to achieve high-speed operation. The frequency operating range of the prescaler is from
400 MHz to 3 GHz with a power consumption of 6 mW at maximum frequency. The divide by 8/32 divider is also based on the
dynamic flip-flops which are connected as a ripple counter and
resynchronized at the output.
The bandwidth of the PLL affects the stability, the lock-in
time, and the suppression of phase noise from the VCO. The
of 40 k
loop bandwidth is chosen to be 2 MHz with resistor
and charge pump current of 20 A.
and
are 240 and 1 pF,
respectively.
The PLL clock generator was implemented monolithically
in a 0.35- m single-poly three-metal CMOS technology [13].
Fig. 16 shows the die photo of PLL clock generator. By varying
the input reference frequency, the ICO transfer characteristic
were measured and shown in Fig. 17. The ICO has a good control linearity. The jitter histogram of the PLL was measured with
other transceiver blocks active on chip. The tracking jitter at
1.25-GHz output is 11 ps (RMS) and 80 ps (peak-to-peak) with
A general ring oscillator topology for multiphase output has
been presented and analyzed. The topology uses the interpolating inverter stages to construct fast loops for long-chain ring
oscillators to achieve both higher speed and multiphase outputs.
The analysis leads to a relationship between relative oscillation
frequency increment/decrement and the feedback index , which
is the number of inverters inside a subfeedback loop. An odd
number of inverter stages inside a subfeedback loop can increase
the operating frequency. For a long-chain ring, there exist optimum values which give the highest operating frequency and
highest power efficiency, respectively.
A 1.25-GHz monolithic CMOS PLL clock generator prototype was designed for a data transceiver. The monolithic PLL
consists of a ring oscillator, divider, PFD, charge pump, and
on-chip loop filter. The design accommodates process, supply
voltage, and temperature variations. The voltage controlled oscillator incorporates a four-stage differential ring structure with
subfeedback loops embedded to speed up and tune the circuit.
It has a linear control characteristics, eight-phase outputs, and
wide tuning range. The fully integrated PLL was fabricated in
a 0.35- m CMOS process, occupies an active area of 1 mm ,
and consumes about 100 mW operating from a 3.3-V supply. A
RMS tracking jitter of 11 ps was measured.
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916
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 6, JUNE 2001
ACKNOWLEDGMENT
The authors would like to thank V. Lee, D. Cartina,
K. Iniewski, B. Gerson, M. Chua, R. Zavari, and Y. Xu of
PMC-Sierra, Inc., Burnaby, Canada, for their support.
[12] J. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE
J. Solid-State Circuits, vol. 24, pp. 62–70, Feb. 1989.
[13] L. Sun and T. Kwasniewski, “A 1.25-GHz 0.35-m monolithic CMOS
PLL clock generator for data communications,” in Proc. IEEE Custom
Integrated Circuits Conf., 1999, pp. 265–268.
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[6] D. Jeong, S. Chai, W. Sing, and G. Cho, “CMOS current controlled oscillators using multiple feedback loop ring architectures,” in ISSCC Dig.
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[7] L. Sun, T. Kwasniewski, and K. Iniewski, “A quadrature output voltagecontrolled ring oscillator based on three-stage subfeedback loops,” in
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[8] A. B. Grebene, Bipolar and MOS Analog Integrated Circuit Design. New York: Wiley Interscience, 1984, ch. 11.
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[10] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based
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Lizhong Sun received the M.Eng. and Ph.D. degrees
in electrical engineering from McGill University,
Montreal, PQ, Canada, and Carleton University,
Ottawa, ON, Canada, in 1994 and 1999, respectively.
From 1994 to 1996, he was with OZ Optics, Carp,
ON, Canada, working on fiber optics and optoelectronic components. In the summer of 1998, he was
with PMC-Sierra, Burnaby, BC, Canada, working on
CMOS phase-locked loops for frequency synthesis
and data recovery. In 1999, he joined Bell Labs, Lucent Technologies, Allentown, PA, as a Member of
Technical Staff. He is currently working on high-speed analog and mixed-signal
IC design.
Tadeusz A. Kwasniewski (M’86) received the
Ph.D. and M.S. degrees from the Institute of Nuclear
Research and Warsaw University of Technology,
Poland, in 1974 and 1980, respectively.
He worked as a Research and Development
Engineer in Warsaw’s Institute of Nuclear Research
and VOEST Alpine in Austria. In 1983, he joined
Lakehead University and in 1985, Carleton University, Ottawa, ON, Canada. His research interests
include CMOS radio circuits and signal processing
architectures. He is currently with PMC-Sierra,
Burnaby, BC, Canada, on leave of absence from Carleton University. He is
currently working on high-speed CMOS data recovery and synthesis circuits.
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