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Introduction to CMOS VLSI Design Lecture 25: Package, Power, Clock, and I/O David Harris Harvey Mudd College Spring 2007 Outline Packaging Power Distribution Clock Distribution I/O 25: Package, Power, and I/O CMOS VLSI Design Slide 2 Packages Package functions – Electrical connection of signals and power from chip to board – Little delay or distortion – Mechanical connection of chip to board – Removes heat produced on chip – Protects chip from mechanical damage – Compatible with thermal expansion – Inexpensive to manufacture and test 25: Package, Power, and I/O CMOS VLSI Design Slide 3 Package Types Through-hole vs. surface mount 25: Package, Power, and I/O CMOS VLSI Design Slide 4 Multichip Modules Pentium Pro MCM – Fast connection of CPU to cache – Expensive, requires known good dice 25: Package, Power, and I/O CMOS VLSI Design Slide 5 Chip-to-Package Bonding Traditionally, chip is surrounded by pad frame – Metal pads on 100 – 200 mm pitch – Gold bond wires attach pads to package – Lead frame distributes signals in package – Metal heat spreader helps with cooling 25: Package, Power, and I/O CMOS VLSI Design Slide 6 Advanced Packages Bond wires contribute parasitic inductance Fancy packages have many signal, power layers – Like tiny printed circuit boards Flip-chip places connections across surface of die rather than around periphery – Top level metal pads covered with solder balls – Chip flips upside down – Carefully aligned to package (done blind!) – Heated to melt balls – Also called C4 (Controlled Collapse Chip Connection) 25: Package, Power, and I/O CMOS VLSI Design Slide 7 Package Parasitics Use many VDD, GND in parallel – Inductance, IDD Package Signal Pads Signal Pins 25: Package, Power, and I/O Chip VDD Bond Wire Lead Frame Board VDD Package Capacitor Chip Chip GND CMOS VLSI Design Board GND Slide 8 Heat Dissipation 60 W light bulb has surface area of 120 cm2 Itanium 2 die dissipates 130 W over 4 cm2 – Chips have enormous power densities – Cooling is a serious challenge Package spreads heat to larger surface area – Heat sinks may increase surface area further – Fans increase airflow rate over surface area – Liquid cooling used in extreme cases ($$$) 25: Package, Power, and I/O CMOS VLSI Design Slide 9 Thermal Resistance DT = qjaP – DT: temperature rise on chip – qja: thermal resistance of chip junction to ambient – P: power dissipation on chip Thermal resistances combine like resistors – Series and parallel qja = qjp + qpa – Series combination 25: Package, Power, and I/O CMOS VLSI Design Slide 10 Example Your chip has a heat sink with a thermal resistance to the package of 4.0° C/W. The resistance from chip to package is 1° C/W. The system box ambient temperature may reach 55° C. The chip temperature must not exceed 100° C. What is the maximum chip power dissipation? 25: Package, Power, and I/O CMOS VLSI Design Slide 11 Example Your chip has a heat sink with a thermal resistance to the package of 4.0° C/W. The resistance from chip to package is 1° C/W. The system box ambient temperature may reach 55° C. The chip temperature must not exceed 100° C. What is the maximum chip power dissipation? (100-55 C) / (4 + 1 C/W) = 9 W 25: Package, Power, and I/O CMOS VLSI Design Slide 12 Power Distribution Power Distribution Network functions – Carry current from pads to transistors on chip – Maintain stable voltage with low noise – Provide average and peak power demands – Provide current return paths for signals – Avoid electromigration & self-heating wearout – Consume little chip area and wire – Easy to lay out 25: Package, Power, and I/O CMOS VLSI Design Slide 13 Power Requirements VDD = VDDnominal – Vdroop Want Vdroop < +/- 10% of VDD Sources of Vdroop – IR drops – L di/dt noise IDD changes on many time scales Power Max clock gating Average Min Time 25: Package, Power, and I/O CMOS VLSI Design Slide 14 Power System Model Power comes from regulator on system board – Board and package add parasitic R and L – Bypass capacitors help stabilize supply voltage – But capacitors also have parasitic R and L Simulate system for time and frequency responses Voltage Regulator VDD Bulk Capacitor Printed Circuit Board Planes Ceramic Capacitor Board 25: Package, Power, and I/O Package and Pins Solder Bumps Package Capacitor On-Chip Capacitor Chip On-Chip Current Demand Package CMOS VLSI Design Slide 15 Bypass Capacitors Need low supply impedance at all frequencies Ideal capacitors have impedance decreasing with w Real capacitors have parasitic R and L – Leads to resonant frequency of capacitor 2 10 1 10 1 mF 0.25 nH impedance 0.03 10 10 10 0 -1 -2 10 4 10 5 10 6 10 7 10 8 10 9 10 10 frequency (Hz) 25: Package, Power, and I/O CMOS VLSI Design Slide 16 Frequency Response Use multiple capacitors in parallel – Large capacitor near regulator has low impedance at low frequencies – But also has a low self-resonant frequency – Small capacitors near chip and on chip have low impedance at high frequencies Choose caps to get low impedance at all frequencies impedance frequency (Hz) 25: Package, Power, and I/O CMOS VLSI Design Slide 17 Clock Distribution On a small chip, the clock distribution network is just a wire – And possibly an inverter for clkb On practical chips, the RC delay of the wire resistance and gate load is very long – Variations in this delay cause clock to get to different elements at different times – This is called clock skew Most chips use repeaters to buffer the clock and equalize the delay – Reduces but doesn’t eliminate skew 25: Package, Power, and I/O CMOS VLSI Design Slide 18 Example Skew comes from differences in gate and wire delay – With right buffer sizing, clk1 and clk2 could ideally arrive at the same time. – But power supply noise changes buffer delays – clk2 and clk3 will always see RC skew gclk 3 mm 3.1 mm clk1 clk2 1.3 pF 25: Package, Power, and I/O 0.4 pF CMOS VLSI Design 0.5 mm clk3 0.4 pF Slide 19 Review: Skew Impact F1 Q1 Combinational Logic D2 Tc clk tpcq Q1 tskew tpdq tsetup D2 clk t pd Tc t pcq tsetup tskew Q1 CL clk D2 tcd thold tccq tskew F2 sequencing overhead clk F2 clk F1 Ideally full cycle is available for work Skew adds sequencing overhead Increases hold time too tskew clk thold Q1 tccq D2 25: Package, Power, and I/O tcd CMOS VLSI Design Slide 20 Cycle Time Trends Much of CPU performance comes from higher f – f is improving faster than simple process shrinks – Sequencing overhead is bigger part of cycle 1000 100 MHz SpecInt95 10 1 80386 80486 Pentium Pentium II / III 0.1 1988 1991 1994 80386 80486 Pentium Pentium II / III 1997 10 1985 2000 1988 1991 1994 1997 2000 100 500 VDD = 3.3 VDD = 5 FO4 inverter delays / cycle Fanout-of-4 (FO4) Inverter Delay (ps) 0.01 1985 100 VDD = 2.5 200 100 50 2.0 1.2 0.8 0.6 0.35 0.25 50 80386 80486 Pentium Pentium II / III 20 10 1985 1988 1991 1994 1997 2000 Process 25: Package, Power, and I/O CMOS VLSI Design Slide 21 Solutions Reduce clock skew – Careful clock distribution network design – Plenty of metal wiring resources Analyze clock skew – Only budget actual, not worst case skews – Local vs. global skew budgets Tolerate clock skew – Choose circuit structures insensitive to skew 25: Package, Power, and I/O CMOS VLSI Design Slide 22 Clock Dist. Networks Ad hoc Grids H-tree Hybrid 25: Package, Power, and I/O CMOS VLSI Design Slide 23 Clock Grids Use grid on two or more levels to carry clock Make wires wide to reduce RC delay Ensures low skew between nearby points But possibly large skew across die 25: Package, Power, and I/O CMOS VLSI Design Slide 24 Alpha Clock Grids Alpha 21064 Alpha 21164 Alpha 21264 PLL gclk grid Alpha 21064 25: Package, Power, and I/O gclk grid Alpha 21164 CMOS VLSI Design Alpha 21264 Slide 25 H-Trees Fractal structure – Gets clock arbitrarily close to any point – Matched delay along all paths Delay variations cause skew A A and B might see big skew 25: Package, Power, and I/O CMOS VLSI Design B Slide 26 Itanium 2 H-Tree Four levels of buffering: – Primary driver – Repeater – Second-level clock buffer – Gater Route around obstructions Repeaters Typical SLCB Locations Primary Buffer 25: Package, Power, and I/O CMOS VLSI Design Slide 27 Hybrid Networks Use H-tree to distribute clock to many points Tie these points together with a grid Ex: IBM Power4, PowerPC – H-tree drives 16-64 sector buffers – Buffers drive total of 1024 points – All points shorted together with grid 25: Package, Power, and I/O CMOS VLSI Design Slide 28 Input / Output Input/Output System functions – Communicate between chip and external world – Drive large capacitance off chip – Operate at compatible voltage levels – Provide adequate bandwidth – Limit slew rates to control di/dt noise – Protect chip against electrostatic discharge – Use small number of pins (low cost) 25: Package, Power, and I/O CMOS VLSI Design Slide 29 I/O Pad Design Pad types – VDD / GND – Output – Input – Bidirectional – Analog 25: Package, Power, and I/O CMOS VLSI Design Slide 30 Output Pads Drive large off-chip loads (2 – 50 pF) – With suitable rise/fall times – Requires chain of successively larger buffers Guard rings to protect against latchup – Noise below GND injects charge into substrate – Large nMOS output transistor – p+ inner guard ring – n+ outer guard ring • In n-well 25: Package, Power, and I/O CMOS VLSI Design Slide 31 Input Pads Level conversion – Higher or lower off-chip V – May need thick oxide gates Noise filtering A – Schmitt trigger – Hysteresis changes VIH, VIL VDDH A VDDL Y VDDL A Y weak Y Y weak A Protection against electrostatic discharge 25: Package, Power, and I/O CMOS VLSI Design Slide 32 ESD Protection Static electricity builds up on your body – Shock delivered to a chip can fry thin gates – Must dissipate this energy in protection circuits before it reaches the gates Diode clamps ESD protection circuits R PAD – Current limiting resistor Thin Current gate limiting oxides – Diode clamps resistor ESD testing 1500 Device – Human body model Under 100 pF Test – Views human as charged capacitor 25: Package, Power, and I/O CMOS VLSI Design Slide 33 Bidirectional Pads Combine input and output pad Need tristate driver on output – Use enable signal to set direction – Optimized tristate avoids huge series transistors PAD En Din Dout NAND Dout En Y Dout NOR 25: Package, Power, and I/O CMOS VLSI Design Slide 34 Analog Pads Pass analog voltages directly in or out of chip – No buffering – Protection circuits must not distort voltages 25: Package, Power, and I/O CMOS VLSI Design Slide 35 MOSIS I/O Pad 1.6 mm two-metal process – Protection resistors – Protection diodes – Guard rings – Field oxide clamps PAD 600/3 264 185 Out 240 48 90 160 20 40 En In Out In_unbuffered 25: Package, Power, and I/O In_b CMOS VLSI Design Slide 36