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Course Introduction
Purpose
• This course discusses techniques that are used to analyze and eliminate
noise in embedded microcontroller and microprocessor systems.
Objectives
• Learn how use a Workbench Faraday Cage (WBFC) and a hybrid balun
to measure common-mode emissions.
• Understand benefits of using a low-noise MCU.
• Gain knowledge about a technique for reducing common-mode emissions
from PCB supply lines.
• Learn how the common-mode noise reduction technique can be applied
to LSI packages and circuit board power distribution lines.
Content
• 17 pages
Learning Time
30 minutes
Reducing EMI
EMI reduction is a goal shared by both
the semiconductor experts who design
MPUs and other LSI devices, and by the
engineers who apply those chips in
embedded systems
Explanation of Terms
Anechoic
chamber
A room designed to block radiation from the outside and to minimize reflections off the room’s walls, ceiling, and floor
Balun
A passive electronic device that converts between balanced and unbalanced electrical signals
CISPR 25
International Special Committee on Radio Interference (CISPR) publication 25: “Limits and methods of measuring
radio disturbance characteristics for the protection of receivers on board vehicles.” CISPR is a sub-committee of the
International Electrotechnical Commission (IEC).
Core
A microcontroller chip is composed of a core, I/O ports, and power supply circuitry. The core consists of the CPU,
ROM, RAM, and blocks implementing timers, communication, and analog functions.
ECU
Electronic Control Unit
EMI
Electromagnetic Interference
Harness
Cables (wires) connecting a board and power supply or connecting one unit in a system to another
LISN
Line Impedance Stabilization Network
Power
supply
Two power supplies are applied to the LSI: Vcc and Vss. The core power supply internal to the LSI is VCL
(internal step-down). The Vss-based power supply routed through the LSI is VSL.
TEM Cell
Transverse Electromagnetic Cell
WBFC
Workbench Faraday Cage
Emission-measurement Standards
The international standards listed here are used to measure
electromagnetic emissions* from MCUs and other ICs
Latest Standard
Document
Issue Date
Remarks
IEC 61967-1: General conditions and definitions
[IEC 61967-1]
2002-03-12
IS
IEC 61967-2: Measurement of radiated emissions,
[IEC 61967-2]
2005-09
IS
[IEC TS 61967-3]
2005-06
TS
IEC 61967-4: Measurement of conducted emissions,
[IEC 61967-4]
2002-04-30
IS
1-ohm/50-ohm Direct Coupling Method
[IEC 61967-4
Ed. 1.1]
2006-2007
Edition 1.1
IEC 61967-5: Measurement of conducted emissions,
[IEC 61967-5]
2003-01-17
IS
[IEC 61967-6]
2002-06-25
IS
Standard No.: Title
TEM-cell and wideband TEM-cell Method
IEC 61967-3: Measurement of radiated emissions,
Surface Scan-method (Technical Specifications)
Workbench Faraday Cage Method
IEC 61967-6: Measurement of conducted emissions,
Magnetic Probe Method
*Measurement range: 150kHz to 1GHz
IS: IEC International Standard
TS: Technical Specification
Workbench Faraday Cage
Used to measure common-mode voltage at Vss points on PCB modules
- Obtains results similar to CISPR-25 or antenna techniques
performed in an anechoic chamber
Common-mode voltage, u, is very small
Vcc
vn
u
Typical Test Setup
Block Diagram
Measuring Common-mode Voltage
The WBFC method was used to compare two MCUs under identical
conditions with no ground plane, no nearby bypass capacitor, and a
long signal cable
Conventional microcontroller (XY)
Reduced-noise microcontroller (RN)
XY
RN
Vcm (Gnd)
measurement point
Vcm (Gnd)
measurement point
Photos show 2-layer evaluation boards illuminated from below
WBFC Evaluation Results
Common-mode noise of RN MCU is much less than that of XY device
Conventional MCU (XY)
FM band
Reduced-noise MCU (RN)
FM band
Only CPU core
operating
(CAN and ports
stopped)
CPU and CAN
operating
(Ports stopped)
CPU, CAN and
ports operating
(Ports stopped)
500 kHz, 1 line
Evaluated at power supply pins
Measuring Vector Sum, Difference
Using a Faraday cage and a hybrid balun, measurements
of both common-mode and differential-mode emissions
can be made
Hybrid Balun
SUM
-
ISO
+
+
0°
Common-mode Test Setup
+
180
°
Differential-mode Test Setup
WBFC
WBFC
Vcm (Vcc)
Vcm (Vss)
0° port
180° port
180° Hybrid balun
ISO port
Vcm (Vcc)
Vcc + Vss
SUM port
Vcm (Vss)
180°
Hybrid balun
180°
Hybrid balun
Terminator
Spectrum Analyzer
Vcc - Vss
Data from Test of XY MCU
Combined noise from XY chip is the same as levels at Vcc and Vss points
- Noise in key bands (FM, etc.) could be a problem
FM band
Data for XY MCU
Data for XY MCU
Vcc
Frequency
Attenuation approximately
the same as Vcc or Gnd alone
Frequency
Vss
Frequency
Vcc - Vss
Vcc + Vss
Frequency
Test conditions: CAN and ports stopped. Cable constantly connected to Vcc and Gnd (Vss) power supply pins. A 50Ω terminator connected to Gnd
during Vcc measurement and to Vcc during Vss measurement. Same cable lengths used for Vcc (+/-) Vss measurements. ISO and SUM output
measured with hybrid balun connected (output under measurement terminated).
Results from Reduced-noise MCU
RN MCU’s combined noise is less than levels at Vcc and Gnd points
- Balanced pin layout reduces common-mode noise
FM band
RNRN
MCU
Data for
MCU
Data for RN MCU
Vcc
Frequency
Attenuation greater than Vcc or Gnd
alone (phase difference nearly 180°)
Vss
Frequency
Vcc + Vss
Attenuation greater than Vcc or Gnd alone
Vcc - Vss
Frequency
Frequency
Test conditions: CAN and ports stopped. Cable constantly connected to Vcc and Gnd (Vss) power supply pins. A 50Ω terminator connected to Gnd
during Vcc measurement and to Vcc during Vss measurement. Same cable lengths used for Vcc (+/-) Vss measurements. ISO and SUM output
measured with hybrid balun connected (output under measurement terminated).
Minimizing CM Radiation — 1
A step-by-step investigation was conducted to find ways to
minimize common-mode noise
Printed Circuit Board
Wire Harness
Data from Simulation
MCU
Breakthrough
Current
Bypass
Capacitor
Parasitic Capacitance
Circuit Diagram
Cv Lv
I2
I1
Zc
Ic
Vd
Cg
I2
Lg
I1
Vc
Equivalent Circuit
Computer Simulations
Made with Different Parameters
Minimizing CM Radiation — 2
Analysis of data from a simulator revealed that emissions
are minimized when a balance of impedances is achieved
Printed Circuit Board
Wire Harness
Data from Simulation
MCU
Breakthrough
Current
Bypass
Capacitor
Parasitic Capacitance
Circuit Diagram
Cv Lv
I2
I1
Zc
Ic
Vd
Cg
I2
Lg
I1
Vc
Equivalent Circuit
Computer Simulations
Made with Different Parameters
Data Analysis
[Conclusion: Noise is
minimized when
LvCv = LgCg]
Minimizing CM Radiation — 3
Subsequent R&D found practical ways to implement designs that
produced significantly lower amounts of common-mode emissions
- 20dB reductions are possible
Printed Circuit Board
Wire Harness
MCU
Breakthrough
Current
Bypass
Capacitor
Parasitic Capacitance
Data Analysis
[Conclusion: Noise is
minimized when
LvCv = LgCg]
Circuit Diagram
Cv Lv
I2
I1
Zc
Data from Simulation
Ic
Vd
Cg
I2
Lg
I1
Vc
Equivalent Circuit
Computer Simulations
Made with Different Parameters
Design and testing of
various boards to
check theory against
reality and create
practical implementations
Overall conclusion:
To minimize commonmode current and noise,
the impedances of the
Vcc and Vss lines
must be balanced
Information about this research was
presented at the following events:
• Conference of Japan Institute of Electronics
Packaging (Mar 22-24, 2006)
• IEEE EMC Symposium (Aug. 14-18, 2006),
Portland, OR
• IEEE EMC Symposium (July. 8-13, 2007),
Honolulu, HI
Low-noise Board Layout
Same noise-reduction-method can be applied to the
pc board layout used to connect an LSI device
• Experiments were conducted to test the method
H8S/2134
- Supply and ground wiring connections to the
package of an H8S/2134 MCU were changed
- The redesign achieved a balanced layout
- Emissions tests were conducted on ECU boards
with unbalanced and balanced supply and ground
layouts to determine the amount
of noise reduction obtained
Balanced layout
of power and
ground wiring on pc board
Red=Vcc Blue=Vss
Unbalanced vs. Balanced Layout
• Balanced board layout achieved 20dB noise reduction in the FM band
• For much of the frequency range, the emission levels from the board
with the balanced layout are no greater than the system dark noise
Noise Level vs. Frequency
Noise Level (dBµA)
FM band
-110
Conventional
supply/ground
board layout
-120
Balanced
layout
–20dB
reduction
-130
Noise floor
-140
0
32
64
96
128
160
192
Frequency (MHz)
Test method: CISPR 25, automotive-specification equivalent
Setup for CISPR-25 test
ECU board, harness, LISN, and battery were laid out
on a wooden bench in a shielded enclosure
ECU
board
MCU
Current Probe
MCU
Model
Test bench
Vcc Line
Battery
C1
LISN
Vss Line
C2
Parasitic
Capacitances
Signal lines may be
included in CISPR-25 testing.
Reference Ground Plane
Equivalent
Circuit
Common-mode Current
The amount of common-mode current (Icm, yellow arrow) equals the
difference between Ig (blue arrow) and Iv (red arrow)
ECU
Current Probe
MCU
Model
Test bench
Vcc Line
C1
Vss Line
Parasitic
Capacitances
C2
Battery
Iｖ
LISN
Iｇ
Common-mode
Current, Icm
(Ig - Iv)
Reference Ground Plane
Equivalent
Circuit
Changing the Supply Lines
The patterns used for supply lines were systematically varied to create seven
different patterns on two-layer boards
- These figures show patterns 1 and 2
2
Pattern 1
Pattern 2
Simulation: Vcc & Vss Patterns
• Simulation showed that in Pattern 1 the common-mode voltage swing
of Vss was opposite the swing of Vcc but larger, an unbalance that
caused emissions in the wiring harness
• In Pattern 2, the swing of Vss was equal and opposite to that of Vcc,
thus minimizing the common-mode voltage and current — and the
resulting emissions from the harness
Pattern 1
Vss (Gnd) side
Vcc
(high) side
Pattern 2
Vss (Gnd) side
Vcc
(high) side
Compensating for Cv/Cg Imbalance
If Cg > Cv, inductance can be inserted into the supply line
to decrease common-mode emissions
Test results when Cv = Cg = 2.5pF
Problem: With Lv = 10nH, Lg = 2nH,
Cv = 0.45pF and Cg = 4.55pF,
common-mode noise was too high
20dB reduction
Test conditions:
Lv = 10nH = inductance of supply wiring on the PCB
Cv= 0.45pF = parasitic capacitance of supply wiring
Lg = 2nH = inductance of ground-side wiring
Cg:= 4.55pF = parasitic capacitance of ground-side wiring
To compensate for a large Cv,
increase Lv to make L vC v = LgC g
Compensating for Cv/Cg Imbalance
Design approach was verified by finding a minimum in the CM current
when the area of Vcc pattern — and thus, Cv — was changed
Copper foil added
Back side of printed circuit board
If Cg is too big, increase Cv
by adding pattern area.
Common-mode Current [dBµA]
- Location of expanded foil area
is important.
Common-mode Current vs. Pattern Area
Problem: With Lv = 10nH, Lg = 2nH,
and Cg = 4.55pF, find value of Cv
that minimizes common-mode current
Added Pattern Area [mm2]
Course Summary
• Use of the Workbench Faraday Cage and hybrid balun
• Emissions of conventional microcontroller versus
reduced-noise MCU
• Technique for reducing common-mode emissions from
PCB supply lines by achieving balanced impedances
• Application of the CM noise reduction-method to the
package for a microcontroller
• Tests showing the effectiveness of the technique for
reducing common-mode noise
For more information on specific devices and related
support products and material, please visit our Web site:
http://america.renesas.com