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Memory Management
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Background
• Programs must be brought (from disk) into memory for
them to be run
• Main memory and registers are only storage CPU can
access directly
• Register access in one CPU clock (or less)
• Main memory can take many cycles
• Cache sits between main memory and CPU registers
• Protection of memory access privileges required to ensure
correct operation
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Base and Limit Registers
Simplistically, a pair of base and limit registers
define the logical address space
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Logical vs. Physical
Address Space
• The concept of a logical address space that is bound to a
separate physical address space is central to proper memory
management
– Logical address – generated by the CPU; also referred to as
virtual address
– Physical address – address seen by the memory unit
• Memory-Management Unit (MMU) is the hardware device that
maps virtual to physical address
• Logical and physical addresses are the same in compile-time
address-binding schemes; logical (virtual) and physical
addresses differ in execution-time address-binding
scheme. The user program deals with logical
addresses - it never sees the real physical addresses
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Binding of Instructions
and Data to Memory
Address binding of instructions and data to memory
addresses can happen at two different stages
– Compile time: If memory location known a priori,
absolute code can be generated; must recompile
code if starting location changes
– Execution time: Binding delayed until run time if
the process can be moved during its execution from
one memory segment to another. Needs
hardware support for address maps.
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Dynamic Loading
• Routine is not loaded until it is called.
• Better memory-space utilization; unused routine is
never loaded.
• Useful when large amounts of code are needed to
handle infrequently occurring cases
• No special support from the operating system is
required, implemented through program design.
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Allocation Possibilities
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Contiguous Allocation
• Main memory usually divided into two partitions:
– Resident operating system, usually held in low memory.
– User processes then held in high memory.
• Relocation registers used to protect user processes from
each other, and from changing operating-system code and
data.
– Base register contains value of smallest physical address
– Limit register contains range of logical addresses –
each logical address must be less than the limit
register.
– MMU maps logical address dynamically.
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HW Address Protection with
Base and Limit Registers
Logical +
relocation
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Contiguous Allocation
(Cont.)
Multiple-partition allocation
– Hole – block of available memory; holes of various size are
scattered throughout memory
– When a process arrives, it is allocated memory from a hole
large enough to accommodate it
– Operating system maintains information about:
a) allocated partitions b) free partitions (hole)
OS
OS
OS
OS
process 5
process 5
process 5
process 5
process 9
process 9
process 8
process 2
process 10
process 2
process 2
process 2
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Dynamic StorageAllocation Problem
How to satisfy a request of size n from a list of free holes
• First-fit: Allocate the first hole that is big enough
• Next -fit: Like first fit, but allocate the first hole from
last allocation that is big enough
• Best-fit: Allocate the smallest hole that is big enough;
must search entire list
– Produces the smallest leftover hole
• Worst-fit: Allocate the largest hole; must also search
entire list
– Produces the largest leftover hole
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Fragmentation
• External Fragmentation – total memory space exists to
satisfy a request, but it is not contiguous
• Internal Fragmentation – allocated memory may be
slightly larger than requested memory; this size difference
is memory internal to a partition, but not being used
• Reduce external fragmentation by compaction
– Shuffle memory contents to place all free memory
together in one large block
– Compaction is possible only if relocation is
dynamic, and is done at execution time
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Segmentation
• Memory-management scheme that supports user view
of memory
• A program is a collection of segments. A segment is a
logical unit such as:
main program,
procedure,
function,
method,
object,
local variables, global variables,
common block,
stack,
symbol table, arrays
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User’s View of a
Program
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Logical View of
Segmentation
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1
2
3
4
2
3
user space
physical memory space
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Segmentation Architecture
• Logical address consists of a two tuple:
<segment-number, offset>
• Segment table – maps two-dimensional physical
addresses; each table entry has:
– base – contains the starting physical address where the
segments reside in memory
– limit – specifies the length of the segment
• Segment-table base register (STBR) points to the
segment table’s location in memory
• Segment-table length register (STLR) indicates
number of segments used by a program;
segment number s is legal if s < STLR
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Segmentation Hardware
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Segmentation
Architecture - Cont.
• Protection
– With each entry in segment table associate:
• validation bit = 0  illegal segment
• read/write/execute privileges
• Protection bits associated with segments; code sharing
occurs at segment level.
• Since segments vary in length, memory allocation is a
dynamic storage-allocation problem.
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Example of Segmentation
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Paging
• Logical address space of process can be noncontiguous; process
is allocated physical memory whenever the latter is available.
• Divide physical memory into fixed-sized blocks called frames
(size is power of 2).
• Divide logical memory into blocks of same size called pages.
• Keep track of all free frames.
• To run a program of size n pages, need to find n free frames and
load program.
• Set up a page table to translate logical to physical
addresses.
• Internal fragmentation.
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Address Translation
Scheme
Address generated by CPU is divided into:
•Page number (p) – used as an index into a page table which contains
base address of each page in physical memory
•Page offset (d) – combined with base address to define the physical
memory address that is sent to the memory unit
page number
page offset
p
d
m-n
n
•For given logical address space of size 2m and page size is 2n
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Paging Hardware
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Shared Pages
• Shared code
– One copy of read-only (reentrant) code shared among
processes (i.e., text editors, compilers, window systems).
– Each page table maps onto the same physical copy of
the shared code.
• Private code and data
– Each process keeps a separate copy of the code and
data.
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Paging Model of Logical
and Physical Memory
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Paging Example
32-byte memory and 4-byte pages
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Free Frames
Before allocation
After allocation
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Active Memory
To check if a page is a valid memory address we have a
Valid-invalid bit attached to each entry in the page table:
– “valid” indicates that the associated page is in the
process’ logical address space, and is thus a legal page.
– “invalid” indicates that the page is not mapped at this
time.
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Trashing
• Thrashing may be caused by programs or workloads
that present insufficient locality of reference
• If the working set of a program or a workload cannot
be effectively held within physical memory, then
constant data swapping, i.e., thrashing, may occur
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Thrashing
• To resolve thrashing due to excessive paging, a user can
do any of the following.
– Increase the amount of RAM in the computer
(generally the best long-term solution).
– Decrease the number of programs being run on the
computer.
– Replace programs that are memory-heavy with
equivalents that use less memory.
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Swapping
• A process can be swapped temporarily out of memory to a
backing store, and then brought back into memory for
continued execution
• Backing store – disk large enough to accommodate
copies of all memory images for all users;
• Roll out, roll in – swapping variant used for priority-based
scheduling algorithms; lower-priority process is swapped
out so higher-priority process can be loaded and executed
• System maintains a ready queue of ready-to-run
processes which have memory images on disk
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Schematic View of
Swapping
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Implementation of Page
Table
• Page table is kept in main memory
• Page-table base register (PTBR) points to the page table
• Page-table length register (PRLR) indicates size of the page
table
• In this scheme every data/instruction access requires two memory
accesses. One for the page table and one for the data/instruction.
• The two memory access problem can be solved by the use of a
special fast-lookup hardware cache called associative memory or
translation look-aside buffers (TLBs)
• Some TLBs store address-space identifiers (ASIDs) in
each TLB entry – uniquely identifies each process to
provide address-space protection for that process
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Paging Hardware With
TLB
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Structure of the Page
Table
• As the number of processes increases, the
percentage of memory devoted to page tables
also increases.
• The following structures solved this problem:
– Hierarchical Paging
– Hashed Page Tables
– Inverted Page Tables
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Hierarchical Page
Tables
• Break up the logical address space into multiple
page tables.
• A simple technique is a two-level page table (the
page table is paged).
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Two-Level Page-Table
Scheme
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Two-Level Paging Example
• A logical address (on 32-bit machine with 1K page size) is
divided into:
– a page number consisting of 22 bits
– a page offset consisting of 10 bits
• Since the page table is paged, the page number is divided into:
– a 12-bit page number
– a 10-bit page offset
• Thus, a logical address is as follows:
page number
p1
12
page offset
p2
d
10
10
• where p1 is an index into the outer page table, and
p2 is the displacement within the page of the outer
page table.
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Address-Translation
Scheme
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Hashed Page Tables
• Common in address spaces > 32 bits.
• The virtual page number is hashed into a page table.
This page table contains a chain of elements hashing
to the same location.
• Virtual page numbers are compared in this chain
searching for a match.
• If a match is found, the corresponding physical frame
is extracted.
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Hashed Page Table
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Inverted Page Table
• One entry for each real page of memory.
• Entry consists of the virtual address of the page stored in
that real memory location, with information about the
process that owns that page.
• Decreases memory needed to store each page table, but
increases time needed to search the table when a page
reference occurs.
• Use hash table to limit the search to one - or at most
a few - page-table entries.
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Inverted Page Table
Architecture
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