Download Advanced Low Power Techniques

Low Power Design Techniques
Lecture
Dr.Ing. Goran Panić
19.05.2016
Fakultet Tehničkih Nauka, Čačak
Agenda
1
Introduction
2
Power Consumption
3
Standard Low Power Techniques
4
Advanced Low Power Techniques
5
Power Aware Design Methodologies
6
Future Trends In Low Power Design
7
Conclusion
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2
Agenda
1
Introduction
2
Power Consumption
3
Standard Low Power Techniques
4
Advanced Low Power Techniques
5
Power Aware Design Methodologies
6
Future Trends in Low Power Design
7
Conslusion
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3
Why Low Power?
• more functionality, limited battery capacity
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4
Introduction – Bulk-CMOS Trends
CMOS Scaling – Increase of static power loss
Low Power Design – Advanced techniques to reduce both static and dynamic power
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Introduction – Advanced CMOS Trends
New Process Technologies - SOI, Multi-gate, FinFet, etc.
Source: ITRS 2011
Reduced Static Power - still needs to be maintained!
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Agenda
1
Introduction
2
Power Consumption
3
Standard Low Power Techniques
4
Advanced Low Power Techniques
5
Power Aware Design Methodologies
6
Future Trends in Low Power Design
7
Conclusion
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7
Power Consumption – Power vs Energy
E1 = P x T
Energy determines the battery life!
E2 = (P/2) x 2T = P x T = E1
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Power Consumption – Power in CMOS
CMOS Power = Dynamic Power + Static Power
Dynamic Power
- power dissipation when logic gates are switching
- associated with active mode of operation
- consists of two components: switching and internal power
Static Power
- results from leakage currents
- dissipated also when transistors are turned off
- inreases with device shrinking, i.e. technology scaling
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Power Consumption – Dynamic Power Loss
Switching Power – power consumption due to charge/discharge of load capacitance
Energy/ Transition  CL  Vdd2
Psw  Energy / Transition  f  C L  Vdd2    f clock
Psw  Ceff  Vdd2  f clock
C eff  C L  
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Power Consumption – Dynamic Power Loss
Internal Power – short-circuit power when input signal is at intermediate voltage level
Psc  t sc  Vdd  I peak  f clock
Pdyn  Psw  Psc  Ceff  Vdd2  f clock  t sc  Vdd  I peak  f clock
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Power Consumption - Static Power Loss
Static Power – Leakage power resulting from leaking currents in transistors
I1 - reverse-bias p-n junction diode leakage
I2 - subthreshold leakage
I3 - gate leakage through the oxide
I sub  K1We
Vth
nV
(1  e
Vdd
V
)
I4 - gate induced drain leakage
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Agenda
1
Introduction
2
Power Consumption
3
Standard Low Power Techniques
4
Advanced Low Power Techniques
5
Power Aware Design Methodologies
6
Future Trends in Low Power Design
7
Conclusion
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Standard Low Power Techniques
• Established for mature technologies
• Focused on reducing supply voltage, switching activity and load capacitance
Standard Low Power Techniques:
• Supply voltage scaling (multi-Vdd)
• Multi-threshold voltage
• Clock gating
• Operand isolation
• Gate-level optimization
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Standard Low Power Techniques – Multi-Vdd
• different blocks operate at different supply voltage
• benefits from reduction of supply voltage
• large impact on design complexity
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Standard Low Power Techniques – Multi-Vth
• usage of both high-Vth and low-Vth transistors in a single chip
• high impact on static power
• moderate impact on dynamic power
• implementation supported by EDA tools
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Standard Low Power Techniques – Clock Gating
•
•
most popular standard technique
disabling the switching of clock nets in inactive parts of circuit
•
•
significant reduction of switching power
automatic clock gating insertion supported by EDA tools
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Standard Low Power Techniques – Operand Isolation
• similar to clock gating
• reduces switching activity in inactive datapath blocks
• automatized implementation supported by modern EDA tools
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Standard Low Power Techniques – Gate Level Optimization
• logic restructuring – making high-activity nets internal to the cell
high activity net
• pin swapping – rewiring of low-capacitance gate pins to high-activity nets
high activity
net
low activity
net
high power input
low power input
low activity
net
high activity
net
• other gate-level techniques: cell sizing, buffer insertion
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Standard Low Power Techniques - Overview
Technique
Multi-Vth
Clock Gating
Multi-Vdd
Operand
Isolation
Gate-Level
Techniques
Dynamic
Power
Savings
low
(<5%)
medium
(<30%)
large
(<50%)
low
(<5%)
low
(<15%)
Leakage
Power
Savings
Timing
Penalty
Area
Penalty
Impact:
Architecture
Impact:
Design
Impact:
Verification
Impact:
Place
&Route
2-3x
little
little
low
low
none
low
none
little
little
low
low
none
low
2x
some
little*
high
medium
low
medium
none
little
little
low
low
none
low
none
little
little
none
none
none
none
• Dynamic Power – multi-Vdd and clock gating most effective
• Static Power – multi-Vth and multi-Vdd most effective
• Implementation automated (except for multi-Vdd)
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Agenda
1
Introduction
2
Power Consumption
3
Standard Low Power Techniques
4
Advanced Low Power Techniques
5
Power Aware Design Methodologies
6
Future Trends in Low Power Design
7
Conclusion
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Advanced Low Power Techniques
• Developed to deal with the increasing contribution of leakage currents in
deep-submicron CMOS
Process-Level Techniques:
• Retrograde and halo doping (bulk-CMOS)
• Silicon-On-Insulator (SOI)
• Multiple-Gate MOSFET (FinFet)
Circuit-Level Techniques:
• Multi-voltage design
• Voltage and frequency scaling
• Power gating
• Body biasing
• Stacked transistor
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Advanced Low Power Techniques – Retrograde and Halo Doping
Different aspects of well engineering
Retrograde channel doping
- low surface channel concentration followed by a highly-doped subsurface region
- improves short-channel effects, increase surface channel mobility -> increase of treshold voltage
Halo doping
- introduces highly doped p-regions at the edges of the channel
- reduces width of depletion area in drain and source -> reduce of threshold voltage degradation
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Advanced Low Power Techniques - SOI
Bulk vs SOI
Bulk-CMOS vs PDSOI vs FDSOI
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Advanced Low Power Techniques – Multiple-Gate MOSFET
-
three-dimensional multiple gates (two-gate, three-gate, allaround, etc.)
-
either bulk or SOI process
FinFET Structure – three-gate MOSFET
-
silicon fin controlled from three sides -> improved subthreshold slope -> lower power in
subthreshold region
-
inversion area increased -> high drive current -> better performance
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Advanced Low Power Design – Multi-Voltage Design
Concept of power islands (voltage islands, power domains)
a)
SVS – static voltage scaling
b)
MVS – multi-voltage scaling
c)
DFVS – dynamic frequency and voltage scaling
d)
AFVS – adaptive voltage scaling
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Advanced Low Power Techniques - DFVS
Benefits:
reduction of both dynamic and static power
Challenges:
voltage regulators, task scheduling, transition time, voltage shifters, timing/voltage
pairs, libraries, power-up sequencing
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Advanced Low Power Techniques - Power Gating (1)
Shut down the power supply of inactive blocks
Multithreshold-CMOS (MTCMOS) – high-Vth switch transistors vs low-Vth logic
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Advanced Low Power Techniques – Power Gating (2)
Power gates – header vs footer
Power gating controller – control of power-up sequences
lsolation logic – prevents crowbar currents in active logic blocks
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Advanced Low Power Techniques – Power Gating (3)
Power Switches
Ring vs Grid-Style
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Advanced Low Power Techniques – Power Gating (4)
Benefits:
large impact on static power saving
EDA tools support for automatized insertion
Challenges:
design strategy (header vs footer, fine vs coarse, ring vs column, etc)
data retention (retention flip-flops, scan-based approach, etc)
design issues (control, isolation, design flow, etc)
implementation issues (synthesis, floorplanning, etc)
testability (scan insertion, etc)
verification (functionality, power, etc)
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Advanced Low Power Techniques – Body Biasing
control of threshold voltage by connecting body of transistor to a bias network
RBB (reverse BB) – negative body-to-source voltage to NMOS (increase threshold -> reduce leakage)
FBB (forward BB) – positive body-to-souce voltage to NMOS (decrese threshold -> bust performance)
ABB (adaptive BB) – allows calibration of each chip in post-production phase (compensation for PVT variations)
DBB (dynamic BB) – dynamic change of body bias during chip operation
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Advanced Low Power Techniques – Stacked Transistors
Stacking effect – subthershold current flowing through a series of transistors
reduces when more than one transistors in the stack is turned off
- reduces significantly subtheshold leakage
- large area penalty
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Low Power Memories
Standard SRAM (MOSFET-based)
• power gating with retention
• multi-bank memories
• voltage scaling
Non-Volatile RAM
• Magnetoresistive RAM (MRAM) - fast Rd/Wr, unlimited endurance, high power
for writing, scalability issues
• Feroelectric RAM (FRAM) – good performance, high on/off current ratio (low
power), reliability issues, low density
• Phase Change RAM (PCRAM) – good scalability, fast, high current for
programming, limited number of write cycles, temperature instability
• Resistive RAM (RRAM) – low programming current, low endurance
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Advanced Low Power Techniques - Overview
Technique
SVS/
MVS
DVFS
Power
Gating
BodyBiasing
Dynamic
Power
Savings
high
(40-50%)
high
(40-70%)
Leakage
Power
Savings
Timing
Penalty
Area
Penalty
Impact:
Architecture
Impact:
Design
Impact:
Verification
Impact:
Place&
Route
2X
low
medium
medium
medium
medium
low
2-3X
low
medium
high
high
high
medium
~0%
10-50X
medium
mediumhigh
high
mediumhigh
high
high
~0%
10X
high
medium
high
high
medium-high
high
SVS/MVS – both dynamic and static power savings, medium impact on architecture
DVFS – high dynamic power savings, static power savings, high impact on architecture
Power Gating – high static power savings, high impact on architecture
Body-biasing – overshadowed by power gating
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Agenda
1
Introduction
2
Power Consumption
3
Standard Low Power Techniques
4
Advanced Low Power Techniques
5
Power Aware Design Methodologies
6
Future Trends in Low Power Design
7
Conclusion
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Power-Aware Design Methodologies (1)
-
industry enabled power-aware design flows
-
need to express power-related specification and rules: design power intent
-
CPF (common power format) vs UPF (unified power format)
CPF-enabled Low Power flow with Cadence tools
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Power-Aware Design Methodologies (2)
UPF-Enabled Synopsys Low Power Flow
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Power-Aware Design Methodologies (3)
High-Level Power Estimation
-
architecture, behavioral, instruction and system level
-
analytical or empirical models
Comercial tools
-
Cadence InCyte – IP based
-
Power Theater / Power Artist – RTL level
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Agenda
1
Introduction
2
Power Consumption
3
Standard Low Power Techniques
4
Advanced Low Power Techniques
5
Power Aware Design Methodologies
6
Future Trends in Low Power Design
7
Conclusion
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Future Trends in Low Power Design (1)
Diversification – non-digital functionalities do not scale at same rate as CMOS
Source: ITRS
• trade-off between performance and power for individual applications
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Future Trends in Low Power Design (2)
Evolving role of design phases in system power minimization
Source: ITRS
• high-level methods for saving power become more important
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Future Trends in Low Power Design (3)
Impact of future design technology improvements on power
Design Technology
Improvement
Year
Dynamic Power
Improvement (x)
Static Power
Improvement (x)
Software Virtual
Prototype
2011
1.23
1.20
Frequency Islands
2013
1.26
1.00
Near-Threshold
Computing
2015
1.23
0.80
Hardware/Software CoPartitioning
2017
1.18
1.00
Heterogeneous Parallel
Processing
2019
1.18
1.00
Many Core Software
Development Tools
2021
1.20
1.00
Power-Aware Software
2023
1.21
1.00
Asynchronous Design
2025
1.21
1.00
Description of
Improvements
Virtualization tools to allow
the programmer to develop
software prior to silicon
Designing blocks that operate
at different frequencies
Lowering Vdd to 400 – 500 mV
Hardware/software
partitioning at the behavioral
level based on power
Using multiple types of
processors in a parallel
computing architecture
Using multiple types of
processors in a parallel
computing architecture
Developing software using
power consumption as
parameter
Non-clock driven design
Source: ITRS
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Agenda
1
Introduction
2
Power Consumption
3
Standard Low Power Techniques
4
Advanced Low Power Techniques
5
Power Aware Design Methodologies
6
Future Trends in Low Power design
7
Conclusion
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Conclusion
-
Power is the most important challenge in design of portable SoC design
-
Both dynamic and static power concerned
-
Focus on energy reduction rather than on peak power
-
Combination of standard and advanced techniques for optimal results
-
Evolve of advanced process technologies focused on low power
-
Advanced design methodologies for efficient low power design
-
Future trends forsee major utilization of high-level techniques for saving
power
The quest for low power continues!
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Thank you for your attention!
Goran Panić
www.ihp-microelectronics.com
A11B
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