Download Optical Ethernet Design

Slide 1
© 2001 By Default!
Gigabit Optical Ethernet
ECE 4006C – Spring 2002 – G1
Team
Ryan Baldwin
David Gewertz
Geoffrey Sizemore
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Slide 2
© 2001 By Default!
Overview

Background on Ethernet Technology
– from classical Ethernet standards to Gb
Installation and testing of legacy Intel/Agilent
test-bed
 Set-up and testing of Maxim Evaluation
Boards
 Design, assembly, and testing of prototype
receiver module using Max3266 and
Max3264 chips

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Slide 3
© 2001 By Default!
Ethernet

Ethernet invention in Xerox Palo Alto
Research Center by Dr Metcalf
– Coincided with the introduction of personal
computers
Initially 3 Mbps, standardized at 10 Mbps
 1 and 10 Gbps on the horizon

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Slide 4
© 2001 By Default!
Common Considerations

Bandwidth
– 80-20 rule
– Ethernet vs. ATM or FDDI
• Backbone, desktop

Backwards compatibility
– OSI stack
– Physical layer
• Connectors and cabling
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Slide 5
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Implementation Using Fiber
Fiber is replacing UTP cable
 Why?

– Better performance characteristics over longer
distances
For Gb data rates: UTP < 100 meters
Fiber < 260 meters
– Higher bandwidth capabilities
– Integration with fiber backbone
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Slide 6
© 2001 By Default!
Cabling Overview
Four mediums: 2 Fiber-based, 2
Copper-based (1000BaseSX,
1000BaseLX, 1000BaseT,
1000BaseCX)
 Fiber allows greater distances, Copper
offers greater flexibility

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Slide 7
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Cabling Technologies
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Slide 8
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Previous Team’s Progress

Design Team Objectives
– Separation of optical transceiver from Intel card
– Redesign and fabrication of new board containing
optical functionality
– Reintegration of board with Intel setup
– Verification to meet optical ethernet specifications
– Use of evaluation kits in further design efforts
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Slide 9
© 2001 By Default!
Pitfalls and Resolutions
Transmission line
noise
Power supply
interference
Different current
requirements for
multiple components
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• Avoided right angles in printed
circuitry
• Length considerations (1/101/4 of a wavelength)
• Differential signaling
• Load balancing (50-Ohm)
• Filtering required to isolate
current sources
• Multiple power supplies
• Decoupling capacitors
Slide 10
© 2001 By Default!
Final Circuit Diagram (Fall 2001)
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Slide 11
© 2001 By Default!
Maxim Evaluation Kits

MAX3266 Evaluation Board Diagram
Photodiode emulation circuit replaced by
photodetector
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Slide 12
© 2001 By Default!
Maxim Evaluation Kits

Circuit Modifications to Minimize Current Loss
– Replacing series resistors and adding a 67-Ohm resistor in
parallel
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Slide 13
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MAX3266 Board Functionality

Photodiode emulation

Transimpedance Amplifier (TIA) on chip
– inexpensively mimic the output of a photodetector
for chip feature testing
–
–
–
–
converts current to voltage
converts single-ended input to differential output
1 mA p-p input = 250 mV p-p output
10 micro-A p-p input = 2.5 mV p-p output
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Slide 14
© 2001 By Default!
Maxim Evaluation Kits

MAX3264 Evaluation Board Diagram
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Slide 15
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MAX3264 Board Functionality

Proper termination impedance and series
capacitors to maintain voltage regularity
 Buffer on chip
– maintains integrity of output from TIA

Limiting Amplifier on chip

RMS Power Detection
– provides 55 dB gain with 1.2 Volt max
– low jitter enables higher speeds
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Slide 16
© 2001 By Default!
Testing and Verification

Pattern Generator
– Tektronix GTS 1250 (1250 Mb/s)
– desired BER = 10-12 or 1 error every terabit
• Example - For a 4 MB MP3, that would be one bit error
for every 31,000 songs transferred

Tektronix CSA 7xxx Scope
– accurately measures and records Gb eye
diagrams
– uses specially designed Communications Signal
Analyzer software
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Slide 17
© 2001 By Default!
Initial Design Idea
Single PCB with both chips
 Interface with other design groups (OE,
TX)
 Interference-free implementation of a
single power source to drive all active
components

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Slide 18
© 2001 By Default!
Intel Gb Test-bed
Intel PCI card with optical
transceiver removed and
reattached through SMA
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PC-to-PC test with card
installed and 100 meter fiber
link
Slide 19
© 2001 By Default!
Intel Gb Test-bed Results
Testing showed no packet loss
*discrepancy in tx/rx packets due to lack of termination synchronization between transmitter and receiver
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Slide 20
© 2001 By Default!
Block Diagram of Maxim Setup
Oscilloscope TDS7154
BERTS GTS1250
Out +
Out -
Note: Scope gets clock
signal from BERTS
+15 +3.3 GND
Dual Output Variable Power Supply
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Slide 21
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Simulated Maxim Setup
PRBS Signal (27-1)
TDS7154 Screen Capture
Maxim
Boards
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Slide 22
© 2001 By Default!
Maxim Knowledge
Lack of DC
cancellation network
created huge jitter
Single Power supply implementation did not introduce noise
to system due to filtering networks on the evaluation boards
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Slide 23
© 2001 By Default!
Unused Maxim Features
Loss of Signal
Compares the RMS level of
the input signal to a
threshold determined value
Squelch
Holds the differential output
voltage static whenever LOS
threshold is not met
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Slide 24
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Initial Draft of Layout
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Slide 25
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PCB Layout Software
FREE!
FREE!
FREE!
Extensive library of components and easy-to-use interface
And it’s “FREE! FREE! FREE!” © Matthew Lesko
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Slide 26
© 2001 By Default!
Receiver Board Layout
Power Connectors Note: Backwards!
Supply Traces
GND Traces
SMA Connectors
Note: SMA connectors connected to bottom of board
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Slide 27
© 2001 By Default!
Prototype Board with Results
K28.5 Input
PRBS7 Input
K28.5 Bit Pattern
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Slide 28
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Problems Encountered
Oscillation in bit pattern results with
variation in power jack setup.
Cross-talk seen when power wires
were in close proximity to board,
SMA cables, or each other.
Possible ground interference issues
could have affected results.
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Here
Slide 29
© 2001 By Default!
Conclusions
Investigated Background on Ethernet
Technology
 Installed and tested legacy Intel/Agilent testbed from Fall 2001
 Set-up and tested Maxim Evaluation Boards
 Designed, assembled, and tested prototype
receiver module using Max3266 and
Max3264 chips
 Next group should examine oscillation and
noise inconsistencies

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