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NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
National Central University
Department of Electrical Engineering Electronic Design Automation Laboratory
High-Level Power/Noise
Estimation of VLSI Designs
劉建男 助理教授
Prof. Chien-Nan (Jimmy) Liu
國立中央大學 電機工程學系
Dept. of EE, National Central Univ.
Email: [email protected]
TEL: 03-4227151 ext:34534
http://www.ee.ncu.edu.tw/~jimmy
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Who am I ???

Education:





1996/9-2001/5: MS & PHD of
National Chiao Tung Univ, Taiwan
(advisor: Prof. Jing-Yang Jou)
1992/9-1996/6: BS of
Dept. of EE, NCTU, Taiwan
Join Dept. of EE, Nat’l Central Univ.
after graduate (from 2001/8)
Group members: 9 Ph.D, 11 master
Research interests: VLSI/CAD on
2017/5/6




Functional verification
Verification of system-level integration
Behavioral modeling of digital/analog circuits
High-level power/current modeling
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
What is CAD ?
CAD = Computer-Aided Design
 Exist everywhere in the whole design flow
EDA = Electronic Design Automation
 CAD for electronic industry
Typically, more than 50% design time is elapsed on
running CAD tools
CAD research falls between design (hardware) and
programming (software)
 Require knowledge from both parts
Methodology (thinking) + program (implementation)
2017/5/6
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
Outline
Introduction
High-Level Power Modeling
High-Level Current Waveform Modeling
Conclusion
Chien-Nan Liu
1000
Transistors (MT)
NCU Electrical Engineering Electronic Design Automation Laboratory
Moore’s Law in Microprocessors
2X growth in 1.96 years!
100
10
486
1
386
286
0.1
0.01
P6
Pentium® proc
8086
8080
8008
4004
8085
0.001
1970
1980
1990
Year
2000
2010
Transistors on Lead Microprocessors double every 2 years
Source: Courtesy, Intel
2017/5/6
Chien-Nan Liu
4004
386
NCU Electrical Engineering Electronic Design Automation Laboratory
Chien-Nan Liu
2017/5/6
The Dies of Intel CPUs
Pentium Pro
NCU Electrical Engineering Electronic Design Automation Laboratory
Trends of VLSI Design
Reference : www.doulos.com
2017/5/6
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
What is SoC?
System-on-Chip
An IC that integrates the major functional elements of a
complete end-product into a single chip
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Scanner on a Chip
National Semiconductor
IEEE Spectrum
Jan. 1999, p.57
2017/5/6
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Chien-Nan Liu
2017/5/6
Design Methodology Transition
10000
Power Density (W/cm2)
NCU Electrical Engineering Electronic Design Automation Laboratory
Power Density
1000
100
Rocket
Nozzle
Nuclear
Reactor
8086 Hot Plate
10 4004
P6
8008 8085
Pentium® proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Power density is getting higher and higher !!
Source: Courtesy, Intel
2017/5/6
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Why Power Estimation ?
Design space has been moved from 2-D (Area/Delay) to
3-D (Area-Delay-Power)
Objectives
 Verify the power dissipation requirements
 Can be used during the circuit, logic and high-level synthesis to
make trade-off between power and other design parameters
• Area, performance, noise margin, …
Power estimation tools are essential
 Exploit the potential to reduce power by design techniques
• An analysis of the expected power dissipation of a particular design
alternative has to be made
 Identify other power related design problems
• Reliability, Hot spot detection, Electromigration, Voltage drops,
Package selection
2017/5/6
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
Noise Problems
Must be checked for signal integrity (SI) problems before
manufacturing
Noise from crosstalk:
victim
aggressor
victim



delay increase
IR-drop is also an
serious problem due to
large peak current
 I , Vdd, actual ↓
Chien-Nan Liu
setup violations
NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
SSN (Simultaneous Switch Noise)
When logic gates turn on at
the same time, power supply
can generate large currents
that introduce SSN.
The SSN estimation can be
divided into two parts,
current waveform and
pad model.
current
CVDD
LVDD
CL
CVSS
Chien-Nan Liu
LVSS
Potential for Power Savings
NCU Electrical Engineering Electronic Design Automation Laboratory
More Impacts at Higher Levels
400%
50%
20%
Behavioral
RTL
Gate
10%
Switch
Accuracy of Power Estimation
2017/5/6
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Target SOC Analysis Platform
circuit
netlist
noise/power aware
cell library
2017/5/6
cell noise
model
input
vectors
Macro / IP
database
macro noise
model
full chip
power & noise
analysis platform
cell power
model
macro power
model
power
noise
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
Bottom-Up Power & Current Model
Estimated
Power Consumption
& Current Waveform
High-Level
(Behavior, RTL)
logic
synthesis
power
model
current
model
Gate-Level
physical
synthesis
simulation
Transistor-Level
Chien-Nan Liu
Model
Characterization
Real
Power Consumption
& Current Waveform
NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
Outline
Introduction
High-Level Power Modeling
 Traditional Power Modeling
 Our Neural Power Model
High-Level Current Waveform Modeling
Conclusion
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Power Dissipation
Leakage power
 Static dissipation due to leakage current
 Typically a smaller value compared to other power dissipation
 Getting larger and larger in deep-submicron process
Short-circuit power
 Due to the short-circuit current when both PMOS and NMOS are open
during transition
 Typically a smaller value compared to dynamic power
Dynamic power
VDD
 Charge and discharge of a load capacitor
 Usually the major part of total
power consumption
Vin
• Energy per switch
1
2
E  CVDD
2
2017/5/6
Vout
GND
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Traditional Power Modeling (1/2)
Look-Up Table (LUT) is the most popular method
 Straight-forward idea
 Easy to use
Number of possible input transitions for an n-input
combinational circuit is 22n
 Impractical to stored the whole input transitions in a table
 Solution
• Use probability measurements liked P(xi), D(xi), etc. …
P: signal probability
D: transition density
2017/5/6
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Traditional Power Modeling (2/2)
Some approaches use equations instead of LUT
Power = C1*Pin+C2*Din+C3*Dout+C4*Pin*Din+ …
 Use linear regression to find out the parameters that form the
equation
 Less data to be recorded than LUT
 Hard to use only a single equation to describe the irregular
power distribution curve
To improve the accuracy, they may
 Increase the order of the power equations
 Increase the number of power equations
Become more and more complex in large designs
2017/5/6
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Challenges in Sequential Circuits
Strong correlations often exist in the input sequence
 Temporal correlation: relationship between consecutive vectors
Internal state “unknown” problem
Existing method : Solve Chapman-Kolmogorov equations
2017/5/6
 Compute the state probabilities in steady state
 Take a probability distribution over the states of the Markov chain at time t
and compute the probability distribution at time t+1
• Not real enough !!
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Our Key Ideas
Use neural network concept instead of LUT
 Learn the relationship between input/output signal statistics and
corresponding power
 Fit the non-linear power curves more easily
Recurrent neural networks (RNNs)
 Elman neural network with internal feedback path
 Can handle temporal correlations of sequential circuits
Low complexity, high accuracy
2017/5/6
 Can be extended to large designs
Chien-Nan Liu
Mathematical model
 Simulate the biological neural network
 Composed of weights (W) and bias (b) matrices
Neuron
(神經元)
神經樹
神經核
神經軸
神經節
P1
P2
w1,1
Applications:
n
Σ
P3
…
…
NCU Electrical Engineering Electronic Design Automation Laboratory
Neural Network (NN)
w1,R
b
PR
 Classification, clustering,
pattern recognition, non-linear systems modeling, etc.
2017/5/6
Chien-Nan Liu
f
y=f(Wp+b)
y
NCU Electrical Engineering Electronic Design Automation Laboratory
The Operation of NN
Learning Phase
Recalling Phase
Input (Training Input)
Input
Neural
Network
Neural
Network
W
Expected Output
(Training Target)
Error
Function
Output
2017/5/6
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Proposed Construction Flow
Building network
Parameter
Selection
Input Sequence
Setting Hidden
Neuron Number
Transistor-level
simulation
Generation
Statistic
Analysis
Training Sets
T
Building
Neural Network
No
Functional
Simulation
Training
Neural Network
(1 iteration)
Yes
Iteration >
Limit?
No
Network training
?
Yes
DONE
2017/5/6
Satisfy Error
Requirement
Chien-Nan Liu
Training set
generation
NCU Electrical Engineering Electronic Design Automation Laboratory
Input Data Type
An example of the signal transition statistics
Input vectors
MSB
Corresponding output vectors
LSB
Timei 0 0 0 1 1 1 0 1 0 1
Timei+1 1 0 1 0 1 0 1 0 1 1
TI00
1/10

TI01
 
  4/10
TI10
3/10
  
TI11

 2/10
TI00=0.1, TI01=0.4, TI10=0.3, TI11=0.2
TI
TO
2017/5/6
MSB
LSB
Timei 0 1 0 1 1 0 1 1 0 0
Timei+1 0 1 1 0 1 1 0 1 1 1
TO00 
1/10
TO01


  4/10
TO10
2/10


TO11
3/10



TO00=0.1, TO01=0.4, TO10=0.2, TO11=0.3
0.1
0.4
0.3
0.2
0.1
0.4
0.2
0.3
Estimated power
consumption
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Power Estimation with Trained NN
For a test sequence with m pattern-pair
2017/5/6
Transition
Analysis
Input Patterns /
Expected Outputs
Trained
Neural Network
Signal Transition
Vectors
1/m
Average
Power
Accumulated
Outputs
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Experiments Setup
Circuits
 ISCAS’89 benchmark + one real design (*FMP)
 0.35um cell library
Golden simulation results
 PowerMill
Neural network implementation
 Use built-in functions of MATLAB
 Run on Intel P-IV 2.4GHz with 1G RAM
*FMP: Forward Matrices Processor
2017/5/6
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Experimental Results (1/3)
# of
input
pins
# of
output
pins
gate count
Neurons in
Hidden Layer
|W|
Construction
time (s)
S344
9
11
160
9
91
119
S349
9
11
161
10
101
907.5
S386
7
7
159
7
71
447.9
S641
35
24
379
9
91
839.6
S713
35
23
393
10
101
168.8
S1196
14
14
529
10
101
1028.5
S1238
14
14
508
7
71
451.3
S1423
17
5
657
10
101
919.7
S1488
8
19
653
7
71
457.2
S1494
8
19
647
8
81
542.5
FMP
144
104
8,200
10
101
906.75
8.8
89.2
617.2
Average
2017/5/6
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Experimental Results (2/3)
3D-LUT Power Model
Neural-Based Power Model
Max
Avg
Std
Max
Avg
Std
S344
-100
13.62
23.8
-3.7
1.2
1.03
S349
-13.09
3.62
3.46
4.63
1.11
0.87
S386
-29.44
4.74
5.82
-33.2
9.09
6.4
S641
-7.72
1.22
1.42
-11.8
4.2
3.3
S713
-9.02
1.34
1.62
7.36
2.62
2.17
S1196
-11.19
2.05
2.27
-13.8
4.2
3.19
S1238
-10.85
2.28
2.37
-13.6
4.81
3.91
S1423
-19.26
2.42
3.36
-19.1
6.44
5.29
S1488
-70.99
12.14
16.58
-31.6
9.34
6.79
S1494
-81.09
18.13
21.28
9.04
1.92
1.47
FMP
6.35
1.17
1.55
-7.26
1.87
1.46
Average
32.64
5.7
7.59
14.1
4.25
3.26
length of test sequences: 500 pattern-pair
2017/5/6
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
Experimental Results (3/3)
Table-Based
max. Err: 32.64%
avg. Err: 5.70%
Std: 7.59%
Neural-Based
max. Err: 14.10%
avg. Err: 4.25%
Std: 3.26%
length of test sequences: 1,000 pattern-pairs
Smaller variation for different cases (std: standard variation)
Smaller size than look-up table
Competitive accuracy on average
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Compared to LUT
Memory Overhead
LUT based
• ex: 10*10*10/2 entries (In 3-D table, interval size=0.1 of each
dimension)
NN based
• Only have to store 2 matrixes. (< 100 floating point numbers)
Construction Time
LUT based
• Need a lot of time to build the table
NN based
• In our experiment, it only cost less than 30 min. to build our
model. (ISCAS’89)
2017/5/6
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
Summary: Power Estimation
We propose a novel power model for sequential circuits
 Use the learning capability of neural networks
 Can be used at behavior level (only need input/output info.)
 Can be extended to large circuits with low complexity
 High efficiency and accuracy even for short sequences
References:
 Wen-Tsan Hsieh, Chih-Chieh Shiue, and Chien-Nan Jimmy Liu, “A Novel
Approach for High-Level Power Modeling of Sequential Circuits Using Recurrent
Neural Networks”, IEEE International Symposium on Circuit and Systems (EI),
pp. 3591-3594, May 2005.
 Wen-Tsan Hsieh, Chih-Chieh Shiue, and Chien-Nan Jimmy Liu, “Efficient Power
Modeling Approach of Sequential Circuits Using Recurrent Neural Networks”,
IEE Proceedings - Computers and Digital Techniques (SCI, EI), vol. 153, no. 2, pp.
78-86, March 2006.
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
Outline
Introduction
High-Level Power Modeling
High-Level Current Waveform Modeling
 Gate-level current waveform estimation using existing information
 Macro-level current waveform estimation using neural network
Conclusion
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
Existing Waveform Estimation Tool
Timing unit is user defined
 Max power is depend on timing unit (E=P*t)
 Limited by the library file format (.LIB)
 Not suitable to calculate Pmax
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
.LIB Format
The most popular library format
Single input / single output pair
2D table (input transition time, output load)
 rise time , fall time , propagation delay
 rise power, fall power
ttran
index_1 ("0.0500, 0.1000, 0.4000, 0.9000, 1.4000, 2.0000, 3.0000");
index_2 ("0.00180, 0.09000, 0.18000, 0.45000, 0.81000, 1.17000, 1.53000");
values ( \
CL
"0.0315, 0.2730, 0.5264, 1.2880, 2.3030, 3.3180, 4.3330", \
"0.0445, 0.2744, 0.5264, 1.2880, 2.3030, 3.3180, 4.3330", \
"0.1103, 0.3311, 0.5567, 1.2900, 2.3030, 3.3180, 4.3330", \
"0.2074, 0.4773, 0.6792, 1.3530, 2.3210, 3.3200, 4.3330", \
"0.2974, 0.6122, 0.8277, 1.4580, 2.3860, 3.3560, 4.3460", \
"0.4021, 0.7646, 1.0000, 1.6130, 2.4980, 3.4370, 4.4030",
"0.5770, 1.0020, 1.2660, 1.9040, 2.7340, 3.6260, 4.5550");
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
Our Key Ideas
Assume triangular waveforms for basic gates
 Most of the current waveforms are similar to a triangle.
 A reasonable assumption that simplifies the current waveform
problems.
Use existing .lib information
 Advanced library format for current waveform is not
standardized and not supported by many tools.
 Use some simple calculation to generate the current waveform
from existing timing and power information stored in .lib files.
 Do not require additional circuit characterization efforts.
 Easier to be integrated with current EDA tools.
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Triangular Waveform
Base：
Is+Ic_internal
 T0 is start time of current waveform.
 T2 is end time of current waveform.
Position：
 T1 is position of maximum current happened.
CL
Height：
 Imax is value of maximum current.
T0
Base?
T1
Imax
Height?
2017/5/6
Ic_load
T2
t
Position?
I
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Voltage Waveform Rebuild
Use piece-wise-linear voltage waveform to simplify the voltage
waveform
tr：Rise time(ns) : output 10%vdd ~ output 90%vdd
tf：Fall time(ns) : output 90%vdd ~ output 10%vdd
td：Delay time(ns) : input 50%vdd ~ output 50%vdd
tin：Input transition time(ns) : input 0%vdd~input 100%vdd
5
tr
8
vin
ttran
2
2017/5/6
5
tr
8
vout
ttran
2
Chien-Nan Liu
½tr = 50% ~ 90%
 T(50%~100%)
= ½tr*5/4 =5/8tr
NCU Electrical Engineering Electronic Design Automation Laboratory
Definition of Base Width (Rise)
T0 = －{(VDD/2−vt)/VDD}×Tin (PMOS turn on)
T(vt to ½Vdd), where Tin is 0 to Vdd
T2=td + (5/8)tr
(CL charge to vdd)
Delay Time + Time of (Vout=50%~100)
td (5/8)tr
Vin
VDD-Vt
(1/2)VDD
0
T0
T2
t
The transition point of
logic simulation (½Vdd)
i
2017/5/6
Vout
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Definition of Position (Rise)
VSD > VSG – Vt
VDG =< Vt
When Vout(Vd) – Vin(Vg) = Vt  You got it !!
vdd
vdd vdd
5
 [t  (td  tr )]  (

 t )  vt
8
2 ttran
(5/4)tr
Equation of Vout
vin
t
Equation of Vin
vout
Vt
Pmos C
Nmos
Vin
L
S
vdd-vt
td-(5/8)tr
2017/5/6
L
S
Vout
vt
vt
Chien-Nan Liu
C
vt
Imax
NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
Definition of Height (Rise)
T
Q
Ipeak
Is+Ic_internal
Energy  Q Ipeak
Q
P  I avgV   V
.lib store
T
P T
 Qint 
V
rise
Ic_load
CL
rise_ power
Total charge
= Qint + CL vdd
1
  T  I peak
2
Internal Output
energy loading
Known
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Experimental Result - clkinvx3
Input transition time = 0.9ns ; Output loading = 0.18pF
2017/5/6
(Rise)
HSPICE
Our method
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Experiment (C17)
ISCAS85:c17
Observe @ 24ns~26ns
ttran=0.1ns
A
A
B
1
CL=0.0076pF
1
1
1
E
A
C
2
0
4
1
out1
5
D
E
3
E
out2
6
CL=0.0006pF
ttran=0.4ns
VDD Waveform=Combine the current waveform from each gate
2017/5/6
Chien-Nan Liu
25ns~26.2ns
C1 7 Po w e r Su p p ly Cu rre n t Wa v e fo rm
5.00E-05
0.00E+00
25.024
-5.00E-05
25.312
25.6
25.888
26.176
-1.00E-04
-1.50E-04
Current
NCU Electrical Engineering Electronic Design Automation Laboratory
Experimental Result (C17)
Our Method
-2.00E-04
Hspice
-2.50E-04
-3.00E-04
-3.50E-04
-4.00E-04
-4.50E-04
2017/5/6
Time
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Automation Flow
Verilog Netlist
Construct Netlist Structure
Input Transition Time
Output Loading
Initial
Input and Output Situation
Value Changed Dump
Generate Triangle Waveform
(Base Position Height)
.lib information
Plot Waveform
Waveform
(.out)
2017/5/6
Chien-Nan Liu
SPICE
Our Method
NCU Electrical Engineering Electronic Design Automation Laboratory
Chien-Nan Liu
2017/5/6
SPICE vs Our Method
Case: C432
NCU Electrical Engineering Electronic Design Automation Laboratory
Experimental Results
Er(imax)
Er(pos)
Corr
C17
17.2786%
5ps
0.9584
C432
14.2248%
7.8776ps
0.9681
C499
7.1979%
2.9184ps
0.9889
C880
5.9526%
9.7755ps
0.9878
C1355
8.8771%
7.8163ps
0.9837
C1908
5.4637%
5.3673ps
0.9930
Er(imax): Peak Value Error Percentage
Er(pos): Peak Value Position Error
Corr: Correlation
2017/5/6
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
Summary of Gate-Level Method
Develop an analytic approach for current waveform
estimation
 Focus on gate-level simulation first
 Using existing library information
 Can improve current EDA tool
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
Outline
Introduction
High-Level Power Modeling
High-Level Current Waveform Modeling
 Gate-level current waveform estimation using existing information
 Macro-level current waveform estimation using neural network
Conclusion
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Motivation
Gate-level power/current estimation is the primary
approach in existing tools
For block-based designs (e.g. protected IP), you may not
have the internal information, like the gate-level netlist
 Only functional information (inputs/outputs) is available
We target to provide a high-level model that only need
“Inputs/Outputs” to estimate the current waveform
 Internal circuit information is only required at the
characterization process
Providing such current waveform model and functional
model will not explore the internal info. to customers
 Suitable for IP protection
2017/5/6
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Existing High-Level Method (1/2)
Transform the current waveform from time domain to
frequency domain by DCT (discrete cosine transform)
Regression
 Four parameters:
•
•
•
•
Decay factor D(k)
Amplitude A
Frequency ω
DC value I(0)
Bodapati, S.; Najm, F.N.;” High-Level current macro model for logic blocks”,
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Vol. 25, Issue 5, pp.837 – 855, May 2006.
Partition input vector pairs
to several groups by hamming distance
 Construct a model for each group
Drawback
 Choose template by logic block and hamming distance (not precise)
 Too many models for a circuit (how much is enough?)
 Lack of delay information (not accurate)
2017/5/6
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Existing High-Level Method (2/2)
Same hamming distance can cause different results.
 Hamming Distance cannot separate different kinds waveforms
very well due to different internal delays
hd=4
※ Hamming Distance (hd) = number of changed inputs
2017/5/6
Chien-Nan Liu
hd=4
NCU Electrical Engineering Electronic Design Automation Laboratory
Our Key Ideas
Levelize
 The arrival time of each gate will become more similar in a level
 Can consider the delay information
 May be easier to model the relationship between input transition
status and current waveform
Level 1
0
0
1
0
1
0
0
2017/5/6
Chien-Nan Liu
Level 2
2
2
Level 3
NCU Electrical Engineering Electronic Design Automation Laboratory
Neural Network Training
We still use Neural Network to build our model
Step 1: LILO model of each level
 Training input: Encoded primary input
 Training target: Each level LILO
Step 2: VDD model of each level
 Training input: Each level LILO and previous level LI
 Training target: Each level current waveform
Primy Input
1
Primy Input
2
Primy Input
3
LILO Model
of Each Level
2017/5/6
LILO’
LILO’
LILO’
1
2
3
VDD’
VDD’
VDD’
VDD
Waveform
VDD Model
of Each Level
Chien-Nan Liu
Why LILO Model ??
We want to use only
“Primy Input”
to estimate the transition status
of each internal level
NCU Electrical Engineering Electronic Design Automation Laboratory
Construction Flow
Verilog Code of Circuit
Levelize
Input Pattern Generation
Getting Current Waveform by
SPICE Simulation
Getting Value of Each Node by
Verilog Simulation
Dumping Current Waveform
Merging Input and Output
Training
DONE !!
2017/5/6
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Waveform Comparison (1/2)
c880
2017/5/6
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
Waveform Comparison (2/2)
Combine all waveforms from each level !!
c880
Total Vdd
Waveform
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
Chien-Nan Liu
2017/5/6
Waveforms with Different Shapes
NCU Electrical Engineering Electronic Design Automation Laboratory
Experimental Results
c17
4bits Adder
cu
c432
c880
#I
5
8
14
36
60
#O
2
5
11
7
26
#cell
6
21
52
86
306
#Level
3
4
4
5
6
#train
724
3000
5000
5000
5000
#test
724
12000
20000
20000
20000
ep,avg (%)
10.62
19.84
16.84
18.85
23.88
ep,std(%)
7.79
15.79
11.87
14.69
17.90
et,avg(%)
2.49
3.77
3.93
4.48
2.39
et,std(%)
4.39
4.37
3.75
7.25
7.57
edi/dt,avg (%)
18.57
29.58
20.71
23.56
26.91
edi/dt,std (%)
13.61
23.06
15.43
23.31
27.94
Corravg
0.98
0.92
0.96
0.90
0.93
avg : average
e : error
std : standard deviation p : peak
2017/5/6
Chien-Nan Liu
t : where peak occur
Corr : correlation
NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
Summary of Macro-Level Method
We propose a high level current model
 Used at high-level (only require input/output info.)
• Convenient to use
• Efficient computation
• Feasible for IP protection
 Constructed by neural network
 Only a single model for one logic block
 Can estimate the waveforms with different shapes
Chien-Nan Liu
NCU Electrical Engineering Electronic Design Automation Laboratory
2017/5/6
Conclusions
工欲善其事
必先利其器 !!
SoC is really a big challenge for IC designers
Power and Noise are two major challenges
Doing the things earlier can have higher impacts
More powerful tools are essential to solve those difficult
design problems
EDA – Where Electronics Begins
Welcome to join MOE CAD contest
http://www.ee.ncu.edu.tw/~cad_contest
Chien-Nan Liu