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We are developing a QPSK Demodulator for 70MHz carrier with 42.4515 Mbps data rate. For this,
we have developed a “hard limited COSTAS loop based design” using System generator tool from
ISE 14.4 version. So, this demodulation logic includes the Carrier recovery logic and data detection
logic.
The logic is running at 250 MHz sampling clock. The system generator logic was integrated with the
VHDL codes of ADC and DAC interface blocks.
We are using the Virtex 6 FPGA (Device: XC6VLX130T) integrated with an ADC (10 bit ADC10D1500) and 5 DACs (4 DACs are 1200MSPS 10 bit- AD9734 and one DAC is 2500MSPS
14bit - AD9739). The clock synthesizer we are using on board is the LMX2541 IC.
The ADC is running at 1 GHz frequency. So, only one channel data (I-channel) of 10 bits at 250 Mhz
is given to the FPGA for demodulation logic.
The clock distribution and Reset logics are designed on the board as follows:
The results of the QPSK demodulation logic were analyzed with practical modulated data (i.e. an
external QPSK modulated signal at 70 MHz carrier) and the observed results were fine as expected.
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That is, during the carrier recovery part of the demodulation logic- the output signal is exactly locked
to the variations of input carrier signal (70 MHz +- 200 KHz Doppler).
The board functionality was fine till recently. But suddenly, the recovered carrier output of the
logic (Hard limited COSTAS loop which is like a dual PLL circuit) became noisy and its
characteristics (like tracking range and acquisition ranges) got reduced from 200 KHz to 125
KHz with additional harmonics and spurs.
Then the problem was put up to the Hardware designer. Upon further debugging by the hardware
team, they found that synthesizer was not getting locked to generate the required 1GHz frequency so
they adjusted the charge pump currents (i.e. adjusting the LMX synthesizer related register settings)
and observed the lock for 1 GHz output from synthesizer.
Then we fed the unmodulated (plain) carrier signal from a signal generator (without noise) as input to
the ADC and implemented the same logic on FPGA. Even then the quality of the demodulation
logic’s output did not improve and observed the following problems:
(a) Several times the chip scope analyzer is in wait mode. After repeating the chip scope runs no. of
times with switch on off the board or rerun the chip scope or clean and re implement the project files
from ISE, etc..; then only the chip scope analyzer is running.
(b) Once the chip scope analyzer is running, intermittent PLL lock observed with noise harmonics
and spur signals present along with the locked carrier signal in the demodulation logic. Also, here we
observed the reduction of locking range and track range of the logic.
For ex; for input of 70 MHz plain carrier (top of the image- DAC1_IN_S1), the bottom locked signal
(DAC_IN_S1) observed.
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Similarly for 69.9MHz input signal, the following are the observations from Chip scope.
(Top image DAC-IN-S1 is the output signal for DAC1-IN-S1 input- bottom image).
Even unlock was observed for 70.2 MHz input (DAC1-IN-S1- top image)
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Sometimes, pressing of reset button affecting the spurs, noise floor and the lock of the output signal.
(c) Another point we observed that initially corresponding noise values under ‘No input signal’
condition (i.e. RF off from the signal generator) which were monitored on chip scope were in the
range of ‘30’h to ‘3D’h. But now, the same noise level values under this condition were observed to
be changed as ‘2C’h to ‘2E’h. The no. of bits for the input signal is 10 bit.
So, please clarify the possibilities of reasons for this change of performance.
Upon the suggestions by the Hardware designers, the LMX 2541 synthesizer charge pump current
settings were changed from 1.7mA to 3.2mA and observed there is no effect of this change on the
output quality and so reverted back the settings.
As we are in confusion of what was causing this sudden misbehavior, we need your support (both
synthesizer aspect and FPGA aspect).
So, kindly help us to come out of the problem at the earliest.
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