Download ADC Presentation

Analog to Digital Converters
Nyquist-Rate ADCs
 Flash ADCs
 Sub-Ranging ADCs
 Folding ADCs
 Pipelined ADCs
 Successive Approximation (Algorithmic) ADCs
 Integrating (serial) ADCs
Oversampling ADCs
 Delta-Sigma based ADCs
Fischer 08
1
Conversion Principles
Principle
Resolution
Speed
Cost
Serial
Conversion
High
>12 Bit
Low
<1kHz
Low
Successive
Approximation
Medium
8-14 Bit
Medium
<10MHz
Medium
Parallel
Conversion
Low
6-10 Bit
High
<100MHz
High
Delta
Sigma
High
>12 Bit
Low-Medium
<1MHz
Low
(analog only)
Fischer 08
2
ADC Architectures
 Flash ADCs: High speed, but large area and high power dissipation.
Suitable for low-medium resolution (6-10 bit).
 Sub-Ranging ADCs: Require exponentially fewer comparators than
Flash ADCs. Hence, they consume less silicon area and less power.
 Pipelined ADCs: Medium-high resolution with good speed. The tradeoffs are latency and power.
 Successive Approximation ADCs: Moderate speed with mediumhigh resolution (8-14 bit). Compact implementation.
 Integrating ADCs or Ramp ADCs: Low speed but high resolution.
Simple circuitry.
 Delta-Sigma based ADCs: Moderate bandwidth due to oversampling,
but very high resolution thanks to oversampling and noise shaping.
Fischer 08
3
Performance Limitations 1
System Definitions
 n-Bit ADC
 Sinusoidal Input
 Swing: ±1[V]
 fmax= ½ fconv
Thermal Noise Limitation
Clock Jitter (Aperture) Limitation
Normalized Noise Powers:
PNTH  2 kTReq f conv
fin=½fconv
1
PQuant  22 n
3
PN Jitter 
1
( f conv tJitter )2
2
Limiting Condition:
PQuant  PNTH
PQuant  PN Jitter
Maximum Resolution:
n
Fischer 08


1
1

log 


2 log 2
6
kTR
f
eq conv 

n


1
1

log 

log 2
 1.5  f conv tJitter 
4
Performance Limitations 2
Displays
Seismology
Audio
Sonar
Wireless
Ultra
Communications
Sound
Video
 Selection of ADC Architecture is driven by Application
Fischer 08
5
Parallel or Flash ADCs
Conceptual Circuit
Fischer 08
6
Sub-Ranging ADCs
Half-Flash or Two-Step ADC
Fischer 08
7
Folding ADCs
Principle Configuration
…
2n1 Sub-Ranges
Fischer 08
8
Folding Processor
Example: 2-Bit Folding Circuit
(2n-1+1)Io for n-Bit
2Io
Fischer 08
9
Successive Approx. ADCs
Concept
Fischer 08
Implementation
10
DAC Realization 1
(Voltage Mode)
Fischer 08
11
DAC Realization 2
Spread Reduction through R-2R Ladder
Fischer 08
12
DAC Realization 3
Charge-Redistribution Circuit
valid only during f2
Pros
 Insensitive w.r.t. Op-amp Gain
 Offset (1/f Noise) compensated
Fischer 08
Cons
 Requires non-overlapping Clock
 High Element Spread  Area
 Output requires S&H
13
DAC Realization 4
Spread Reduction through capacitive Voltage Division
Example: 8-Bit ADC
valid only during f2
7
1 3

Vout  Vref   bi 2( i 4 )   bi 2( i 8) 
i 4
16 i 0

Spread=2n/2
Fischer 08
14
DAC Realization 5
Charge-Redistribution Circuit with Unity-Gain Amplifier
Example: 8-Bit ADC
16/15C
7
1 3

Vout  Vref   bi 2( i 4 )   bi 2( i 8) 
i 4
16 i 0

Pros
 Voltage divider reduces spread
 Buffer  low output impedance
 No clock required
Fischer 08
Amplifier Input Cap.
Spread=½2n/2
Cp  Gain Error: єG=-Cp/16C
Cons
 Parasitic cap causes gain error
 High Op-amp common mode input required
 No amplifier offset compensation
15
DAC8 with Unity-Gain Amplifier
Sub-range Output (4 LSBs)
0
0.5u 1u
Fischer 08
1.5u
2u
2.5u 3u
3.5u
4u
4.5u
5u
Amplifier Output
5.5u
6u 6.5u
0
0.5u 1u
1.5u
2u
2.5u
3u
3.5u
4u 4.5u
5u
5.5u
6u 6.5u
16
DAC Realization 6
Current Mode Implementation
Fischer 08
17
Current Cell & Floor Plan
Symmetrical Current Cell Placement
Unit Current Cell
Array of 256 Cells
R
Iout
Current summing Rail
Switching
Devices
Cascode
Current
Source
Fischer 08
18
DAC Implementation
Layout of 10-Bit Current-Mode DAC (0.5mm CMOS)
Current summing Rails
Fischer 08
19
Modified SA Algorithm 1
Idea: Replace DAC by an Accumulator
 Consecutively divide Ref by 2
Fischer 08
20
Modified SA Algorithm 2
Idea: Maintain Comparator Reference (½ FS=Gnd)
 Double previous Accumulator Output
First cycle only
Accumulator
Fischer 08
21
SC Implementation
SC Implementation of modified SA ADC
Fischer 08
22
Timing Diagram
Fischer 08
23
Offset Compensated Circuit
Offset Compensated SC Implementation
Fischer 08
24
Building Blocks 1
Transconductance Amplifier
Fischer 08
DC Gain
77 dB
Gainbandwidth
104 MHz @
CL= 1.5 pF
Power
1.3 mW
Output
Swing
4 V p-p
25
Building Blocks 2
Latched CMOS Comparator
Fischer 08
Power
0.5 mW
Resolution
> 0.5 mV
Settling Time
3 ns
26
Layout of 8-Bit ADC
165 mm (0.5 mm CMOS)
Fischer 08
27
Spice Simulation (Bsim3)
8-Bit ADC: fclk=10MHz  fconv=1.25MHz
Fischer 08
28
Pipelined ADCs
Pipelined modified SA or Algorithmic ADC
Pros
 Offset (1/f Noise) compensated
 Minimum C-spread
 One conversion every clock period
Fischer 08
Cons
 Matching errors  digital correction for n>8
 Clock feed-through very critical
 High amplifier slew rate required
29
Integrating or Serial ADCs
Dual Slope ADC Concept
Prop. to Input Ramp
Using 2N/k samples requires Ref = FS/k
 reduced Integrator Constant
(Element Spread)
Fischer 08
Constant Ramp
N represents digital
equivalent of analog Input
30
SC Dual-Slope ADC
10-Bit Dual-Slope ADC
Fischer 08
31
ADC Testing
Types of Tests
 Static Testing
 Dynamic Testing
Input
Circuit
Under Test
Output
Clock
 In static testing, the input varies slowly to reveal the actual code
transitions.  Yields INL, DNL, Gain and Offset Error.
 Dynamic testing shows the response of the circuit to rapidly
changing signals. This reveals settling errors and other dynamic
effects such as inter-modulation products, clock-feed-trough, etc.
Fischer 08
32
Performance Metrics 1
Static Errors
IDEAL ADC
Error Types
 Offset
 INL
 Gain
 Missing Codes
 DNL
Fischer 08
33
Performance Metrics 2
Frequency Domain Characterization
SNR  10 log 10
PSignal
PNoise
Amplitude
SNDR  10 log 10
PSignal
PNoise  PHarm
SNDRmax [dB]
3
 log 10 ( )
10
2
ENOB 
2 log 10 2
fsig
Fischer 08
Ideal n-Bit ADC:
SNR = 6.02 x n + 1.76 [dB]
34
ADC Error Sources
Static Errors




Element or Ratio Mismatches
Finite Op-amp Gain
Op-amp & Comparator Offsets
Deviations of Reference
Dynamic Errors





Fischer 08
Finite (Amplifier) Bandwidth
Op-amp & Comparator Slew Rate
Clock Feed-through
Noise (Resistors, Op-amps, switched Capacitors)
Intermodulation Products (Signal and Clock)
35
Static Testing
Servo-loop Technique
 Comparator, integrator, and ADC under test are in negative feedback loop
to determine the analog signal level required for every digital code transition.
 Integrator output represents equivalent analog value of digital output.
 Transition values are used to generate input/output characteristic of ADC,
which reveals static errors like Offset, Gain, DNL and INL.
Fischer 08
36
Dynamic Testing
Test Set-up
Types of Dynamic Tests
 Histogram or Code-Density Test
 FFT Test
 Sine Fitting Test
Fischer 08
37
Histogram or Code-Density Test
 DNL appears as deviation of
bin height from ideal value.
 Integral nonlinearity (INL) is
cumulative sum (integral) of
DNL.
 Offset is manifested by a
horizontal shift of curve.
 Gain error shows as
horizontal compression or
decompression of curve.
Fischer 08
38
Histogram Test
Pros and Cons of Histogram Test
 Histogram test provides information on each code
transition.
 DNL errors may be concealed due to random noise in
circuit.
 Input frequency must be selected carefully to avoid
missing codes (fclk/fin must be non-integer ratio).
 Input Swing is critical (cover full range)
 Requires a large number of conversions (o 2n x 1,000).
Fischer 08
39
Simulated Histogram Test
8-Bit SA ADC with 0.5%
Ratio Error and 5mV/V
Comparator Offset
Fischer 08
40
FFT Test
Pros and Cons of FFT Test
 Offers quantitative Information on output Noise, Signalto-Noise Ratio (SNR), Spurious Free Dynamic Range
(SFDR) and Harmonic Distortion (SNDR).
 FFT test requires fewer conversions than histogram
test.
 Complete characterization requires multiple tests with
various input frequencies.
 Does not reveal actual code conversions
Fischer 08
41
Simulated FFT Test
8-Bit SA ADC with 0.5% Ratio Error and 5mV/V Comparator Offset
SNDR=49 dB
SFDR=60 dB
Fischer 08
 ENOB=7.85
42