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ELEC 2200-002
Digital Logic Circuits
Fall 2015
Switching Algebra (Chapter 2)
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
http://www.eng.auburn.edu/~vagrawal
[email protected]
Fall 2015, Sep 30 . . .
ELEC2200-002 Lecture 4
1
Switching Algebra
A Boolean algebra, where
 Set K contains just two elements, {0, 1}, also
called {false, true}, or {off, on}, etc.
 Two operations are defined as, + ≡ OR,
· ≡ AND.
+
0
1
·
0
1
0
0
1
0
0
0
1
1
1
1
0
1
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ELEC2200-002 Lecture 4
2
Claude E. Shannon (1916-2001)
http://www.kugelbahn.ch/sesam_e.htm
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ELEC2200-002 Lecture 4
3
Shannon’s Legacy
A Symbolic Analysis of Relay and Switching
Circuits, Master’s Thesis, MIT, 1940. Perhaps
the most influential master’s thesis of the 20th
century.
An Algebra for Theoretical Genetics, PhD
Thesis, MIT, 1940.
Founded the field of Information Theory.
C. E. Shannon and W. Weaver, The
Mathematical Theory of Communication,
University of Illinois Press, 1949. A “must read.”
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ELEC2200-002 Lecture 4
4
Switching Devices
Electromechanical relays (1940s)
Vacuum tubes (1950s)
Bipolar transistors (1960 - 1980)
Field effect transistors (1980 - )
Integrated circuits (1970 - )
Nanotechnology devices (future)
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ELEC2200-002 Lecture 4
5
Example: Automobile Ignition
Engine turns on when
Ignition key is applied AND
Car is in parking gear OR
Brake pedal is on
AND
Seat belt is fastened OR
Car is in parking gear
Fall 2015, Sep 30 . . .
ELEC2200-002 Lecture 4
6
Switching logic
Parking gear
Seat belt
Key
Brake pedal
Motor
Battery
Fall 2015, Sep 30 . . .
Parking gear
ELEC2200-002 Lecture 4
7
Define Boolean Variables
Parking gear
Key
Seat belt
P = {0, 1}
S = {0, 1}
Brake pedal
Parking gear
K = {0, 1}
M = {0, 1}
B = {0,1}
P = {0, 1}
Motor
Battery
0 means switch “off” or “open”
1 means switch “on” or “closed”
Fall 2015, Sep 30 . . .
ELEC2200-002 Lecture 4
8
Write Boolean Function
Parking gear
Key
Seat belt
P = {0, 1}
S = {0, 1}
Brake pedal
Parking gear
K = {0, 1}
M = {0, 1}
B = {0,1}
P = {0, 1}
Motor
Battery
Ignition function:
M
Fall 2015, Sep 30 . . .
= K AND (P OR B) AND (S OR P)
= K(P + B)(S + P)
ELEC2200-002 Lecture 4
9
Simplify Boolean Function
M =
K AND (P OR B) AND (S OR P)
=
K(P + B)(S + P)
=
K(P + B)(P + S)
Commutativity
=
K (P + B S)
Distributivity
Fall 2015, Sep 30 . . .
ELEC2200-002 Lecture 4
10
Construct an Optimum Circuit
M = K (P + B S)
Key
Parking gear
P = {0, 1}
Brake pedal
Seat belt
K = {0, 1}
M = {0,1}
B = {0,1}
S = {0, 1}
Motor
Battery
This is a relay circuit.
Earlier logic circuits, even computers,
were built with relays.
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ELEC2200-002 Lecture 4
11
Implementing with Relays
An electromechanical relay contains:
Electromagnet
Current source
A switch, spring-loaded, normally open or closed
Switch has two states, open (0) or closed (1).
The state of switch is controlled by “not
applying” or “applying” current to
electromagnet.
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12
One Switch Controlling Other
Switches X and Y are normally open.
Y cannot close unless a current is applied
to X.
Y
X
Y=X
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13
Inverting Switch
Switch X is normally closed and Y is
normally open.
Y cannot open unless a current is applied
to X.
Y
X
Y=X
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ELEC2200-002 Lecture 4
14
Boolean Operations
AND – Series connected relays.
OR – Parallel relays.
A
F
A
B
B
F=AB
Fall 2015, Sep 30 . . .
F
F=A+B
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15
Complement (Inversion)
A
F
F
A
B
F=A
F=A+B
=A· B
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ELEC2200-002 Lecture 4
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Relay Computers
Conrad Zuse (1910-1995)
Z1 (1938)
Z3 (1941)
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Electronic Switching Devices
Electron Tube
Fleming, 1904
de Forest, 1906
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Point Contact Transistor
Bardeen, Brattain, Shockley, 1948
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Transistor, 1948
The thinker, the tinkerer, the visionary and the transistor
John Bardeen, Walter Brattain, William Shockley
Nobel Prize, 1956
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ELEC2200-002 Lecture 4
19
Bell Laboratories, Murray Hill,
New Jersey
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Bipolar Junction Transistor (BJT)
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ELEC2200-002 Lecture 4
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Field Effect Transistor (FET)
a.k.a.
metal oxide
semiconductor
(MOS) FET.
(metal
oxide)
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23
Integrated Circuit (1958)
Jack Kilby (1923-2005), Nobel Prize, 2000
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MOSFET (Metal Oxide Semiconductor
Field Effect Transistor)
Drain
Drain
Short
or
Open
Gate
Short
or
Open
Gate
VGS
VGS
Source
Source
NMOSFET
PMOSFET
VGS = 0, open
VGS = high, short
VGS = 0, short
VGS = high, open
Reference:
R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design,
Third Edition, McGraw Hill.
Fall 2015, Sep 30 . . .
ELEC2200-002 Lecture 4
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NMOSFET NOT Gate (Early Design)
Power supply
VDD volts
w.r.t. ground
Problem: When A = 1,
current leakage causes
power dissipation.
A: Boolean variable
Solution: Complementary
MOS design proposed by
A = VDD volts; 1, true, on
A = 0 volt; 0, false, off
A
A
Ground = 0 volt
Fall 2015, Sep 30 . . .
ELEC2200-002 Lecture 4
F. M. Wanlass and C.-T. Sah,
“Nanowatt Logic Using FieldEffect Metal-Oxide
Semiconductor Triodes,”
International Solid State Circuits
Conference Digest of Technical
Papers, Feb 20, 1963, pp. 32-33.
26
CMOS Circuit
Wanlass, F. M. "Low Stand-By Power Complementary Field Effect Circuitry.“
U. S. Patent 3,356,858 (Filed June 18, 1963. Issued December 5, 1967).
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ELEC2200-002 Lecture 4
27
CMOS NOT Gate (Modern Design)
Power supply
VDD = 1 volt; voltage depends on technology.
A = VDD = 1 volt is state “1”
A = GND = 0 volt is state “0”
Truth Table
A
Electrical
Circuit
Fall 2015, Sep 30 . . .
A
GND
Ground
A
A
0
1
1
0
A
A
Symbol
Boolean Function
ELEC2200-002 Lecture 4
28
CMOS Logic Gate: NAND
VDD
Electrical
Circuit
A
Boolean Function
F
B
Symbol
Truth Table
A
B
F
0
0
1
0
1
1
1
0
1
1
1
0
A
F
B
GND
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ELEC2200-002 Lecture 4
29
CMOS Logic Gate: NOR
Electrical
Circuit
VDD
Boolean Function
Symbol
Truth Table
A
F
B
A
B
F
0
0
1
0
1
0
1
0
0
1
1
0
A
F
B
GND
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CMOS Logic Gate: AND
Boolean Function
Truth Table
Symbol
A
A
F
B
Fall 2015, Sep 30 . . .
F
≡
B
ELEC2200-002 Lecture 4
F
A
B
F
0
0
0
0
1
0
1
0
0
1
1
1
31
CMOS Logic Gate: OR
Boolean Function
Truth Table
Symbol
A
A
F
B
Fall 2015, Sep 30 . . .
F
≡
F
B
ELEC2200-002 Lecture 4
A
B
F
0
0
0
0
1
1
1
0
1
1
1
1
32
CMOS Gates
Number of transistors
Logic function
1 or 2 inputs
N inputs
NOT
2
-
AND
6
2N + 2
OR
6
2N + 2
NAND
4
2N
NOR
4
2N
Fall 2015, Sep 30 . . .
ELEC2200-002 Lecture 4
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Optimized Ignition Logic
M = K (P + B S)
= KP + KBS
K
KP
P
M
B
S
KBS
3 gates, 20 transistors. Can we reduce transistors?
Fall 2015, Sep 30 . . .
ELEC2200-002 Lecture 4
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Further Optimization
M = K (P + B S) = KP + KBS
NAND gates
4+6 transistors
K
(Distr. law)
= KP + KBS
(Theorem 3, involution)
= KP · KBS
(De Morgan’s theorem)
KP
P
M
B
S
KBS
3 gates, 14 transistors.
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Digital Systems
DIGITAL
CIRCUITS
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Digital Logic Design
Representation of switching function:
Truth table
Canonical forms
Karnaugh map
Logic minimization: Minimize number of
literals.
Technology mapping: Implement logic
function using predesigned gates or
building blocks from a technology library.
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ELEC2200-002 Lecture 4
40
Truth Table
Truth table is an exhaustive description of a switching
function. Contains 2n input combinations for n variables.
Example: f(A,B,C) = A B +A C + AC
n Input variables, n = 3
2n
= 8 rows
Fall 2015, Sep 30 . . .
Output
A
B
C
f(A,B,C)
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
1
ELEC2200-002 Lecture 4
41
How Many Switching Functions?
Output column of truth table has length 2n
for n input variables.
2n
It can be arranged in 2 ways for n
variables.
Example: n = 1, single variable.
Input
Fall 2015, Sep 30 . . .
Output functions
A
F1(A)
F2(A)
F3(A)
F4(A)
0
0
0
1
1
1
0
1
0
1
ELEC2200-002 Lecture 4
42
Definitions
Boolean variable: A variable denoted by a
symbol; can assume a value 0 or 1.
Literal: Symbol for a variable or its
complement.
Product or product term: A set of literals,
ANDed together. Example, a bc.
Cube: Same as a product term.
Sum: A set of literals, Ored together.
Example, a + b +c.
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43
More Definitions
SOP (sum of products): A Boolean function
expressed as a sum of products.
Example: f(A,B,C) = A B +A C + AC
POS (product of sums): A Boolean function
expressed as a product of sums.
Example:
f(A,B,C) = (A +B +C) (A + B +C) ( A +B + C)
Fall 2015, Sep 30 . . .
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44
Minterm
A product term in which each variable is present either in
true or in complement form.
For n variables, there are 2n unique minterms.
Minterm
Product
m0
A BC
m1
A B C
A BC
m2
m3
m4
A B C
A BC
m6
A B C
A B C
m7
A B C
m5
Fall 2015, Sep 30 . . .
ELEC2200-002 Lecture 4
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Value of minterm
Minterms are Canonical Functions
1
m0
m1
m2
m3
m4
m5
m6
m7
0
000
001
010
011
100
101
110
111
Input
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ELEC2200-002 Lecture 4
46
Canonical SOP Form
a.k.a. Disjunctive Normal Form (DNF)
Truth table with row numbers
A Boolean function expressed as a sum of minterms.
Example: f(A,B,C) = A B +A C + AC
= ABC +ABC + ABC + ABC + ABC
= m1+m3+m4+m6+m7 =  m(1, 3, 4, 6, 7)
Row No.
A
B
C
f(A,B,C)
0
0
0
0
0
1
0
0
1
1
2
0
1
0
0
3
0
1
1
1
4
1
0
0
1
5
1
0
1
0
6
1
1
0
1
7
1
1
1
1
Fall 2015, Sep 30 . . .
ELEC2200-002 Lecture 4
47
Maxterm
A summation term in which each variable is present
either in true or in complement form.
For n variables, there are 2n unique maxterms.
Maxterm
M0
A+B+C
M1
A + B +C
A +B + C
M2
M3
M4
A +B +C
A + B + C
M6
A + B +C
A +B + C
M7
A + B + C
M5
Fall 2015, Sep 30 . . .
Sum
ELEC2200-002 Lecture 4
48
Canonical POS Form
a.k.a. Conjunctive Normal Form (CNF)
Truth table with row numbers
A Boolean function expressed as a product of maxterms.
Example: f(A,B,C) = A B +A C + AC
= (A + B + C)(A +B + C)(A + B +C)
= M0 M2 M5 =  M(0, 2, 5)
Row No.
A
B
C
f(A,B,C)
0
0
0
0
0
1
0
0
1
1
2
0
1
0
0
3
0
1
1
1
4
1
0
0
1
5
1
0
1
0
6
1
1
0
1
7
1
1
1
1
Fall 2015, Sep 30 . . .
ELEC2200-002 Lecture 4
49
Canonical Forms are Unique
A canonical form completely defines a Boolean
function. That is, for every input the canonical
form specifies the value of the function.
To determine canonical form:
Construct truth table and sum minterms
corresponding to 1 outputs, or multiply maxterms
corresponding to 0 outputs.
Alternatively, use Shannon’s expansion theorem
(see Section 2.2.3, page 101).
Two Boolean functions are identical if and only if
their canonical forms are identical.
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Why Generate Canonical Form?
Example: Are the following Boolean
Functions Identical?
F1  A B D  A B D  A C D
F2  A C D  A B D  B C D
F3  A B C D  B D
Generate canonical forms, e.g., minterms,
and compare.
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Algebraic Procedure
Expand each term to contain all variables
Remember
Postulate 6: Complement
aa 1
aa  0
Postulate 2: Identity elements
a + 0 = a, 0 is identity element for +
a · 1 = a, 1 is identity element for dot (·)
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F1  ABD  ABD  ACD
 ABD(C  C)  ABD(C  C)  ACD(B  B)
 ABCD  ABCD  ABCD  ABCD  ABCD  ABCD
 m7  m5  m15  m13  m11

 m(5, 7, 11, 13, 15 )
Similarly,
 m(5, 7, 11, 13, 15 )
F3   m(5, 7, 11, 13, 15 )
F2 
Hence , three functions are identical.
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53
Karnaugh Map
1952: Edward M. Veitch invented a
graphical procedure for digital circuit
optimization.
1953: Maurice Karnaugh perfected the
map procedure:
“The Map Method for Synthesis of Combinational
Logic Circuits,” Trans. AIEE, pt I, 72(9):593-599,
November 1953.
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ELEC2200-002 Lecture 4
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Karnaugh Map: 2 Variables, A, B
A=0
Unit
Hamming
distance
between
adjacent
cells
B=0
10
00
m0
Each cell is
a minterm
m2
11
01
B=1
m1
Fall 2015, Sep 30 . . .
A=1
m3
ELEC2200-002 Lecture 4
m3 = AB = 11
(numerical
interpretation)
55
Representing a Function
A=0
0
A=1
2
1
B=0
m0
m2
1
3
Place 1 in cells
corresponding to
minterms in canonical form.
For example, see
F = A B + AB
represented on the left.
1
B=1
m1
m3
Truth Table
A
B
F
0
0
0
0
1
0
1
1
Fall 2015, Sep 30 . . .
ELEC2200-002 Lecture 4
0
1
1
1
56
Grouping Adjacent Minterms
A=0
0
A=1
B=0
m0
m2
1
3
B=1
m1
1
Adjacent cells differ in
one variable, which is
eliminated.
1
For example,
F = A B + AB
= A(B +B) = A
2
m3
Product term A
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Karnaugh Map Minimization
Canonical SOP form represented on map
Example: F = AB + A B +A B
Find minimal cover (fewest groups of largest sizes),
F=A+B
A=0
A=1
product A
A
1
B=0
m0
B=1
m2
Fall 2015, Sep 30 . . .
B
1
1
m1
F
product B
m3
ELEC2200-002 Lecture 4
58
Karnaugh Map: 3 Variables, A, B, C
A
0
2
000
1
C
6
010
110
3
001
4
7
011
100
5
111
101
B
Check unit Hamming distance between adjacent cells.
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ELEC2200-002 Lecture 4
59
Synthesizing a Digital Function
Start with specification.
Create a truth table from specification.
Minimize (SOP with fewest literals):
Either write canonical SOP
Reduce using postulates and theorems
Or find largest cubes from Karnaugh map
Minimized SOP gives a two-level AND-OR
circuit.
NAND or NOR circuit for CMOS technology can
be found using de Morgan’s theorem.
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Example: Multiplexer
Inputs: A, B, C
Output: F
Function:
F = A, when C = 1
F = B, when C = 0
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3-Input Function: Multiplexer
A
BC
Truth Table
row
A
B
C
F
0
0
0
0
0
0
2
1
3
1
6
7
C
1
1
1
0
0
1
0
2
0
1
0
1
B
3
0
1
1
0
F = A C + BC
4
1
0
0
0
5
1
0
1
1
6
1
1
0
1
7
1
1
1
1
Fall 2015, Sep 30 . . .
4
5
1
A C
A
C
F
B
ELEC2200-002 Lecture 4
62
Technology Optimization
A
F = A C + BC
C
F
2 + 6 + 6 + 6 = 20 transistors
B
A
C
F
B
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Optimized Multiplexer
A
X
C
F
B
Y
F  X  Y  XY
from de Morgan' s theorem
X
A
C
F
B
Fall 2015, Sep 30 . . .
Y
2 + 4 + 4 + 4 = 14 transistors
ELEC2200-002 Lecture 4
64
Karnaugh Map: 4 Variables, A, B, C, D
A
C
0
4
12
8
1
5
13
9
3
7
15
11
2
6
14
10
D
B
Check unit Hamming distance between adjacent cells.
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65
Adjacency of Edge Cells
3
11
2
10
2
9
6
1
14
8
10
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0
0
4
12
8
ELEC2200-002 Lecture 4
66
Reexamine Three Functions
from Slide 48
Example: Are the following Boolean
Functions Identical?
F1  A B D  A B D  A C D
F2  A C D  A B D  B C D
F3  A B C D  B D
This time generate Karnaugh maps, and
compare.
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ELEC2200-002 Lecture 4
67
Karnaugh Map of F1
F1  A B D  A B D  A C D
C
0
4
12
8
1
5
13
9
3
7
2
6
.
F1 = Σm(5,
7, 11, 13, 15)
Fall 2015, Sep 30 . . .
A
1
1
15
1
1
14
11
D
1
10
B
ELEC2200-002 Lecture 4
68
Karnaugh Map of F2
F2  A C D  A B D  B C D
C
.
A
0
4
12
8
1
5
13
9
3
7
2
6
1
1
15
1
1
14
11
D
1
10
B
F2 = Σm(5, 7, 11, 13, 15) ⇒ F1 and F2 cover same area on map.
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69
Karnaugh Map of F3
F3  A B C D  B D
A
0
4
12
8
1
5
13
9
1
C
3
7
2
6
1
1
15
11
14
10
1
D
1
B
F3 .= Σm(5, 7, 11, 13, 15) ⇒ F1, F2 and F3 cover exactly the
same area on map, hence, they are identical.
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ELEC2200-002 Lecture 4
70
Ignition Function
M = K AND (P OR B) AND (S OR P)
= K(P + B)(S + P)
Fall 2015, Sep 30 . . .
Minterm
K
P
B
S
M
0
0
0
0
0
0
1
0
0
0
1
0
2
0
0
1
0
0
3
0
0
1
1
0
4
0
1
0
0
0
5
0
1
0
1
0
6
0
1
1
0
0
7
0
1
1
1
0
8
1
0
0
0
0
9
1
0
0
1
0
10
1
0
1
0
0
11
1
0
1
1
1
12
1
1
0
0
1
13
1
1
0
1
1
14
1
1
1
0
1
15
1
1
1
1
1
ELEC2200-002 Lecture 4
71
Karnaugh Map: M(K, P, B, S)
K
B
.
Fall 2015, Sep 30 . . .
0
4
12
1
5
13
3
7
15
2
6
14
1
1
1
1
8
9
11
1
S
10
P
ELEC2200-002 Lecture 4
72
Karnaugh Map: Minimum Cover
K
B
.
Fall 2015, Sep 30 . . .
0
4
12
1
5
13
3
7
15
2
6
14
1
1
1
1
8
KP
9
11
1
S
10
KBS
P
ELEC2200-002 Lecture 4
73
Minimized Function
M = KP + KBS
K
P
M
B
S
Fall 2015, Sep 30 . . .
ELEC2200-002 Lecture 4
74
Using Inverting Gates
Because They Need Fewer Transistors
M = KP + KBS
= KP · KBS
Using de Morgan’s Theorem
K
P
M
B
S
Fall 2015, Sep 30 . . .
ELEC2200-002 Lecture 4
75
Karnaugh Map on the Web
http://www.ee.calpoly.edu/media/uploads/resources/KarnaughExplorer_1.html
Fall 2015, Sep 30 . . .
ELEC2200-002 Lecture 4
76
Minterm Clusters, Cubes or Products
A
0
ABC D
4
12
8
5
13
9
ABD
1
1
1
BCD
3
7
1
15
11
1
C
2
6
D
14
1
10
1
1
AC
B
Larger clusters are products with fewer variables.
Fall 2015, Sep 30 . . .
ELEC2200-002 Lecture 4
77
Product P1  ABC D  A  B  C  D
VDD = 1 volt
P1
A
Signals are voltages
w.r.t. GROUND
A = 0 or 1 volt
B = 0 or 1 volt
C = 0 or 1 volt
D = 0 or 1 volt
B
C
D
NMOS transistors
PMOS transistors
A
B
C
D
P1 =
0 or 1 volt
GROUND
More variables in a product mean more transistors (hardware).
Fall 2015, Sep 30 . . .
ELEC2200-002 Lecture 4
78
Product P2  AC  AC
A
P2
C
VDD = 1 volt
Signals are voltages
A
w.r.t. GROUND
A = 0 or 1 volt
B = 0 or 1 volt
C
C = 0 or 1 volt
D = 0 or 1 volt
P1 =
0 or 1 volt
GROUND
Fewer variables in a product mean fewer transistors (hardware).
Fall 2015, Sep 30 . . .
ELEC2200-002 Lecture 4
79
Observations
A larger minterm cluster is a product with
fewer variables; requires fewer transistors.
Each gate input needs two transistors.
Smaller number of clusters is more
efficient:
Fewer gates to generate products.
Fewer inputs for the OR gate to produce the
function.
Direct minterm implementation is most
inefficient.
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