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Semiconductor Packaging Technologies for Miniaturization and High Pin Count
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Semiconductor Packaging Technologies for Miniaturization
and High Pin Count
Ichiro Anjo
Asao Nishimura
Ryo Haruta
OVERVIEW: Electronic information device designers today aim to develop
products that can be casually operated on the move with the mobility needed
for nomadic operation. Pocket size is the immediate problem, with wristwatch
size the target for the future. Realization of this small size and light weight
is not only a matter of making semiconductor devices that are highly
integrated or highly functional; also essential are fundamental reductions
in assembly area and physical volume. At present the extremely miniaturized
chip-scale package (CSP) is being developed as a technology solution for
semiconductor packages. This technology is especially effective for the highpin count category. As the next-generation technology, other technologies
are under consideration including the three dimensional assembly package,
which has the highest integration level among packages, and flip-chip
technology, which permits assembly at actual chip dimensions. However,
development of optimum package technology cannot be executed unless it
matches the user’s assembly designs including assembly substrate material
and interconnect rules. Thus we must enhance development collaboration
with users in the future to achieve optimum assembly solutions.
INTRODUCTION
SMALL size and light weight not only determine the
product value of electronic information devices, they
have come to be considered essential requirements.
Especially for such products as typified by mobile
communications terminals and digital consumer
devices, the so-called mobile field, this is particularly
significant. Increasing the integration level of
semiconductors will of course help realize smaller size
and lighter weight, but selection of assembly
technology can be said to be the key to gaining
competitive advantage in smaller size and lighter
weight.
Questions such as how to make the semiconductor
package smaller and lighter, and how to assemble for
higher density are strongly related to cost and
reliability. Thus the selection of a package technology
suitable for each system differs for every system.
Advances in recent years in package materials
technology and design technology have made it
possible to design a large variety of packages, and a
large number of package variations have actually been
proposed. It can be said that this is truly an era of
package innovation.
In this paper we will discuss the package
technologies that we think will be used in the near
future as standard products from among the many
choices available, and also package technology now
being developed for future system solutions.
PACKAGE FUNCTIONS
Formerly lead-type package technology was the
foundation of package technology. At that time, the
main purpose of the package was to protect the
semiconductor device. Prevention of thermal stress
and moisture-induced corrosion after attachment to the
circuit board were the most important problems. Since
then, advances in package encapsulation materials,
chip-surface protection materials, and packagestructure design technology have greatly improved
resistance to heat and moisture - and packages have
become smaller and thinner 1).
Now is the time for change to meet the new needs
of higher-pin (lead) count and higher speed as the
functions required of the package. Package terminals
are arranged around the periphery of the peripheral
lead-type package, causing the package area to grow
with the square of the number of leads as the pin count
Hitachi Review Vol. 48 (1999), No. 2
95
3.0
Leadframe-type package
Board connect pitch
2.5
DIP
2.0
Multichip package
Area-array type package
1.5
BGA
SOP
1.0
CSP
QFP
0.5
Limit for testing
and assembly
Flip chip
TCP
COB
0
10
DIP: dual inline package
TCP: tape carrier package
100
Package integration level (leads per cm2)
SOP: small outline package
BGA: ball grid array
QFP: quad flat package
CSP: chip scaile package
1,000
COB: chip on board
Fig. 1— Packaging Technology Progresses to Smaller Sizes.
Package form is rapidly migrating from leadframe type to area type; at present the CSP type is
making headway toward widespread acceptance. For the future the key is overcoming difficulties in
testing and assembly caused by fine pitch, and we believe progress will be made toward flip-chip
assembly and multichip packages.
QFP: quad flat package
CSP: chip scale package
600
500
Package area (mm2)
increases, as shown in Fig. 2. Thus for high pin count
packages with more than 250 pins, the package size
becomes much larger than the chip size, and small size
becomes difficult from the standpoint of assembly
technology and production technology.
However, with an area-array package on which the
terminals are arranged on the rear surface of the
package in a rectangular grid, the package area is
proportional to the number of pins. Therefore, an areaarray type package is essential to realize small size in
multipin packages.
Contrarily, with low pin count packages, use of an
area-array type package is not very effective in
reducing area compared with a peripheral-lead type
package, and sufficient benefits are not obtained to
justify use of a new-configuration package. However,
we think that higher-speed requirements will rapidly
grow, and this will lead to a change in conditions.
Inductance and capacitance of leads inside the package
are a cause of signal noise, and this will create a need
to shorten lead (interconnect) length inside the package
(see Fig. 3).
To shorten interconnect length within the package,
Peripheral-lead type
QFP
400
0.5-mm pitch
300
200
Area-array type
CSP
100
0.5-mm pitch (2 rows)
0.8-mm pitch (4 rows)
0
0
50
100
150
200
Pin count or ball count
250
300
Fig. 2—Comparison of Package Sizes for Area-Array Type and
Peripheral-Lead Type.
Peripheral-lead type package area is proportional to the square
of the pin count and package area becomes large, but areaarray type package area is merely proportional. Thus the
greater the number of terminals the more effective the areaarray type becomes for smaller size.
Semiconductor Packaging Technologies for Miniaturization and High Pin Count
Capacitance (pF) Self inductance (nH)
area-array type packages are better than peripherallead type packages because lead length can be reduced
from the bonding pad on the chip to the connection
with the circuit board. Thus we believe that even lowpin count packages will migrate to area-array type
packages. Actually, there are now in general use ball
grid array (BGA) having solder balls with coarse
pitches of 1 mm or more as connection leads that make
for ease of assembly.
If we make an even more detailed study of the
purpose of packages, we find that terminal pitch is the
most important element when designing area array
packages. In general, when the pitch is large the
package size becomes large, and when the pitch is
small connection to the board becomes difficult.
We believe that today’s interconnect rules are less
than 1 µm for chips, but in general several hundred
micrometers on assembly circuit boards. Packages
serve as scale converters between the chip and the
board. Pads for connection to the chip require a
spacing of about 100 µm; lands for connection to the
board require a spacing of 0.5 mm or larger.
Technologically it is possible to assemble terminals
with a fine pitch of about 0.3 mm directly to a board,
but when we consider cost and reliability in seeking
an optimum system solution, it is better to perform
assembly through the medium of a package.
Thus the purpose of a package is not only to protect
a chip; we must also pay attention to its function as a
scale converter. Formerly packaging technology was
technology to make a container to encapsulate a
semiconductor device. Now it is a means to provide
the optimum solution in combination with the
TSOP
BGA
Design index
CSP
10
100 Mbit/s × pins
5
250 Mbit/s × pins
800 Mbit/s × pins
0
1990
1995
2000
100 Mbit/s × pins
1.0
0.5
800 Mbit/s × pins
0
1990
1995
2000
Year
TSOP: thin small outline package BGA: ball grid array
Fig. 3—Package Electrical Characteristics.
Package internal self inductance and capacitance must be
reduced to meet the needs of high-speed systems.
96
assembly board material and design. That is, the
function desired of package technology has changed
from providing a package as an individual component
to packaging technology that includes board assembly
technology; it can be said to have expanded to
providing a system solution.
CSP TECHNOLOGY
CSP is the generic term for packages approaching
chip size, and a large number of types have been
proposed. Among area-array type packages, fine-pitch
versions of BGA have become the most widely used
type of CSP for the reasons given in the section above.
Not only can mass assembly by reflow be used with
this type in the same manner as with previous surface
mount types, it also builds-in reliability. Thus we
believe that this is the most effective package today
for making smaller electronic devices.
In general, there are variations in the external
configuration of BGA type CSPs in combinations of
package size and solder ball pitch, but there are a
multitude of variations of package structure including
those related to reliability, manufacturability, and
design of interconnects within the package. At present,
these CSPs are used in mobile phones and similar
applications using high interconnect density boards
where small size is essential.
Solder ball pitch, from the standpoint of test socket
technology and assembly board interconnect design,
is now at the stage where stable functional technology
has been created for 0.5 - 0.8 mm.
The most important determinants with regard to
reliability are solder-process heat resistance and
thermal-cycle life after assembly, moisture resistance,
and mechanical stress resistance. The thinness of CSP
packages makes it difficult to maintain a low level of
moisture absorption by the package before assembly,
and the danger of cracks occurring during reflow
soldering is higher than with earlier types of packages.
Also, it is more difficult to maintain reliability after
assembly than for earlier types because CSP packages
are small and thin. An example of the structure of a
Hitachi CSP is shown in Fig. 4.
Fan-out CSP
Package substrate material is the polyimide tape
usually used in tape carrier packages (TCP). The Cu
leads on the tape are attached to the chip by tape
automated bonding (TAB) technology. Solder balls are
attached to the Cu interconnects through openings in
the solder resist on the tape. Stiffeners are attached
Hitachi Review Vol. 48 (1999), No. 2
Polyimide tape
Stiffener
Polyimide tape
LSI chip
Sealant resin
Al pad
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LSI chip
Adhesive
Solder ball
Elastomer
Cu lead
Solder ball
S-shape lead
Fan-out type
Fan-in type
Fig. 4—Example of CSP Structure.
Hitachi has a lineup of fine-pitch BGA (FBGA) in the CSP category. One type for high pin counts is
the fan-out type with solder balls located outside the chip perimeter. The other type for low pin
counts in the fan-in type with solder balls located on the chip.
on the rear surface of the tape to maintain the
coplanarity of the solder balls.
The stiffeners are made of copper, and have
approximately the same thermal coefficient of
expansion as ordinary glass-epoxy substrates, so the
stress on the solder balls is small. Stress on the
mounted chip and the assembly board caused by the
difference in thermal coefficient of expansion is
relieved by the thin polymide film between them.
Therefore, underfill after assembly is not necessary.
The package outline can be made small by making
the solder-ball pitch 0.5 mm and arranging solder balls
in two rows around the periphery; then the design of
the arrangement of the assembly board interconnects
is relatively easy. If solder balls with a diameter of
0.3 mm are used, the package thickness can be 1.0
mm, and thinness can be realized.
Fan-in CSP
The fan-in type of structure was first proposed by
the Tessera Inc. of the US 4, 5). Polyimide tape is used
as the substrate material, and Cu interconnects on the
tape are used to make electrical connections to the chip.
Solder balls are attached to the copper interconnects
through holes formed in the tape. A feature of this
technology is the use of an elastomer as the adhesive
between the chip and the tape. Therefore, even if the
low-cost glass-epoxy substrates that are utilized in the
largest quantities are used, the stress at the base of the
solder balls is suppressed.
When stress at the solder ball region is relieved, it
is known that stress becomes concentrated at the other
attachment interface: the chip attachment region. To
prevent this from happening in the fan-in structure, an
S-shaped lead attachment configuration is used. The
aim is to have the slack in the lead relieve the distortion
caused by thermal stress. Use of this structure makes
underfill free after soldering to the substrate.
Hitachi has made especially strong efforts to
optimize the materials properties of the elastomer.
Reliability has been enhanced from the standpoint of
moisture and thermal resistance, and has reached a
Joint Electronic Device Engineering Council (JEDIC)
reflow resistance reliability level 1 rating.
Fan-in and -out CSP
Our fan-in and -out CSP is a molded-type CSP that
uses a polyimide tape as the package base material. A
chip with its device side facing upward is mounted on
a tape with formed Cu interconnects, and electrical
connections are made between the chip and Cu
interconnects by Au wire bonding. Then epoxy
packaging resin is used for molded encapsulation.
Solder balls are attached to the Cu interconnects via
throughholes formed in the tape. Ability to locate
solder balls under the chips enables decreased size.
Semiconductor Packaging Technologies for Miniaturization and High Pin Count
The stress caused by the differences in thermal
coefficient of expansion between the chip and the
assembly board that occurs when chips are assembled
on a glass-epoxy board is relieved by the die-bond
adhesive under the chip, and by the tape. These effects
are small, though, so the reliability is inferior to the
two CSP types previously described. Therefore this
type is suitable for small chips in small packages.
When the chip size or package size is large, underfill
after assembly or other modification is necessary.
Multichip Package
A large variety of technologies have been
announced for encapsulating multiple semiconductor
devices in a single package. Dynamic random access
memory (DRAM) examples are shown in Fig. 5 and
6. The double density package (DDP) is a conventional
TSOP package for a single chip in which 2 chips have
been encapsulated. Chips with their rear surfaces
ground down to reduce thickness are mounted on
leadframes; two leadframes carrying chips are
arranged at the front and back, encapsulated by
molding, and then corresponding leads are connected.
Alternately, with multilevel TCP, two types of TCP
with different lead lengths are assembled in stacked
layers to achieve a two-story structure on the memory
module. Both methods are examples of the use of
package technology to achieve 2 × DRAM capacity.
However it is not easy to use extensions of these
technologies to obtain 4× or 8× DRAM capacity. The
problem arises of how to make packages with heat
dissipation capability sufficient to handle the generated
heat.
Questions related to intellectual property (IP)
including which semiconductor devices to combine
and how to interconnect them are likely to be key
elements during the future development of multichip
packages.
Lead frame
LSI chip
Sealant resin
128-Mbit DRAM
(64 Mbit × 2)
Same outline as
TSOP (400-mm width)
Fig. 5—DDP Structure.
In the three-dimensional package category Hitachi makes a
lineup of double density package (DDP) products having 2
chips within the TSOP outline. When this package is used a
128-Mbit DRAM can be packaged in the same size space as a
64-Mbit DRAM.
TCP
Lead
DIMM: dual inline memory module
256-Mbyte
(64 Mbit × 32 chips)
Standard DIMM module
Cover
25.4 mm
NEXT-GENERATION PACKAGE
TECHNOLOGY
CSP approaches chip size and can be said to be the
ultimate solution. The direction for the future to attain
even further evolution will be found along two routes.
One will be three-dimensional packages in which
multiple semiconductor devices are stacked in the same
area, the other will be packages that implement actual
chip size with bear-chip assembly technology.
Examples of types under consideration at Hitachi are
described below.
Au wire
98
133.5 mm
Fig. 6—Multilevel TCP Module Structure.
Bare-Chip Assembly Technlogy
The attraction of assembling bare chips is said to
be that they implement the ultimate reduction in size
and eliminate packaging operations. However, because
of problems such as those described below, a definitive
assembly method has not been developed.
First of all there is the difficulty of known good
die (KGD). The package function of enlarging the
pitch is missing necessitating a fine pitch test contact
method, but an inexpensive test method has not been
perfected. Second is the problem of achieving and
guaranteeing reliability. Reliability after assembly
depends the techniques of the assembly manufacturer.
Therefore, when rejects occur, difficulty in pinpointing
responsibility is a problem.
At present, development is proceeding as described
below and shown in Fig. 7 to overcome these difficult
Hitachi Review Vol. 48 (1999), No. 2
99
superb packages cannot be used if they do not conform
to user concepts. In the future we expect to confer
with assembly-technology engineers from the
technology-development phase in an effort to improve
packaging technology.
Enlarged view
Bump
UBM
Relocation
interconnect
UBM: under bump metal
Al
Structure cross-section
Fig. 7—Wafer Level Package Technology.
Now under development is more highly advanced CSP
technology in which a package equivalent to the contour of CSP
is fabricated in the wafer process. Flip-chip attachment is used
based on two technologies: the Al pad connections are relocated
by interconnections to an area array; and reliability of the bump
attachment region is achieved by UBM.
problems. The chip is rewired with an area array of
bumps arranged on the device surface to avoid having
fine-pitch contacts. Because the bumps are formed
within the restricted limits of the chip area, for high
pin counts a bump arrangement with an even finer pitch
than for CSP is required. Also low-cost widespread
availability of high-interconnect density assembly
boards is a prerequisite.
To achieve high reliability after assembly, it is
desirable that the thermal coefficient of expansion of
assembly boards approaches that of the chip.
Moreover, the structure must be capable of providing
protection for at least the device surface of the chip.
Thus Hitachi uses an under bump metal (UBM)
structure on the bump attachment region to prevent
thermal diffusion of the solder.
If this structure is implemented, the present
packaging process would be performed as a wafer
process, and turnaround time (TAT) will be reduced.
The structure is especially promising for highfrequency applications where short interconnects are
desired because chip size assembly can be realized.
We also think that the range of applications will
become broader with the widespread availability of
high-interconnect density assembly boards.
CONCLUSIONS
We have described promising package technology
that should contribute to systems solutions. At present
it is difficult to draw a boundary between package
technology and user assembly technology. Even
REFERENCES
(1) I. Anjo, et al., Advanced IC Packaging for the Future
Applications, IEEE Transactions on Electron Devices 45, No.
3 (1998-3).
(2) I. Anjo, et al., Development of Tape BGA-type CSP, Journal
of Electronic Information Communication Society 96, No.
414, CPM96-121, (1996), pp.1–8.
(3) R. Haruta, et al., Development of Fan Out CSP with Superior
Mounting Reliability, Proceedings from the 7th
Microelectronics Symposium (1997), pp. 169–172
(4) T. H. Di Stefano, et al., µBGA for High Performance
Applications, Proc. of Surface Mount International 1884,
(1994) pp. 212–215.
(5) T. H. Di Stefano, et al., Development of Practical, Superhigh
Pin Count and High Density Package with Chip Scale, NIKKEI
MICRODEVICE (May 1994), pp. 98–102
(6) Y. Akiyama, et al., Chip Scale Packaging for Memory Devices,
Proc. of 48th IEEE Electronic Components and Technology
Conference, pp. 477–481
ABOUT THE AUTHORS
Ichiro Anjo
Joined Hitachi, Ltd. in 1978, and now works at the
Packaging Engineering Development Dept.,
Semiconductor Technology Development Center,
Semiconductor & Integrated Circuits Group. He is
currently engaged in the development of packaging
technology for advanced systems. Mr. Anjo can be
reached by e-mail at [email protected]
Asao Nishimura
Joined Hitachi, Ltd. in 1975, and now works at the
Packaging Engineering Development Dept.,
Semiconductor Technology Development Center,
Semiconductor & Integrated Circuits Group. He is
currently engaged in the development of elementary
technologies for advanced packaging such as process
technology and structural analysis. Mr. Nishimura
can be reached by e-mail at
[email protected]
Ryo Haruta
Joined Hitachi, Ltd. in 1979, and now works at the
Packaging Engineering Development Dept.,
Semiconductor Technology Development Center,
Semiconductor & Integrated Circuits Group. He is
currently engaged in the development of new LSI
packages. Mr. Haruta can be reached by e-mail at
[email protected]