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Introduction to the HC12 A/D converter system
ME 437/537
Introduction:
The M68HC12 contains an eight-channel, 8-bit A/D converter with +/- 1 LSB accuracy.
Port AD bits PAD0-PAD7 are the analog input pins which are sampled and converted to
8-bit digital values. The results of the A/D conversion are placed in the data registers
ADR0H – ADR7H ($0070 - $007E). There are several A/D control registers, named
ATDCTL#, which control the operation of the A/D. These registers must be initialized to
perform the A/D process. These will be described in the following sections. In addition,
a single reference voltage state must be physically set over the pins VRH and VRL (see the
breakout board for these pins). VRH must not exceed 6V, and VRL must not go below 0V.
The range VRH - VRL must be greater than or equal to 0 V. Using this reference range, all
analog inputs are converted to a value using a linear conversion over this range. For
example, if VRH = 5V and VRL = 0V, then an analog input of 2.5 V would be converted to
a digital number of ½*28 or ½*256 or 127 (1 V input would be converted to 1/5*28 or
1/5*256). Note that the resolution is given as:
resolution = (VRH - VRL)/256.
Procedure to Use A/D Converter:
Step 1: A/D power up. ATDCTL2 (A/D ConTroL register 2, $0062) shown below,
contains several initialization parameters. Of primary importance is the ADPU bit (A/D
power up bit), which must be set to one to power up the A/D, and the AFFC (A/D fast
flag clear all) bit, which controls how A/D flags are cleared (recommend using the
default). For example, writing $80 to ATDCTL2 will power up the A/D. After powerup, a 100 microsec. delay is required before using the A/D.
ATDCTL2 -- $0062 – ATD Control Register 2
Bit 7
6
ADPU
AFFC
Reset 0
0
5
AWAI
0
4
3
2
0
0
0
0
0
0
1
ASCIE
0
bit 0
ASCIF
0
with
ADPU: ATD Power up
0 = Disables A/D for reduced power consumption (default)
1 = Allows the A/D to function normally
A short time delay of 100 micro seconds should be executed after powering up the A/D to
allow all analog circuits to be stabilized.
AWAI: ATD Wait mode
0 = ATD continues to run when the HC12 is in a wait mode
1 = ATD stops when HC12 is in a wait mode (to save power)
1
AFFC: ATD Fast Flag Clear All
ASCIE: ATD Sequence Complete Interrupt Enable
ASCIF: ATD Sequence Complete Interrupt Flag
Step 2: Set sampling and conversion time. The sampling and conversion time can be
controlled, with ATDCTL4 ($0064). It is advised to use the default values. The general
rule of thumb is that high-impedance sources require a longer sample time. Therefore, no
action needs to be taken in step 2.
ATDCTL4 -- $0064 – ATD Control Register 4
Bit 7
6
5
0
SMP1
SMP0
0
0
Reset 0
4
PRS4
0
3
2
1
bit 0
PRS3
PRS2
PRS1
PRS0
0
0
0
0
with
SMP1, SMP0: Sample Time Select Bits
Prescaler bits
PRS4-PRS0
00000
00001
00010
00011
00100
00101
00110
00111
01xxx
11xxx
SMP1
Total Divsor
2
4 (default
6
8
10
12
14
16
do not use
do not use
SMP0
0
0
1
1
Max P-Clock
(MHz)
Max ATD
Clk (MHz)
4
8
8
8
8
8
8
8
Min ATD Clk
(MHz)
1
2
3
4
5
6
7
8
.5
.5
.5
.5
.5
.5
.5
.5
2
2
1.33
1
.8
.667
.571
.5
Final sample time,
ATD Clock
periods
0
1
0
1
Min P-Clock
(MHz)
2
4
8
16
Total conversion
time, ATD clk
periods
18
20
24
32
Nyquist Frequency
for 2 MHz ATD
clk
55.5 kHz
50 kHz
41.7 kHz
31.25 kHz
2
Step 3: Set ATDCTL5. The ATDCTL5 register ($0065) controls the sampling modes.
This is done through the following bits:
S8CM – allows 4 or 8 A/D conversions at a given time
SCAN – set for either a single scan sequence (0) or a continuous scan sequence (1)
MULT – set to allow conversion of a single channel (0) or multiple channels (1)
CD-CA – Selects the channel for conversion (when MULT=0)
Note: If conversion is to be completed on 1 channel, then 4 or 8 conversions on that one
channel are performed and stored. If conversion is to be completed on multiple channels,
then 4 or 8 channels are read and stored. The following charts provide more information
on ATDCTL5 selection.
ATDCTL5 -- $0065 – ATD Control Register 5
Bit 7
6
5
0
S8CM
SCAN
0
0
Reset 0
4
MULT
0
3
2
1
bit 0
CD
CC
CB
CA
0
0
0
0
with
S8CM: Select 8 Channel Mode
0 = Conversion sequence consists of four conversions (default)
1 = Perform 8 conversions in the conversion sequence
SCAN: Enable continuous channel scan
0 = Single conversion sequence each time ADTCTL5 is written (default)
1 = Continuous conversion sequences
MULT: Enable multichannel conversion
0 = All 4 or 8 conversions are done on a single input channel selected by CD-CA
(default)
1 = Each of the 4 or 8 conversions are done on sequential channels in groups
selected by CD-CA
CD-CA: Channel select for conversion
S8CM
MULT
CD
CC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
CB CA Channels
converted
0
0
0
0
1
1
1
0
2
1
1
3
0
0
4
0
1
5
1
0
6
Result
Registers
Comments
ADR0-ADR3
ADR0-ADR3
ADR0-ADR3
ADR0-ADR3
ADR0-ADR3
ADR0-ADR3
ADR0-ADR3
Sequence of 4
conversions of
a single channel
3
0
0
0
1
1
1
7
ADR0-ADR3
0
0
1
1
0
0
0
1
x
x
x
x
0-3
4-7
ADR0-ADR3
ADR0-ADR3
Sequence of 4
conversion of 4
channels
0
x
1
0
x
x
Reserved
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
0
1
0
Vrh
Vrl
ADR0-ADR3
ADR0-ADR3
ADR0-ADR3
4 conversions of
Vrh, Vrl, etc.
0
0
1
1
1
1
Reserved
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
ADR0-ADR7
ADR0-ADR7
ADR0-ADR7
ADR0-ADR7
ADR0-ADR7
ADR0-ADR7
ADR0-ADR7
ADR0-ADR7
Sequence of 8
conversions of
a single channel
1
1
0
x
x
x
0-7
ADR0-ADR7
Sequence of 8
conversions of 8
chls
1
x
1
0
x
x
Reserved
1
1
1
0
0
0
1
1
1
1
1
1
0
0
1
0
1
0
Vrh
Vrl
ADR0-ADR7
ADR0-ADR7
ADR0-ADR7
8 conversions of
Vrh, Vrl, etc.
1
1
x
1
1
1
1
x
1
x
1
x
Reserved
Reserved
(Vrh-Vrl)/2
(Vrh-Vrl)/2
Step 5: A/D Operation. The A/D conversion is started by writing to the ATDCTL5
register. Each conversion requires some number of clock cycles (refer to HC-12
reference manual). After the conversions are done, a sequence complete flag (SCF) is set
in the A/D status register (ATDSTAT, $0066, $0067), and the result registers are ready to
be read. The A/D is now waiting for another write to the ATDCTL5 register to begin
another sequence (if SCAN=0) or will repeat the process (if SCAN = 1).
ATDSTAT -- $0066, (and $0067) – ATD Status Registers
Bit 7
6
5
4
3
2
1
bit 0
4
SCF
0
0
Reset 0
0
0
0
0
0
CC2
CC1
CC0
0
0
0
0
with SCF the sequence complete flag. This bit is set at the end of the conversion
sequence.
Step 6: Fetch digital results. The digital results are available in the ADR0H to ADR7H
registers ($0070 to $007E). The conversion is complete when the SCF flag is set in the
ATDSTAT register. This register can be checked through a polling process. The SCF
flag is cleared when the ATDCTL5 register is written (when AFFC = 0 in ATDCTL2).
In addition, Conversion complete flags (CCFx) are contained in the low byte of
ATDSTAT that indicate the end of the conversion for each associated channel.
ADR0H - $0070 – A/D Converter Result Register 0
ADR1H - $0072 – A/D Converter Result Register 1
ADR2H - $0074 – A/D Converter Result Register 2
ADR3H - $0076 – A/D Converter Result Register 3
ADR4H - $0078 – A/D Converter Result Register 4
ADR5H - $007A – A/D Converter Result Register 5
ADR6H - $007C – A/D Converter Result Register 6
ADR7H - $007E – A/D Converter Result Register 7
PORTAD - $006F – PORT AD Data Input Register
Bit 7
6
5
PAD7
PAD6
PAD5
0
0
Reset 0
4
PAD4
0
3
2
1
bit 0
PAD3
PAD2
PAD1
PAD0
0
0
0
0
PAD0-7: General purpose digital input bits. Any bit not selected by the channel select
bits CD-CA may be used as general purpose inputs.
Summary: A/D Programming
1. Power up the A/D by setting the ADPU bit in ATDCTL2
2. Wait for 100 microsec. Before using the A/D
3. Choose the S8CM, SCAN, MULT and CD-CA bits in ATDCTL5
4. Write to ATDCTL5 to start the conversion
5. Wait for the conversion sequence to complete by polling the SCF bit in ATDSTAT
6. Read the result in the ADR0H-ADR7H register
5
Example Program
The following example program demonstrates simple use of the A/D functionality in the
HC12. This program will convert the data on Channel 1 (PAD0) and output the
conversion to Port A. The input analog signal can be a photo resistor to measure the level
of light/darkness in a room. The output can be a scale of 8 LED’s attached to Port A.
Note, the reference voltage range of 5 V (VRH=5, VRL=0) is set and a suitable voltage
divider is formed using a photo resistor.
6
* A/D Example Program: This program converts the data on Channel 1 and
* shows conversion results through output of Port A.
* Note: The reference voltage range of 5 V (VRH=5, VRL=0) is set and a suitable
* voltage ; divider is formed using a photo resistor.
ATDCTL2
ATDCTL4
ATDCTL5
ADR0H
ADR1H
ADR2H
ADR3H
ATDSTAT
SCF
ADPU
PORTA
DDRA
STACK
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$0062
$0064
$0065
$0070
$0072
$0073
$0074
$0066
%10000000
%10000000
$0000
$0002
$0A00
* A/D Mode: S8CM=0 (4 conversion sequence), SCAN = 0 (single conversion)
* MULT = 0 (single channel conversion) CD-CA= 0000 (Channel 0, PAD0, converted)
ADMODE
EQU
%00000000
delay
loop
wait
ORG
LDS
LDAA
STAA
LDAA
STAA
LDAA
DECA
BNE
LDAA
STAA
BRCLR
LDAB
STAB
BRA
$0800
STACK
%$FF
DDRA
ADPU
ATDCTL2
#200
;Set all PortA pins to be output
;Power up the A/D
;Create a short delay
delay
#ADMODE
ATDCTL5
;Start the A/D conversion process
ATDSTAT,SCF,wait ;Wait until the conversion is done
ADR0H
;retrieve data from ADR0H
PORTA
loop
7