Download Hw2 Solution - University of California, Berkeley

UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering and Computer Sciences
Last modified on February 6, 2003 by Huifang Qin ([email protected])
Jan Rabaey
Homework #2 Solutions
EECS 141
Problem 1 – Extracting Unified Model Parameters from Simulation
1A
From the figure above, determine the following parameters: VT0,, .
VT0
This one should immediately signal you to look at a curve(s) that don’t have body-effect.
That means VBS = 0V. Pick two points, each from different curves that satisfy the nobody-effect condition. Make sure they’re in the same operating region too!
Point
A
B
VGS
2.5V
2.0V
VDS
1.8V
1.8V
W 
(VGS , A
2
L
1
W 
k p  (VGS , B
2
L
1
I D, A

I D, B
kp
300
160

ID
300uA
160uA
Operating Region
saturation
Saturation
2
 VT 0 ) (1    V DS , A )
2
 VT 0 ) (1    V DS , B )
( 2.5  VT 0 )
2
( 2.0  VT 0 )
2
VT0 = 0.64V
As you can see, working on two points with the same VDS helps to cancel as many
variables as possible to be able to solve the equation.

We can use the same methodology as above. This time, we want to keep VGS constant.
Point
A
B
VGS
2.5V
2.5V
VDS
2.4V
1.8V
W 
(VGS , A
2
L
1
W 
k p  (VGS , B
2
L
1
I D, A
I D, B

kp
310
300


ID
310uA
300uA
Operating Region
saturation
saturation
2
 VT ) (1    V DS , A )
2
 VT ) (1    V DS , B )
(1    2.4)
(1    1.8)
 = 0.0617V-1
It shouldn’t be a surprise, but that leaves us to keep almost everything constant except for
VSB.
Point
VSB
VGS
VDS
ID
A
B
1.0V
0.0V
2.0V
2.0V
1.2V
1.2V
105uA
150uA
W 
2
(VGS , A  VT ) (1    VDS , A )
2
L
1
W 
2
k p  (VGS , B  VT 0 ) (1    V DS , B )
2
L
1
I D, A
I D, B

Operating
Region
saturation
saturation
kp
105
150

( 2.0  VT )
2
( 2.0  0.64)
2
VT = 0.862V
Now solve for using the following equation:
VT  VT 0  

VSB  2 F   2 F
0.862  0.64  
 1  0.6 
0.6


 = 0.453V1/2
2B
Using SPICE, generate the family of curves for a PMOS transistor with the following
parameters.
The following is a listing of my example SPICE deck. You should get familiar with the .ALTER statement, which
allows me to change parameters and resimulate automatically.
**********************************************
PS1 2B PMOS Curves
.lib '/home/aa/grad/huifangq/g25b.mod' TT
* parameters
.param bs = 0
* netlist
M1 D G S B PMOS L=0.25u W=2.0u
VS S 0 2.5
VGS G S 0
VDS D S 0
VBS B S bs
* control
.options post=2 nomod
.op
* analysis
.DC VDS -2.5 0 0.1 VGS -0.7 -2.3 -0.4
.alter
.param bs = 0.5
.alter
.param bs = 1.2
.END
**********************************************
Problem 2 – Device Parameters Part 2
Measurement
Number
1
VGS
VDS
VSB
ID
-2.5V
-2.5V
0
-84.375uA
2
3
4
1.0V
-0.7V
-2.0V
1V
-0.8V
-2.5V
0
0
0
0.0
-1.04uA
-56.25uA
5
-2.5V
-2.5V
-0.8V
-72.0uA
6
-2.5V
-1.5V
0
-80.625uA
7
-2.5V
-0.8V
0
-66.56uA
Operation
Region
velocity
saturation
cutoff
saturation
velocity
saturation
velocity
saturation
velocity
saturation
linear
2A
Is the measured transistor a PMOS or an NMOS device? Explain your answer.
This is a PMOS device. Negative gate-source, drain-source, currents should be your biggest
hint.
2B
From measurements above, determine the following parameters: VT0, , .
This problem is solved using the EXACT same method as problem 1, except that the points are
already chosen for you. I will skip the equations and state the answers.
VT0
-0.5V – The device is in velocity saturation, so we use the velocity saturation equations
of the unified model. The measurements you should use are 1 and 4.

-0.538V1/2 – Use measurements 1 and 5 in the same fashion as problem 2A. Use the
VELOCITY SATURATION equations from the unified model.

-0.05V-1 – Use measurements 1 and 6 in the same fashion as problem 2A. Use the
VELOCITY SATURATION equations from the unified model.
2C
Now, to really impress your friend, complete the missing column in the table above using
the values you obtained in 2B. Fill in either “LINEAR”, “CUTOFF”, “SATURATION”,
or “VEL. SATURATION.” (You don’t have to recopy the whole table, just the last
column is sufficient) Explain your judgment briefly.
The answers are provided in the table above and are shaded in the last column.
ID = 0
=> CUTOFF
Vmin = min (VGT, VDS, VDSAT) = VDS
=> LINEAR
Vmin = min (VGT, VDS, VDSAT) = VGT
=> SATURATION
Vmin = min (VGT, VDS, VDSAT) = VDSAT
=> VELOCITY SATURATION
Problem 3 – Generating a Voltage Transfer Characteristic
3A
Draw the VTC for this circuit. Determine (or estimate, if necessary, from your VTC) the
following parameters: VOH, VOL, VM
We are given both load line plots for the active NMOS device and the non-linear device of the
shaded box. How do we link the information provided by these curves to generate information
about input and output voltages? First, we need to realize that the output voltage of the NMOS
device determines what the voltage drop across the shaded box. That is,
Vout = VDS = VDD – Vshaded-box
A
B
C
D
E
F, G
Since we know I-V relationships in each device AND also the fact that the current through one
must be equal to the current through the other, we can manipulate the curves to tell us something.
Using the relation above, we can superimpose a horizontally-flipped version of the shaded-box’s
I-V curve onto that of the NMOS’ curves. The intersections are the operating points of this
circuit and will give us the input-output voltage relationships we need to build our VTC. Below
is the revised, superimposed graph with the intersections labeled:
Point
A
B
C
D
E
F
G
Vin (VGS)
2.4V
2.0V
1.6V
1.2V
0.8V
0.4V
0.0V
Vout (VDS)
0.57V
0.7V
0.97V
1.4V
2.2V
2.5V
2.5V
VM
VM
The resolution of our plot will not be as fine as we’d like, but you can see how if we had more
points, the curve becomes more and more accurate. This VTC is plotted using Matlab. You can
also do it by hand.
Looking at the VTC, it is quite easy to determine what VOH, VOL, and VM are:
VOH
VOL
VM
3B
2.5V -- NMOS off, shaded-box offers resistive path to bring Vout high, assuming the
output is driving a capacitive load or infinite resistance (which is often true for analysis
questions like these)
~0.6V – When the NMOS transistor turns on, it tries to pull Vout low. At the same time,
the shaded-box is trying to pull Vout high. Depending on the ratio of their effective
resistances, VOL will change. This is something that will be discussed later on the
semester when Ratioed Logic is covered in the course.
~1.3V – Slightly off the 1.25V we were hoping to get in an ideal symmetrical VTC for an
inverter.
This circuit can be used as an alternative to a traditional CMOS inverter (where the nonlinear device is a PMOS transistor). From the concepts discussed thus far in lecture and
from the results of your VTC, what are the disadvantages of this method?
Incomplete pull-down of the output node means we don’t get full rail-to-rail swing at the output.
The noise margin is reduced.
There is static power consumption when the input is high, because there is a direct path from
supply to ground when the NMOS transistor is on. Also the high VOL leads to static power
consumption in the gate that it drives. For low power applications, we aim to minimize static
power.
The VTC also is asymmetric, meaning that a rising transition and its associated output have
different large signal and timing characteristics as a falling transition. Uneven noise margin is
also another problem.
Problem 4 –VTC and Noise Margins Analysis of Different Inverter Implementations
4A
Find VOH, VOL, VM using the quadratic equations.
All-NMOS inverter:
a) Calculate VOH ― Set VIN = 0, M1 is off
Since ID1 = ID2, M2 is also off, which happens when
VGS2 - VT2 = VDD – VOH – VT2 = 0
Solve for VOH get
Where VSB = -VOH.
b) Calculate VOL― Set VIN = VDD, then M2 is saturated and M1 is likely in linear region.
Solve ID1 = ID2 =>
Method 1: Using math software the equations can easily be solved. VOL = 0.374V is the accurate
solution of the equation.
Method 2: Hand analysis with approximations can also produce the result with good accuracy.
i) First using the Taylor series approximation to get rid of the square root calculation,
ii) Then ignore the channel length modulation by assuming temporally that λ = 0.
With these two approximations the equation can now be solved by hand easily =>
VOL = 0.335V.
Generally speaking this result is already accurate enough because the error introduced by
ignoring the channel length modulation is only a factor of (1+ λ(VDD-VOL)) = 1.15 ≈ 1.
iii) However we can still improve the accuracy of the result by hand solving the same equation in
ii) with ID2 multiplied by a factor 1.15. This would give us the result:
VOL = 0.372V, which is very close to the Matlab solution.
― This is a simple illustration on how proper approximations in engineering analysis can help
us simplify the calculations, while still producing results with good accuracy.
VOL = 0.374V => VDS1 < VGS1 = VDD – VT0
Thus M1 is in linear region. Our previous assumption is correct.
c) Calculate VM― Set VIN = VOUT = VM. Both M1 &M2 are in saturation.
Solve ID1 = ID2 => VM = 1.27V
CMOS inverter:
a) Calculate VOH, VOL
When VIN =0, NMOS is off, PMOS is on and pull VOUT all the way up to VDD.
Similarly, when VIN = 3.3V, PMOS is off, NMOS is on and pulls VOUT all the way down to
ground.
Thus VOH = 3.3V, VOL = 0.
b) Calculate VM — Set VIN = VOUT = VM. Both M1 &M2 are in saturation
Solve IDn = IDp => VM = 1.68V
4B
What’s the noise margin of the two inverters? Comment on the results.
All NMOS Inverter:
As shown on the VTC plot, VIL ≈ 0.6V, VIH ≈ 1.6V
NML = VIL - VOL = 0.226V
NMH = VOH - VIH = 0.64V
CMOS Inverter:
As shown on the VTC plot, VIL ≈ 1.4V, VIH ≈ 2.0V
NML = VIL - VOL = 1.4V
NMH = VOH - VIH = 1.3V
4C
Use HSPICE to plot the VTC of the two inverters. Compare the differences in VTC
curves, robustness and regeneration (applying the output of an inverter to another inverter in the
same implementation) of each inverter.
Compared with the CMOS inverter, the all-NMOS inverter has an unsymmetrical VTC, with low
VOH, high VOL and slow transition between VIL and VIH. Therefore the noise margins are
seriously reduced and leading to degraded robustness. Static power consumption is large when
the input is high, because the load NMOS doesn’t shut off.
Applying the VOH and VOL of the all-NMOS inverter to the next inverter in the same
implementation will lead to even reduce output swing and noise margins in the following
inverter. In the CMOS inverter case the high noise margin and good robustness are not degraded
during regeneration.