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Transcript
XC2000 Logic Cell Array Family Product Specifications Features Description • Fully Field-Programmable: The Logic Cell Array (LCA) is a high density CMOS integrated circuit. Its user-programmable array architecture is made up of three types of configurable elements: Input/Output Blocks, logic blocks and Interconnect. The designer can define individual I/O blocks for interface to external circuitry, define logic blocks to implement logic functions and define interconnection networks to compose larger scale logic functions. The XACT Development System provides interactive graphic design capture and automatic routing. Both logic simulation and in-circuit emulation are available for design verification. – I/O functions – Digital logic functions – Interconnections • General-purpose array architecture • Complete user control of design cycle • Compatible arrays with logic cell complexity equivalent from 600 to 1,500 gates • • • • • • • Standard product availability 100% factory-tested Selectable configuration modes The Logic Cell Array is available in a variety of logic capacities, package styles, temperature ranges and speed grades. Low-power, CMOS, static-memory technology TTL or CMOS input thresholds Device Logic Capacity (gates) Complete development system support – XACT Design Editor – Schematic Entry – Macro Library – Timing Calculator – Logic and Timing Simulator – Auto Place/Route XC2064 XC2018 600 - 1,000 1,000 - 1,500 Performance equivalent to TTL SSI/MSI CLBs User I/O Max Config. bits 64 100 58 74 12038 17878 The LCA logic functions and interconnections are determined by data stored in internal static-memory cells. On-chip logic provides for automatic loading of configuration data at power-up. The program data can reside in an EEPROM, EPROM or ROM on the circuit board or on a floppy disk or hard disk. The program can be loaded in a number of modes to accommodate various system requirements. 2-217 XC2000 Logic Cell Array Family Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. Absolute Maximum Ratings Symbol Description Units VCC Supply voltage relative to GND –0.5 to +7.0 V VIN Input voltage with respect to GND –0.5 to VCC +0.5 V VTS Voltage applied to 3-state output –0.5 to VCC +0.5 V TSTG Storage temperature (ambient) –65 to +150 °C TSOL Maximum soldering temperature (10 s @ 1/16 in.) +260 °C Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions Symbol VCC Description VCC relative to GND Commercial 0°C to +85°C junction VCC relative to GND Industrial –40°C to +100°C junction VCC relative to GND Military –55°C to +125°C case Min Max Units 4.75 5.25 V 4.5 5.5 V 4.5 5.5 V VIHT High-level input voltage — TTL configuration 2.0 VCC V VILT Low-level input voltage — TTL configuration 0 0.8 V VIHC High-level input voltage — CMOS configuration 70% 100% VCC VILC Low-level input voltage — CMOS configuration 0 20% VCC TIN Input signal transition time 250 ns At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per °C. 2-218 DC Characteristics Over Operating Conditions Symbol Description Min VOH High-level output voltage (@ IOH = –4.0 ma VCC min) VOL Low-level output voltage (@ IOL = 4.0 ma VCC min) VOH High-level output voltage (@ IOH = –4.0 ma VCC min) VOL Low-level output voltage (@ IOL = 4.0 ma VCC min) VCCPD Power-down supply voltage (PWRDWN must be Low) ICCO Quiescent operating power supply current Commercial Max 3.86 V 0.32 Industrial Military Units 3.76 V V 0.37 2.3 V V CMOS thresholds (@ VCC Max) 5 mA TTL thresholds (@ VCC Max) 12 mA 500 µA +10 µA 10 15 pF pF ICCPD Power-down supply current (VCC(MAX) @ TMAX) IIL Input Leakage Current CIN Input capacitance (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 –10 2-219 XC2000 Logic Cell Array Family CLB Switching Characteristic Guidelines INPUT (A,B,C,D) 1 TILO OUTPUT (X,Y) (COMBINATIONAL) 2 TITO OUTPUT (X,Y) (TRANSPARENT LATCH) 4 TCKI 3 TICK CLOCK (K) 6 TCCI 5 TICC CLOCK (C) 8 TCII 7 TICI CLOCK (G) 9 TCKO 10 TCCO 11 TCIO OUTPUT (VIA FF) SET/RESET DIRECT (A,D) 12 TRIO SET/RESET DIRECT (F,G) 13 TRLO 14 TCH 15 TCL CLOCK (ANY SOURCE) X5389 2-220 CLB Switching Characteristic Guidelines (Continued) Speed Grade Description Logic Input to Output Symbol -70 -100 -130 Units Min Max Min Max Min Max Combinatorial Transparent latch Additional for Q through F or G to out 1 2 To output Logic-input setup Logic-input hold 9 3 4 TCKO TICK TCKI 7 0 To output Logic-input setup Logic-input hold 10 5 6 TCCO TICC TCCI 6 0 Logic Input to G Clock To output Logic-input setup Logic-input hold 11 7 8 TCIO TICI TCII 3 4 Set/Reset direct Input A or D to output x, y Through F or G to output Reset pad to output x, y Separation of set/reset Set/Reset pulse-width 12 13 TRIO TRLO TMRQ TRS TRPW 7 7 6 6 5 5 FCLK 70 *100 130 MHz TCH TCL 7 7 *5 *5 3.5 3.5 ns ns K Clock C Clock Flip-flop Toggle rate Q through F to flip-flop Clock Clock High Clock Low 14 15 TILO TITO 10 14 8 10 5.5 8 ns ns TQLO 6 6 3.7 ns 7 ns ns ns 7 ns ns ns 13 ns ns ns 8 11 13 ns ns ns ns ns 10 13 7 6 0 2.5 1.0 9 5 0 3 1 20 13 2 3 16 21 20 0 5 10 14 17 Notes: 1. All switching characteristics apply to all valid combinations of process, temperature and supply with a nominal chip power dissipation of 250 mW. * These parameters are for clock pulses generated within a CLB. For an externally generated pulse, derate these parameters by 20%. 2-221 XC2000 Logic Cell Array Family IOB Switching Guidelines Pad (Package Pin) (Out) (In) 8 TOP Output Signal 1 TPID TTHZ 9 Input (Direct) TTON 10 3-State 3 TLP 2 TPL L (I/O Clock) 4 TLW 5 TLI Input (Registered) 7 TRC 6 TRI RESET X5433 Speed Grade Description Symbol -70 -100 -130 Min Max Min Max Min Max Pad (package pin) To input (direct) 1 TPID 6 4 I/O Clock To input (storage) To pad-input setup To pad-input hold Pulse width Frequency 5 2 3 4 TLI TPL TLP TLW Output To pad (output enabled) 8 TOP 9 7 Three-state To pad begin hi-Z To pad end hi-Z 9 10 TTHZ TTON 15 15 11 13 RESET To input (storage) To input clock 6 7 TRI TRC 11 6 0 7 70 8 4 0 *5 *100 25 20 3.5 ns 7.5 ns ns ns ns MHz 5.5 ns 2 4 3.5 17 14 Units 7 11 ns ns 15 ns ns 10 Note: Timing is measured at 0.5 VCC levels with 50 pF output load. *These parameters are for clock pulses generated within an LCA device. For an externally applied clock, derate these parameters by 20%. 2-222