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EEEB373 - Microprocessor Systems 8.3.2) Registers Related to Interrupts 8.3.2.1) Reset Configuration Register (RCON) These registers enable/disable the interrupts, set the priority of the interrupts, and record the status of each interrupt source. The RCON register has a bit (IPEN – Interrupt Priority Enable bit) to enable interrupt priority scheme. The other bits are used to indicate the cause of reset. q q q q q RCON INTCON, INTCON2, and INTCON3 PIR1, PIR2, and PIR3 PIE1, PIE2, and PIE3 IPR1, IPR2, and IPR3 Each interrupt source has three bits to control its operation: 1) A flag bit to indicate whether an interrupt event has occurred. 2) An enable bit enabling/disabling the interrupt source. 3) A priority bit selecting high or low priority, which has effect only when the priority scheme is enabled. 28 8.3.2.2) Interrupt Control Registers (INTCON, INTCON2, INTCON3) 7 6 5 4 3 2 1 0 IP EN - - RI TO PD P OR BO R IP EN : In terrup t priority enable bit 0: D isab le priority levels o n interru pts 1: Enab le priority levels o n interrup ts R I: RESET instructio n flag b it 0 : T he reset instructio n w as executed causin g a device reset 1 : T he reset instructio nw as n ot execu ted T O : W atch dog tim eout flag bit 0 : A w atchdo g tim eo ut occurred 1: After po wer-up, C LRW D T instructio n, or SLEEP instru ction P D: P ow er-d ow n d etection flag b it 0 : B y executio n of th e SLEEP instruction 1: After pow er up or by th e C LRW D T instructio n P OR : P o w er-on reset status bit 0 : A p ow er-on reset h as occurred 1 : A p ow er-on reset has not occu rred B O R: Bro wn -ou t reset statu s bit (P IC 18C X 01 do es n ot have th is b it) 0: A b row n-o ut reset has occurred 1: A bro wn -ou t reset has not occu rred 29 Figure 6.1 T he R CO N Register (reprint w ith perm ission of Microch ip) 8.3.2.2) Interrupt Control Registers (INTCON, INTCON2, INTCON3) (Cont) INTCON These 3 registers contain enable, priority, and flag bits for external INT pins, port B pin change, and Timer 0 (TMR0) overflow interrupt. 7 6 5 4 3 2 1 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF GIE/GIEH: Global interrupt enable bit when IPEN (RCON<7>)= 0 0: disables all interrupts 1: enables all interrupts when IPEN = 1 0: disables all interrupts 1: enables all high priority interrupts PEIE/GEIEL: P eripheral interrupt enable bit when IPEN = 0: 0: disables all peripheral interrupts 1: enables all peripheral interrupts when IPEN = 1 0: disables all low priority interrupts 1: enables all low priority interrupts TMR0IE: TMR0 overflow interrupt enable bit 0: disables TMR0 overflow interrupt 1: enables TMR0 overflow interrupt INT0IE: INT0 pin interrupt enable 0: disables INT0 pin interrupt 1: enables INT0 pin interrupt RBIE: PORTB port change interrupt enable bit 0: disables PORTB port change interrupt 1: enables PORTB port change interrupt TMR0IF: TMR0 overflow interrupt flag bit 0: TMR0 has not overflowed 1: TMR0 has overflowed INT0IF: INT0 pin interrupt flag bit 0: the INT0 pin interrupt did not occur 1: the INT0 pin interrupt has occurred PORTB port change interrupt flag bit 0: none of the RB7:RB4 pins have changed state 1: at least one of the RB7:RB4 pins change state 30 Lecturer: Dr Jamaludin Bin Omar Figure 6.2a The INTCON register (reprint with permission of Microchip) 31 8-1 EEEB373 - Microprocessor Systems 8.3.2.2) Interrupt Control Registers (INTCON, INTCON2, INTCON3) (Cont) 8.3.2.2) Interrupt Control Registers (INTCON, INTCON2, INTCON3) (Cont) INTCON2 7 RBPU 6 5 4 3 2 INTCON3 1 INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP 0 RBIP RBPU: PORTB pull-up enable bit 0: all PORTB pull-ups are enabled 1: all PORTB pull-ups are disabled INTEDG0..INTEDG3: INT0..INT3 interrupt pins edge select 0: interrupt on falling edge 1: interrupt on rising edge TMR0IP: TMR0 overflow interrupt priority bit 0: low priority 1: high priority INT3IP: INT3 interrupt priority bit (not available in P18FXX8 & P18CX01) 0: low priority 1: high priority RBIP: PORTB change interrupt priority bit 0: low priority 1: high priority 7 6 INT2IP INT1IP 5 4 INT3IE INT2IE 3 2 1 0 INT1IE INT3IF INT2IF INT1IF INT2IP..INT1IP: INT2..INT1 interrupt priority bit 0: low priority 1: high priority INT3IE..INT1IE: INT3..INT1 interrupt enable bit 0: disable interrupt 1: enable interrupt INT3IF..INT1IF: INT3..INT1 interrupt flag bit 0: interrupt did not occur 1: interrupt occurred Note. 1. PIC18FXX2 , PIC18CXX2, PIC18CXX8, and PIC18FXX8 do not have INT2 and INT3 enable and flag bits 2. PIC18C601/801 does not have INT3 enable and flag bits Note. 1. PIC18FXX8 does not have INTEDG2 & INTEDG3) 2. PIC18C601/801 does not have INTEDG3 Figure 6.2c The INTCON3 register (reprint with permission of Microchip) Figure 6.2b The INTCON2 register (reprint with permission of Microchip) 32 8.4) PIC18 Interrupt Operation 33 8.4) PIC18 Interrupt Operation (Cont) • The interrupt priority scheme can be enabled (IPEN=1) or disabled (IPEN=0). • When IPEN=1, all interrupts are divided into core group and peripheral group. • The priority bits of the interrupts sources in the core group are contained in one of the interrupt control registers (INTCON, INTCON2, and INTCON3). • When the priority scheme is enabled, all highpriority interrupts are under the control of a twolevel interrupt enabling mechanism. • All low-priority interrupts are under the control of a three-level interrupt enabling scheme. • When the priority scheme is disabled, all interrupts in the core group are under the control of a two-level interrupt enabling scheme. • All interrupts in the peripheral group are under the control of a three-level enabling scheme. • The following interrupts are in the core group: 1) INT3…INT0 pin interrupts (RB3…RB0) 2) TMR0 overflow interrupt 3) PORTB input pin (RB7…RB4) change interrupts 49 Lecturer: Dr Jamaludin Bin Omar 50 8-2 EEEB373 - Microprocessor Systems 8.4.1) PIC18 Interrupt Without Setting Priority 8.4.1) PIC18 Interrupt Without Setting Priority (Cont) • The priority scheme is disabled by clearing the bit 7 of the RCON register, i.e. IPEN is logic 0. • All interrupt sources share the common interrupt vector at 0x000008. • In order to identify the cause of interrupt, one need to check each individual interrupt flag bit. • The interrupt sources in the core group can be enabled by setting the GIE bit and the corresponding enable bit of the interrupt source. For example, to enable TMR0 interrupt one must set both the GIE and the TMR0IE bits. • The interrupts in the peripheral group can be enabled by setting the GIE, PEIE, and the associated interrupt enable bits. For example, to enable A/D conversioncomplete interrupt one needs to set the GIE, PEIE, and the ADIE bits. • When an interrupt is responded to (being serviced), the GIE bit is cleared to disable further interrupt. The return address is pushed onto return address stack and the PC is loaded with the interrupt vector. • Most interrupt flags must be cleared by the software in ISR to avoid repetitive interrupts from same source. • The last instruction of an ISR must be retfie instruction. The execution of this instruction will cause the top word of the hardware stack to be popped into the PC and the GIE bit to be set. After this, program control is returned to the interrupted program, and interrupt is re-enabled. This instruction has the option to restore the WREG, the STATUS, and the BSR registers from the fast register stack if the application requires it. 51 8.4.2) PIC18 Interrupt With Priority Enabled 52 8.4.3) PIC18 Interrupts in the Core Group • Should be used when certain interrupts need to be serviced promptly. • The PEIE bit of the INTCON register is used as the lowpriority interrupt enable bit. • A high-priority interrupt is enabled when the GIEH bit and its interrupt enable bit are set to 1. By default, all interrupts are placed in high-priority level after reset. The interrupt vector is at 0x000008. • A low-priority interrupt is enabled when the GIEH, GIEL, and its associated interrupt enable bits are all set to 1. The interrupt vector is at 0x000018. • Pending interrupts in the high-priority group will always be served before the interrupts in the low-priority group. • Interrupt flags must be cleared in the interrupt service routine to avoid recursive interrupts. 8.4.3.1) INT0…INT3 Pin Interrupts • All INT pins interrupt (INT0 – INT3) are edgetriggered. • The edge-select bits are contained in the INTCON2 register. • When an edge-select bit is set to 1, the corresponding INT pin interrupt on the rising edge. 53 Lecturer: Dr Jamaludin Bin Omar 54 8-3 EEEB373 - Microprocessor Systems 8.4.3) PIC18 Interrupt in the Core Group (Cont) 8.5) PIC18 Interrupt Programming 8.4.3.2) Port B Pins Input Change Interrupt Two steps are needed: • An input change on pins RB7…RB4 sets the flag bit RBIF (INTCON<0>). Step 1 Write the interrupt service routine and place it in the predefined program memory. • If the RBIE bit is set, then the setting of the RBIF bit causes an interrupt. Step 2 Set the appropriate interrupt enable bits to enable the desired interrupt. • In order to use this interrupt, the RB7…RB4 pins must be configured for input. • Reading the PORTB port will clear the RBIF flag bit. 55 8.5.1) Interrupt Programming in Assembly Language #1 58 8.5.1) Interrupt Programming in Assembly Language #1 (Cont) Example 6.1: Circuit is as shown in Figure 6.6. • Write a main program and an INT0 interrupt service routine in assembly language. • The main program initializes a counter to 0, enables the INT0 interrupt, and then stays in a while-loop to wait forever. • The INT0 ISR simply increments the counter by 1 and outputs it to the LEDs. Whenever the count is incremented to 15, ISR resets it to 0. count 59 Lecturer: Dr Jamaludin Bin Omar #include <p18F8720.inc> set 0x00 ; count value to be output to LEDs org goto 0x00 main org 0x08 goto retfie int0_ISR org retfie 0x18 ; INT interrupt vector ; pseudo interrupt service routine 60 8-4 EEEB373 - Microprocessor Systems 8.5.1) Interrupt Programming in Assembly Language #1 (Cont) ;**************************************** ; main – main program: initialize and ;**************************************** main clrf count,A movlw 0xF0 movwf TRISD movff count,PORTD forever wait for the interrupt ;**************************************** ; INT0 pin interrupt service routine ;**************************************** ; initialize the count to 0 ; configure port D lower ; 4 pins for output ; output count to port D bsf bcf movlw movwf RCON,IPEN,A ; enable priority interrupt INTCON,INT0IF ; clear INT0 flag 0x90 ; set INT0 interrupt to high priority INTCON,A ; enable INT0 interrupt goto forever 8.5.1) Interrupt Programming in Assembly Language #1 (Cont) int0_ISR add_1 update ; wait for the interrupt INTCON,INT0IF ; clear INT0 interrupt flag bit 0x0F count,A ; count equal to 15 already? add_1 count,A ; reset count to 0 after reaching 15 update count,F,A count,PORTD ; output the count to LEDs Int0 DEMO… 61 8.5.2) Interrupt Programming in Assembly Language #2 bcf movlw cpfseq goto clrf goto incf movff retfie end 62 8.5.2) Interrupt Programming in Assembly Language #2 (Cont) Example 6.2: • Suppose port D pins RD3..RD0 are driving four LEDS. • Write an assembly program that chooses the instruction clock as the clock source for Timer 1 and set the prescale factor so that it overflows twice every second. • The program will increment a counter by one in every Timer 1 overflow interrupt and output the count value to LEDs. • Program the Timer 1 interrupt to the low-priority group. • Assume that the crystal oscillator used in the demo board is 40 MHz. led_cnt 63 Lecturer: Dr Jamaludin Bin Omar #include <p18F452.inc> set 0x00 org goto 0x00 start org retfie 0x08 org goto retfie 0x18 tmr1_ISR ; Low priority group ; jump to Timer 1 ISR 64 8-5