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Power Sequencing Considerations
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Contents
Contents
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices............................... 3
Power Sequence for Arria 10 and Stratix 10 Devices......................................................... 3
Programmable Power Management Controller (PPMC)....................................................... 9
PPMC Example Design .......................................................................................10
Multiple Supply Sequencer...........................................................................................11
Low Cost Discrete Sequencer Design.............................................................................12
Low Cost Sequencer Circuit Description................................................................13
Low Cost Discrete Sequencer Simulation Results................................................... 14
I/O Management During Power Sequencing....................................................................15
Hot-Plug Challenges.......................................................................................... 16
Hot-Plug Example..............................................................................................16
Managing Uncontrolled Loss of Power Events..................................................................20
References................................................................................................................ 22
Document Revision History.......................................................................................... 23
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
2
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
Power Sequencing Considerations for Arria 10 and Stratix
10 Devices
The Arria® 10 and Stratix® 10 FPGAs and SoCs require a specific power-up and
power-down sequence. This document describes several power management options
and discusses proper I/O management during device power-up and power-down.
Design your power supply solution to properly control the complete power sequence.
Power Sequence for Arria 10 and Stratix 10 Devices
The power rails in Arria 10 and Stratix 10 devices are each divided into three groups.
Refer to Arria 10 and Stratix 10 pin connection guidelines for additional details.
Figure 1.
Power-Up Sequence for Arria 10 Devices
Group 1
Group 2
Group 3
Group 1
VCC, VCCP,
VCCR_GXB,
VCCT_GXB,
VCCERAM,
VCCL_HPS
90% of Nominal Voltage
Group 2
VCCPT,
VCCH_GXB,
VCCA_FPLL,
VCCPLL_HPS,
VCCIOREF_HPS
90% of Nominal Voltage
Group 3
VCCPGM,
VCCIO,
VCCIO_HPS
Device I/O Pins
90% of
Nominal
Voltage
Output Tri-Stated
Recommend Inputs Not Driven
Normal I/O Incomplete Operation
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
Figure 2.
Power-Up Sequence for Stratix 10 Devices
Group 1
Group 1
VCC
VCCP
VCCR_GXB
VCCT_GXB
VCCERAM
VCCL_HPS
VCCPLLDIG_SDM
VCCPLLDIG_HPS
Group 2
Group 3
90% of
Nominal
Voltage
Group 2
90% of
Nominal
Voltage
VCCPT
VCCH_GXB
VCCA_PLL
VCCPLL_HPS
VCCPLL_SDM
VCCADC
Group 3
VCCIO_SDM
VCCIO_HPS
VCCIO
VCCIO3V
VCCFUSEWR_SDM
Device I/O Pins
90% of
Nominal
Voltage
Output Tri-Stated
Recommend Inputs Not Driven
Normal I/O
Operation
Group 1
Arria 10 Group 1 includes the VCC, VCCP, VCCR_GXB, VCCT_GXB, VCCERAM, and VCCL_HPS
power rails.
Stratix 10 Group 1 includes the VCC, VCCP, VCCR_GXB, VCCT_GXB, VCCERAM, VCCL_HPS,
VCCPLLDIG_SDM, and VCCPLLDIG_HPS power rails.
All the power rails in Group 1 must ramp up to a minimum of 90% of their respective
nominal voltage before the power rails from other groups can start ramping up.
Group 2
Arria 10 Group 2 includes the VCCPT, VCCH_GXB, VCCA_FPLL, VCCPLL__HPS, and VCCIOREF_HPS
power rails.
Stratix 10 Group 2 includes the VCCPT, VCCH_GXB, VCCA_PLL, VCCPLL_HPS, VCCPLL_SDM and
VCCADC power rails.
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
4
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
The power rails within Group 2 can ramp up in any order after the last power rail in
Group 1 has ramped to the minimum threshold of 90% of its nominal voltage. All the
power rails in Group 2 must ramp to a minimum threshold of 90% of their nominal
value before the Group 3 power rails can start ramping up.
Group 3
Arria 10 Group 3 includes the VCCPGM, VCCIO, and VCCIO_HPS power rails.
Stratix 10 Group 3 includes the VCCIO, VCCIO3V, VCCIO_SDM, and VCCIO_HPS and
VCCFUSEWR_SDM power rails.
The power rails within Group 3 can ramp up in any order after the last power rail in
Group 2 has ramped up to a minimum threshold of 90% of their full value.
The Group 3 power rails can be combined with Group 2 in the following case:
•
Arria 10: If the Group 3 power rails are 1.8 V and sharing the same regulator as
Group 2, VCCIO, VCCPGM, and VCCIO_HPS may ramp together with the other power
rails in Group 2.
All the power rails must ramp up monotonically. The power-up sequence should meet
either the standard or the fast Power On Reset (POR) delay time. The POR delay time
depends on the POR delay setting used.
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
5
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
Figure 3.
Power-Down Sequence for Arria 10 Devices
Group 3
Group 1
Group 2
Group 3
Group 2
Group 1
VCC, VCCP,
VCCR_GXB,
VCCT_GXB,
VCCERAM,
VCCL_HPS
VCCPT,
VCCH_GXB,
VCCA_FPLL,
VCCPLL_HPS,
VCCIOREF_HPS
10 % of
Nominal
Voltage
VCCPGM,
VCCIO,
VCCIO_HPS
10 % of
Nominal
Voltage
Device I/Os
Normal I/O Operation
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
6
Outputs tri-stated, inputs
recommended not to be driven
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
Figure 4.
Power-Down Sequence for Stratix 10 Devices
Group 3
Group 1
VCC, VCCP,
VCCR_GXB,
VCCT_GXB,
VCCERAM,
VCCL_HPS,
VCCPLLDIG_SDM,
VCCPLLDIG_HPS
Group 2
VCCPT,
VCCH_GXB,
VCCA_PLL,
VCCPLL_HPS,
VCCPLL_SDM,
VCCADC
Group 3
Device I/Os
Group 2
Group 1
10% of
Nominal
Voltage
VCCIO_SDM,
VCCIO_HPS,
VCCIO,
VCCIO3V,
VCCFUSEWR_SDM
10% of
Nominal
Voltage
Normal I/O Operation
Outputs tri-stated, inputs
recommended not to be driven
During power-down, all power supplies in Group 3 must ramp down to 10% of the
nominal before any power supplies from Group 2 can start to ramp down. All power
supplies in Group 2 must ramp down to 10% of the nominal before any power supplies
from Group 1 can start to ramp down. VCC power rail in Group 1 must be the last to
ramp down.
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
7
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
Figure 5.
Power-Down Sequence for Arria 10 and Stratix 10 Devices for combined
Group2 and Group3 powers
Group 3
Group 2
Group 1
Group1 Power rails
Group 2
Group 3
VCCPT
VCCH_GXB,
VCCA_PLL,
VCCPLL_HPS,
VCCPLL_SDM,
VCCADC,
VCCIO_SDM,
VCCIO_HPS,
VCCIO,
VCCIO3V
10% of
Nominal
Voltage
VCCFUSEWR_SDM
10% of
Nominal
Voltage
Device I/Os
Normal I/O Operation
Outputs tri-stated, inputs
recommended not to be driven
For Arria 10 and Stratix 10 devices, when the Group 3 power rails are 1.8V and share
the same voltage regulator, then the Group 3 power rails can be combined with Group
2 power rails. In this case, Group 2 and Group 3 power rails can ramp down together.
During the power-up/down sequence, the device output pins are tri-stated. Intel
recommends that the input pins should not be driven during this time to ensure long
term reliability of the device.
Not following the power sequence considerations can result in unpredictable device
operation.
Notes:
Special consideration must be given to the ramping of VCC. If the VCC voltage level is
different from the other voltages within Group1, then ramp up VCC first followed by
the other voltage rails, or ramp down VCC last after the other voltage rails have
ramped down.
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
8
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
To ramp up VCC, first ramp up VCC to 90% of its nominal value. Next, ramp up the
other voltage rails (in any order) within Group 1.
Ramp down VCC at the end after all other power rails within Group 1 have fallen below
10% of their nominal values.
For configuration via protocol (CvP), the total TRAMP must be less than 10 ms from the
first power supply ramp-up to the last power supply ramp-up. Select fast POR delay
setting to allow sufficient time for the PCI Express® (PCIe®) link initialization and
configuration. The power-up sequence must meet either the standard or fast POR
delay time depending on the POR delay setting used.
Related Links
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Programmable Power Management Controller (PPMC)
Using a programmable power management controller provides a full-featured option to
implement the power sequencing requirements.
These controllers provide the necessary power-up/down sequence control functions.
These controllers can dynamically monitor and scale the regulator's output voltage,
and supervise fault conditions such as over voltage or under voltage. To program the
power management controller, typically a PMBus or I2C interface is used to connect to
an intelligent host such as the system's microprocessor.
PPMC can be an optimal solution for systems in which up-time and fault tolerance are
critical features and voltage monitoring and fault reporting are essential system
requirements.
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
9
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
PPMC Example Design
Figure 6.
Simplified Multi-Channel Programmable Power Management Controller
VCC
DAC_1P
SENSE_1P
DAC_1N
SENSE_1N
EN1
Vreg1
Vin Vout
Vout1
R1a
fb
en
pg
PG1
Vreg2
Vin Vout
DAC_2P
SENSE_2P
DAC_2N
SENSE_2N
EN2
MAX Device or
Microprocessor
Host
I2C
Vout2
fb
pg
Load1
R2a
R1b
en
R3a
PG2
R3b
Load2
R2b
SDASCL
Vreg n
Vin Vout
DAC_nP
SENSE_nP
DAC_nN
SENSE_nN
ENn
Programmable Power
Management Controller
Vout n
R1 n
fb
en
pg
PG n
R2 n
R3 n
Load n
A single channel of the PPMC typically provides the following features:
•
Differential sense line inputs to remotely monitor the load voltage.
•
Digital-to-Analog Converter (DAC) outputs to trim the regular output voltages. The
DAC outputs drive the regulator's feedback input (fb) and control the regulator's
output voltage.
•
Enable Outputs (EN1, EN2, ...ENn) that drive the voltage regulator's Enable
Inputs (en). The regulator's enable inputs control the desired power-up/down
sequence.
Typically, PPMC devices have multiple channels so that a single controller can
sequence multiple regulators. If more channels are required than what is offered by a
single device, then multiple devices can be cascaded. A separate host interface
( PMBus or I2C) is used to connect the system processor and the PPMC to manage the
controller software and programming.
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
10
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
Consult your power module vendor for more information on PPMC.
Multiple Supply Sequencer
If only a simple power-up / down sequencing is required to follow the Arria 10 or
Stratix 10 power sequencing considerations, then a low cost multiple supply sequencer
IC can be used.
These devices offer multiple sequenced output enables that are controlled by a
dedicated input. When the input is switched on, the Output Enables (EN1/ EN2 /EN3)
turn on in successive order after a programmed time delay. This time delay between
the output enables can be adjusted.
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
11
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
Figure 7.
Example Schematic Design using a Multiple Supply Sequencer IC
VCC
Vreg1
Vin Vout
Vout1
R1a
fb
EN1
en
pg
Vreg2
Vin Vout
R2a
Load1
Vout2
R1b
fb
EN2
On Switch
en
pg
R2b
Load2
ON
Vreg 3
Vin Vout
Vout3
R1c
fb
EN3
Multiple Supply
Sequencer IC
en
pg
R2c
Load3
ON
EN1
EN2
EN3
Consult your power module vendor for more information on multiple supply sequencer
ICs.
Low Cost Discrete Sequencer Design
Discrete sequencer design is a low cost option in which the charging and discharging
voltage of a simple resistor-capacitor (RC) network and preset reference voltage levels
are used.
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
12
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
The RC ramp-up/down voltage is compared with preset reference voltage levels to
generate a series of sequenced power enable outputs to control the voltage
regulators.
Figure 8.
Power-Up / Power-Down Sequencer
The power-on event triggers the capacitor charging. As the capacitor voltage rises
above each of the preset reference voltage levels, the power enable outputs are
sequentially turned on. Similarly, for the power-down event, the discharging of the
capacitor causes the power enable outputs to turn off in the reverse sequential order.
Power On
Power Off
System Off
Reference n
Reference 2
Reference 1
Charging
Capacitor
Ramp Up
Capacitor
Discharge
Ramp Down
Power Enable 1
Power Enable 2
Power Enable 3
Low Cost Sequencer Circuit Description
The example design for the simple low cost power-up/down sequencer uses a quad
comparator IC (U1) and discrete resistors and capacitors.
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
13
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
Figure 9.
Low Cost Sequencer Example Circuit
VCC_stby
V1
+
VCC
+
-
VCC
S1
R1
Switch
8K
R3
49.9 K
12 V
R2
10 K
C1
1 µF
C3
0.1 µF
- + U1A
+ LT1720
Vref
12 V
.tran 250 m Startup
R4
49.9 K
C2
0.1 µF
R5
4.99 K
Vramp
R6
4.99 K
C4
4.7 µF
R7
49.9 K
V3
- + U1B
+ - LT1720
En_Reg3
V2
- + U1C
+ - LT1720
En_Reg2
- + U1D
+ - LT1720
En_Reg1
R8
49.9 K
R9
49.9 K
V1
R10
49.9 K
A system standby voltage VCC_stby is always present to power the comparator U1A.
A reference voltage Vref is generated from VCC_stby through resistor dividers R3
and R4. Vref is the reference voltage for the inverting input of comparator U1A. A
more accurate Vref can be generated using a precision trimmed zener diode in place
of resistor R4. The resistor ladder network consists of resistors R7, R8, R9, and R10.
This ladder network further divides the reference voltages V3, V2, and V1. Comparator
(U1B, U1C, and U1D) outputs drive the associated regulator enables (En_reg3,
En_Reg2, En_Reg1). These outputs turn On/Off the voltage regulators (not shown).
Switch S1 is the system power On/Off switch.
Low Cost Discrete Sequencer Simulation Results
Figure 10.
Circuit Simulation Results for Power-Up and Power-Down Events
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
14
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
Initially, the power sequencer circuit is not operational because the power switch S1 is
open. As a result, all the regulator enables (En_Reg1, En_Reg2, and En_Reg3) are
low. As the regulator enables drive the voltage regulators, all the voltage regulators
are turned off.
Power ON
•
When switch S1 is closed, the system turns on and the voltage VCC charges the
capacitor C1 to voltage level Vin.
•
C1 is charged through resistor R1. Voltage level Vin depends on the values of R1
and R2 which form voltage divider and Vin = (R2/(R1+R2))*VCC. R1 and R2
are selected such that the value of Vin is slightly higher than comparator U1A's
reference voltage Vref.
•
When the value of Vin rises above Vref, comparator U1A's output goes high and
capacitor C4 starts charging through resistor R5.
•
Resistors R5 and R6 set the ramp voltage Vramp. Resistor R5 and capacitor C4
define the time constant for the ramp rate of Vramp. Vramp is the input voltage to
the non-inverting inputs of comparators U1B, U1C, and U1D. As Vramp rises
above the voltage references (V1, V2, and V3), it sequentially trips comparators
U1D, U1C, and U1B, turning on regulator enables En_Reg1, En_Reg2, and
En_Reg3.
Power OFF
•
The order of the power-down sequence is reverse of the power-up sequence.
•
When switch S1 is opened, the system starts shutting down. Capacitor C1 starts
discharging through R2. R2 and C1 set the decay rate of Vin during the powerdown cycle.
•
When Vin falls below Vref, comparator U1A's output turns off. This discharges
Vramp through the parallel combination of R5 and R6.
•
As Vramp discharges below V3, V2, and V1, the comparators U1B, U1C and U1D
sequentially turn off their regulator enables.
This example circuit can be easily expanded to support more regulator enable
(reg_en) outputs.
To expand the circuit, add more comparators and extend the resistor ladder network
to generate additional reference voltage comparison points (for example, V4, V5,
etc). Also, increase the Vramp charging/discharging rate to allow more time between
the additional regulator enables. This time delay is controlled by the time constant
determined by R5, R6, and C4.
I/O Management During Power Sequencing
I/O management during power sequencing is essential for Hot-plug systems. Hot-plug
is also known as hot-swap, hot-socketing, or live-plug.
This is a common requirement for high-availability fault-tolerant systems such as
blade-servers, switches, routers and other vital telecommunications and data
communications equipment where the system up-time goal can be as high as
99.999% (also referred to as five 9s).
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
15
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
To achieve this, systems are designed to enable the component boards (line cards) to
be easily expanded or replaced in event of an upgrade or fault condition. Typically, the
system continues to run during the line card expansion / replacement process. System
designers must ensure that the line cards can be safely inserted or removed from the
live system without causing undesirable system operation, failure, or damage.
Hot-Plug Challenges
During hot-plug operations, the unpowered line card presents a large uncharged
capacitive load that appears as an electrical short to the host system's power supply.
The host's supply voltage drops because this instantaneous capacitive load generates
a large inrush current. If the supply drops below the system's minimum operating
voltage, a brown-out condition or system reset can occur. If the inrush current is large
enough the connectors, PCB traces, and/or devices on the printed circuit board can be
damaged.
Therefore the input impedance to the line card is controlled to limit the inrush current.
This enables the input power to the line card to ramp up slowly.
Note:
•
For using Arria 10 devices in hot-plug applications, follow the power sequence
shown in Figure 1 on page 3.
•
There are hot socket circuits in every 6-pack to monitor VCC, VCCT and VCCR
power level. If any of those power supplies are not at operational level, all PMA
outputs and inputs will be gated low.
Hot-Plug Example
An example hot-plug implementation for Arria 10 devices is shown in the following
figure. This example uses staggered connector pin lengths and a hot-swap controller
to limit the inrush current to the regulators on the line card.
Figure 11.
Hot-Plug Example using Staggered Pin Length Connectors
Backplane/Host System
Line Card
System HighSide VCC
Line Card
VCC
Hot Swap and
Regulators
Card_Present#
Arria 10
FPGA
Signals
Signals
CONF_DONE
Input Signal
CONF_DONE
Backplane
Connectors
Card Present Pin
Signal Pins
Power Pins
GND Pins
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
16
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
Backplane/
Host System
Line Card 1
Line Card
VCC
System HighSide VCC
Hot Swap and
Regulators
Card_Present#
Signals
Backplane
Connectors
Arria 10
FPGA
CONF_DONE
Input Signal
CONF_DONE
Line Card 2
Line Card
VCC
System HighSide VCC
Hot Swap and
Regulators
Card_Present#
Signals
Backplane
Connectors
Arria 10
FPGA
Arria 10
FPGA
CONF_DONE
Input Signal
CONF_DONE
Line Card n
Line Card
VCC
System HighSide VCC
Hot Swap and
Regulators
Card_Present#
Signals
Backplane
Connectors
CONF_DONE
Input Signal
Card Present Pin
Signal Pins
Arria 10
FPGA
CONF_DONE
Power Pins
Ground Pins
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
17
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
GND
System High Side VCC
Z
I/O
I/O Driver
Delay
Card Present#
100 ms
Group 1
Group 2
Group 3
Configuration
Configuration Status
CONF_DONE
Note:
This document does not address all the available hot-plug schemes. Other hot-plug
implementations can be used. Designing specific hot-plug implementations are up to
the system designer based on the system's specific requirements.
Hot Swap Controller and Regulator
The circuit operation is divided into two important events:
1. Hot Insertion
2. Hot Removal
Figure 12.
Hot Swap Controller and Regulator Circuit Details
High-Side VCC
Backplane
Connector
From Host
To Host
RSENSE
24/48 V
VCC
FET
Regulator
Vin Vout
Hot-Swap
Controller
Vreg1
Vin Vout
intvcc
SENSE GATE
en
pg
ON
EN1
Power Down
en
pg
Vreg2
Vin Vout
Card_present#
EN2
en
en
VCC2
pg
Vregn
Vin Vout
EN3
Sequencer IC
VCC1
VCCn
pg
Hot Insertion Operation
Initially the line card slot is empty and a high voltage level on the card present
signal informs the host to tri-state all slot I/O signals.
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
18
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
When the line card is inserted, the ground pins mate, connecting the signal return
path. Then the second tier power and signal pins mate. The short delay between the
mating of the ground pins and second tier power and signal pins enables the ground
bounce to settle.
After the power and signal pins mate, the host system high-side VCC (assume 24V or
48V) powers on the first stage regulator (assume 12V). The hot-swap controller, sense
resistor Rsense, and power transistor (FET) control the inrush current ramp rate. The
impedance of the FET is controlled by softly turning on the FET after sensing the input
current across sense resistor Rsense. This enables the line card's input voltage to
pre-charge gracefully.
The high input voltage (low input current) and low on-resistance of the FET (R ds(on))
limits any DC IR drop concerns.
After the input voltage rises to a working level, the 12V regulator's output starts
ramping up. When this output voltage is within 90% of its final value, the power good
(pg) signal starts the sequencer. This enables the down-stream regulators (Vreg1,
Vreg2, and Vregn) to power up in a pre-programmed sequence. The host continues to
keep the line card I/O pins in a tri-state condition and the I/O pins can mate without
any issues.
When the line card is fully engaged, the card present indicator informs the host
that a new card has been successfully inserted. The CONF_DONE signal should then be
routed back to the master and sampled as an enable to the signals that will be driven.
This ensures that configuration is done, the device is stable, and that the master can
drive the I/O to the newly powered up slave device without fear of damaging the part.
The host system drives the line card's I/O pins and configures it for normal operation.
Hot Removal
When the line card is ejected, the card present pin breaks first. This informs the
host to tri-state the line card's I/Os and initiate a power down. After tri-stating the
I/Os, the host drives the power-down signal to the sequencer to start the reverse
power-down sequence. Because the power-down signal from the host and the power
good signal are both open drain type, there is no contention.
The power-down sequence is completed before the second tier power and I/O pins
disconnect. The high-side power is removed from the line card when the power pins
break contact. At the end, the ground pins disconnect and the card is safely removed.
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
19
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
Managing Uncontrolled Loss of Power Events
Sudden loss of power events such as a utility grid blackout, accidental removal of the
system power cable, or other uncontrolled loss of power events can create difficult
power management scenarios for the system designer. To manage these types of
exceptions with Arria 10 and Stratix 10 FPGA devices ensure the power management
design incorporates these features:
1.
Loss of power detection
2.
Hold-up capacitor to keep the Power Management Controller operational during
shutdown
3. Reset logic to the FPGA and/or system to minimize power consumption during
shutdown
4.
Figure 13.
Rapid discharge circuit for each power group to minimize power-down time
Managing Uncontrolled Power Loss Events
The following figure shows a conceptual implementation for managing uncontrolled
power loss events.
DC Input
Power
DC Input High-Side Voltage (12 V)
C_hold
Vin
EN
Vout
VRM1
Group 1 Power
C_Decap Group 1
R_discharge 1
Power Loss
Detection
and Reset
Logic
Vin
Reset
(NCONFIG = 0)
Vdd
(5 - 12 V)
EN
Group 2 Power
Vout
VRM2
C_Decap Group 2
R_discharge 2
EN1
Power
EN2
Management
Controller EN3
Vin
EN
Group 3 Power
Vout
VRM3
C_Decap Group 3
R_discharge 3
The Power Management Controller is powered directly from the 12V high-side DC
input voltage, but can operate down to 5V. C_hold is used to maintain sufficient
charge to keep the Power Management Controller operational during loss of power
events. C_Decap Group 1-3 represents the total decoupling capacitance associated
with each power rail grouping. R_discharge 1-3 and its associated power FETs enable
fast discharging of each power group voltage to 0V when a shutdown sequence is
initiated. The fast discharging circuit is used to speed up the power down cycle of each
rail as the natural RC discharge decay is very slow. Without the fast discharge circuit,
the shutdown time will be very long, requiring the C_hold to be impractical in size.
Theory of Operation
While the system is running, the high-side DC input is maintained at 12V +/-10%
tolerance. The power loss detection circuit continuously monitors the DC input for a
loss of power event. This detection circuit can be a simple comparator with a reference
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
20
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
voltage set to a threshold slightly below the -10% threshold, or it can be an Analogto-Digital Converter (ADC) employing multiple successive samplings to discriminate
against false power interruptions.
When the DC input voltage drops below 10% of nominal and a valid loss of power
event occurs, the detection circuit generates a reset to the system. The reset signal
pulls the FPGAs’ NCONFIG signal low to reduce the device’s operational current to just
its static quiescent value. Concurrently, the Power Management Controller is triggered
to initiate a shutdown sequence. Because of the reduced current and the wide
operating voltage range of the Power Management Controller (5V–12V), the value of
C_hold needed to support the Power Management Controller during the shutdown
process is minimized.
Figure 14.
Power Loss detection and Shutdown Event
Following figure illustrates a power loss detection event
Power While
System Is Running
Power
Loss of Power Detected When
Power Is Below Preset Threshold
Power Drops When System Is
Reset and NCONFIG Is Pulled Low
(Only Leakage Currents)
C_hold Allows Power to Decay
Slowly Due Over ∆t Time to Allow
Power Management Controller
to Perform Shutdown Sequence
Power Below Which System Can
No Longer Function
∆t
Time Available to Perform
Power-Down Function
Time
The ∆t time that the Power Management Controller has to perform a graceful powerdown is dependent on the total power consumption of the system and C_hold
capacitor needed to maintain reliable system power. While the individual power groups
are being disabled in reverse sequential order, the FET for each particular group is also
successively turned on to facilitate a rapid discharge of the respective power rail to
ground through the R_discharge resistors. The discharge FET and resistor must be
properly sized to handle the instantaneous discharge current through it. The discharge
resistor must be able to handle the single pulse power load for the duration of the
discharge time. You can determine this from the data sheet of the selected resistor.
This data is typically provided as a graph plotting the Maximum pulse load power
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
21
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
versus the Pulse duration for various resistor package sizes. The value of C_hold is
determined from the energy stored in the capacitor and the total power required to
maintain system operation. C_hold is calculated from the following equations:
ΔE
Power =
=
Δt
Chold =
1
2
C(v21 - v22)
(t1 - t2)
2 × ( PFPGA leakage + PSystem peripherals ) × (t1 - t2)
Eff x (v21 - v22)
E = Energy stored in the capacitor in Joules
P = Power in Watts
V = Voltage in Volts
C = Capacitance in Farads
t = Time in Seconds
Eff = Efficiency percentage of the regulator
Example Design
Consider an FPGA system that has total quiescent current of 25A when the system is
under reset (FPGA leakage and total system standby current), and the hold time of
the capacitor needs to be 1ms as the voltage drops from 10V to 5V. Also, assume that
the voltage rail is 0.9V.
Determine the C_hold capacitance required for the Power Management Controller to
maintain operation so that a proper power down sequence can be completed.
From the above equation, C_hold = (2 * 25A * 0.9V * .001s) / (0.85 * (10^2 -5^2))
= 706 uF
References
•
Quad-Comparator Circuit Provides Power-Down Sequencing At Low Cost,
How2Power Today, Josh Mandelcorn
•
Hot Swap Power Management, Texas Instruments Corporation, Dave Olson
•
Understanding Hot Swap: Example of Hot-Swap Circuit Design Process, Analog
Devices, Marcus O'Sullivan
•
Design Considerations for Hot Swap, Quarch Technology
•
Introduction to Hot Swap, Planet Analog, Jonathan M. Bearfield
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
22
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
Document Revision History
Table 1.
Document Revision History
Date
Version
Changes
May 2017
2017.05.08
Made the following changes:
• Added the following description for power down sequence for Arria 10
and Stratix 10 Devices "For Arria 10 and Stratix 10 devices, when the
Group 3 power rails are 1.8V and share the same voltage regulator,
then the Group 3 power rails can be combined with Group 2 power
rails. In this case, Group 2 and Group 3 power rails can ramp down
together." Updated the diagrams accordingly.
• Added the following note in "Hot-Plug Challenges" topic: "There are
hot socket circuits in every 6-pack to monitor VCC, VCCT and VCCR
power level. If any of those power supplies are not at operational
level, all PMA outputs and inputs will be gated low."
October 2016
2016.10.31
Made the following changes:
• In the section "Hot Swap Controller and Regulator" updated the
description to "When the line card is fully engaged, the card present
indicator informs the host that a new card has been successfully
inserted. The CONF_DONE signal should then be routed back to the
master and sampled as an enable to the signals that will be driven.
This ensures that configuration is done, the device is stable, and that
the master can drive the I/O to the newly powered up slave device
without fear of damaging the part. The host system drives the line
card's I/O pins and configures it for normal operation."
• In the "Hot-Plug Example" section added 2 new diagrams for "HotPlug Example using Staggered Pin Length Connectors."
September 2016
2016.09.20
Made the following change:
• In topic "Power Sequence for Arria 10 and Stratix 10 Devices" for
figure "Power-Down Sequence for Arria 10 Devices for combined
Group2 and Group3 powers" edited the description to "During the
power-up/down sequence, the device output pins are tri-stated. Intel
recommends that the input pins should not be driven during this time
to ensure long term reliability of the device."
June 2016
2016.06.16
Made the following changes:
• Added new figures for "Power-Down Sequence for Arria 10 Devices",
"Power-Down Sequence for Stratix 10 Devices" and "Power-Down
Sequence for Arria 10 Devices for combined Group2 and Group3
powers".
• Added the "Power-Up Sequence Considerations for Stratix 10
Devices".
• Added a new section for "Managing Uncontrolled Loss of Power
Events".
• Added a new figure for "Power-Up Sequence for Stratix 10 Devices".
October 2015
2015.1.02
Made the following change:
• Clarified information in the "Power-Up Sequence for Arria 10 Devices"
section.
September 2013
2013.09.06
Initial release to MOLSON.
Power Sequencing Considerations for Arria 10 and Stratix 10 Devices
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