Download Analysis and Design of Quasi- Square Wave Resonant Converters

Analysis and Design of QuasiSquare Wave Resonant Converters
Agenda
1. Quasi-Resonant (QR) Generalities
2. Limiting the free-running frequency
3. Calculating the QR inductor
4. Choosing the Power Components
5. Predicting the Losses of a QR Power Supply
6. Synchronous Rectification
7. Loop Compensation
8. NCP1380, our future QR controller
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2
Agenda
1. Quasi-Resonant (QR) Generalities
2. Limiting the free-running frequency
3. Calculating the QR inductor
4. Choosing the Power Components
5. Predicting the Losses of a QR Power Supply
6. Synchronous Rectification
7. Loop Compensation
8. NCP1380, our future QR controller
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3
What is Quasi-Square Wave Resonance ?
‰ MOSFET turns on when VDS(t) reaches its minimum value.
¾ Minimize switching losses
¾ Improves the EMI signature
valley
MOSFET turns on in first valley
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4
MOSFET turns on in second valley
Quasi-Resonant Operation
‰ In DCM, VDS must drop from (VIN + Vreflect) to VIN
‰ Because of Lp-Clump network Æ oscillations appear
‰ Oscillation half period:
Vin
VDS
Lp
Cout
1:N
SW
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Rload
Vout
VIN + Vreflect
VIN
Vin
VDS
t x = π LpClump
Clump
Agenda
1. Quasi-Resonant (QR) Generalities
2. Limiting the free-running frequency
3. Calculating the QR inductor
4. Choosing the Power Components
5. Predicting the Losses of a QR Power Supply
6. Synchronous Rectification
7. Loop Compensation
8. NCP1380, our future QR controller
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6
A Need to Limit the Switching Frequency
‰ In a self-oscillating QR, Fsw increases as the load decreases
Higher losses at light load if Fsw is not limited
‰ 2 methods to limit Fsw:
– Frequency clamp with frequency foldback
– Changing valley with valley lockout
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Frequency Foldback in QR Converters
QR mode
Second valley
First valley
‰ In light load, frequency increases and hits clamp
¾ Multiple valley jumps
¾ Jumps occur at audible range
¾ Creates signal instability
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8
Changing Valley
‰ As the load decreases, the controller changes valley (1st to 4th valley
in NCP1380)
‰ The controller stays locked in a valley until the output power changes
significantly.
¾ No valley jumping noise
¾ Natural switching frequency limitation
80000
SWITCHING FREQUENCY (Hz)
70000
60000
50000
4th
3rd
2nd
1st
40000
30000
20000
QR operation
10000
0
0
10
VCO mode
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9
20
30
OUTPUT POWER (W)
40
50
60
Agenda
1. Quasi-Resonant (QR) Generalities
2. Limiting the free-running frequency
3. Calculating the QR inductor
4. Choosing the Power Components
5. Predicting the Losses of a QR Power Supply
6. Synchronous Rectification
7. Loop Compensation
8. NCP1380, our future QR controller
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10
Calculating the QR Inductor
‰ Calculation steps:
1. Primary to secondary turns ratio
2. Primary and secondary peak current
3. Inductance value
4. Primary and secondary rms current
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11
Turns Ratio Calculation
‰ Derate maximum MOSFET BVdss:
Vds , max = BVdss k D
kD: derating factor
‰ For a maximum bulk voltage, select the clamping voltage:
15% derating
Vos
Vreflect
Vos: diode overshoot
‰ Deduce turns ratio:
N s kc (Vout + V f )
N ps =
=
Np
Vclamp
kc: clamping coef.
kc = Vclamp / Vreflect )
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Vds,max
Vclamp
Vclamp = Vds , max − Vin ,max − Vos
12
BVdss
Vbulk,max
How to Choose kc
‰ Choose kc to equilibrate MOS conduction losses and clamping resistor
losses.
800 V MOSFET
600 V MOSFET
3
3
PRclamp
Ptot ≈ 2.8 W
2
PMOS,on @ Vin,min
Ploss (W)
Ploss (W)
2
Ptot ≈ 3.8 W
1
PRclamp
1
PSW,on @ Vin,max
PSW,on @ Vin,max
0
1.2
1.5
PRclamp = kleak
1.8
Pout
kc
2.1
kc
η kc − 1
PMOS,on @ Vin,min
2.4
2.7
0
3
PMOS ,on
1.2
4 Pout 2
= Rdson 2
3η Vin ,min
1.5
1.8
kc
2.1
2.4
⎛ 1
kc
+
⎜⎜
⎝ Vin ,min BVdss k D − Vin ,max − Vos
2
Psw,on
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2.7
BV k − V
−V ⎞
1⎛
= ⎜ Vin ,max + dss D in ,max os ⎟ COSS Fsw,max
2⎝
kc
⎠
3
⎞
⎟⎟
⎠
Primary Peak Current and Inductance
1
Lpri I pri , peak Fswη
2
‰ Pout =
DCM
Ipri,peak
ton
ton
0
toff
tv
toff
tv
‰ Tsw =
I pri , peak L pri
I pri , peak
Vin ,min
Vout + V f
N ps
Pout ⎛ 1
=2
+
⎜⎜
η ⎝ Vin,min Vout + V f
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+
I pri , peak L pri N ps
+ π L pri Clump
⎞
2 Pout Clump Fsw
⎟⎟ + π
η
⎠
Coss contribution
alone.
Lpri =
2 Pout
I pri , peak 2 Fswη
RMS Current
‰ Calculate maximum duty-cycle at maximum Pout and minimum Vin:
d max =
I pri , peak Lpri
Vin ,min
Fsw,min
‰ Deduce primary and secondary RMS current value:
I pri ,rms = I pri , peak
I sec ,rms =
I pri , peak
N ps
d max
3
1 − d max
3
Ipri,rms and Isec,rms
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Losses calculation
Design Example
‰ Power supply specification:
–
Vout = 19 V
–
Pout = 60 W
–
Fsw,min = 45 kHz
–
600 V MOSFET
–
Vin = 85 ~ 265 Vrms
Vbulk
Vout
T1
.
.
Gnd
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Design Example
‰ Based on equations from slides 11 to 14:
¾ Turns ratio:
¾ Peak current:
N ps =
kc (Vout + V f )
BVdss k D − Vin ,max − Vos
I pri , peak =
=
¾ Inductance:
Lpri =
¾ Max. duty-cycle:
d max =
¾ Secondary rms current:
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1.5 × (19 + 0.8)
⇒ N ps ≈ 0.25
600 × 0.85 − 375 − 20
N ps
2 Pout ⎛ 1
+
⎜⎜
η ⎝ Vin,min Vout + V f
⎞
2 Pout Clump Fsw
⎟⎟ + π
η
⎠
2 × 60 ⎛ 1
0.25 ⎞
2 × 60 × 250 p × 45k
+
⎜
⎟ +π
0.85 ⎝ 100 19.8 ⎠
0.85
2 Pout
2 × 60
=
I pri , peak 2 Fswη 3.322 × 45k × 0.85
¾ Primary rms current:
17
=
I pri , peak Lpri
Vin ,min
Fsw,min =
I pri ,rms = I pri , peak
I sec ,rms =
⇒ Lpri = 285 µH
3.32 × 285µ
45k ⇒ d max = 0.43
100
d max
0.43
= 3.32
3
3
I pri , peak
N ps
⇒ I pri , peak = 3.32 A
⇒ I pri ,rms = 1.26 A
1 − d max 3.32 1 − 0.43
=
3
0.25
3
⇒ I sec ,rms = 5.8 A
Agenda
1. Quasi-Resonant (QR) Generalities
2. Limiting the free-running frequency
3. Calculating the QR inductor
4. Choosing the Power Components
5. Predicting the Losses of a QR Power Supply
6. Synchronous Rectification
7. Loop Compensation
8. NCP1380, our future QR controller
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18
MOSFET
‰ TO220 package: RθJA = 62 °C / W
‰ Ambient temperature: TA = 50 °C, MOS junction temperature: TJ = 110 °C
Power dissipated by TO-220 without heatsink:
MOS RDS(on) @ TJ = 110 °C:
Assume we do not
want a heatsink
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RDSon120 =
PTO − 220
TJ − TA
=
≈ 1W
RθJA
PTO − 220
1
=
= 0.6 Ω
2
2
I pri , RMS
1.3
!
15 A, 600 V MOSFET
MOS Heatsink
‰ We choose a 7 A, 600 V MOS: RDS(on)120 = 1.2 Ω, RDS(on)25 = 0.6 Ω
MOS conduction losses:
Tj
Pcond = RDS ( on )120 I pri ,rms 2 = 1.2 × 1.262 = 1.9 W
Thermal resistance of the heatsink:
Rθ SA
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TJ − TA
110 − 50
=
− Rθ JC − Rθ CS =
− 2.5 − 1.6 = 27 °C / W
Pcond
1.9
Output Diode
‰ TO-220 package Æ power dissipation: 1 W
I
Rd
‰ MBR20200: VT0 = 0.60 V, Rd = 20 mΩ
V
VT0
Diode conduction losses:
Pdiode = VT 0 I out + Rd I sec ,rms 2
Pdiode = 0.60 × 3.2 + 0.02 × 5.82 = 2.60 W
Heatsink:
Rθ SA =
TJ − TA
110 − 50
− Rθ JC − Rθ CS =
− 2.0 − 1.6
Pcond
2.6
Rθ SA ≈ 19 °C / W
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21
Output Capacitor Selection
‰ Maximum output voltage ripple: Vripple = 2%Vout =0.38 V
Maximum ESR of output capacitor:
RCout ≤
Vripple
I sec , peak
0.38
=
≈ 30 mΩ
13.2
RMS current circulating in Cout:
I Cout , RMS = I sec ,rms 2 − I out 2 = 5.82 − 3.22 ≈ 4.83A
Two 1200-µF capacitors (3.2 Arms, 13 mΩ / capacitor)
Losses in Cout:
PCout = RCout I Cout , RMS 2 = 6.5m × 4.832 = 0.15W
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Agenda
1. Quasi-Resonant (QR) Generalities
2. Limiting the free-running frequency
3. Calculating the QR inductor
4. Choosing the Power Components
5. Predicting the Losses of a QR Power Supply
6. Synchronous Rectification
7. Loop Compensation
8. NCP1380, our future QR controller
www.onsemi.com
23
Origin of Losses
.
OUT
.
GND
Conduction losses in ESR of capacitor, diodes, clamp resistor, sense resistor
Conduction and switching losses in MOSFET
Copper and core losses in inductor
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Switching Losses at Turn-On
‰ Traditional approach:
Psw,on
⎛
Vout + V f
1
= COSS ⎜ Vin ,min −
⎜
2
N ps
⎝
2
⎞
⎟⎟ Fsw
⎠
1
19 + 0.8 ⎞
⎛
= 200 p ⎜100 −
⎟ 45k = 2 mW
2
0.25 ⎠
⎝
2
C OSS (V DS ) =
‰ Use the variable capacitor for losses calculation:
Psw,on
Vout + V f
2⎛
= ⎜ Vin ,min −
3 ⎜⎝
N ps
3
2
⎞
⎟⎟ CDO VO Fsw
⎠
C DO
V
1 + DS
VO
CDO
COSS
2⎛
19 + 0.8 ⎞
= ⎜100 −
⎟
3⎝
0.25 ⎠
3/ 2
200 p 25 45k = 3.6 mW
Losses are negligible!
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25
VO
Bulk Capacitor Losses
‰ Power losses caused by ac current in the bulk capacitor ESR (350 mΩ)
Pbulk = Rbulk I bulk ,rms 2
I bulk ,rms = I in ,mean
I in,rms
I in,ac
2
3Fline tc
=
I bulk,rms
−1
Cbulk
I in,mean
Flyback
Conduction time of diode bridge
tc =
1
4 Fline
⎛ Vmin
arcsin ⎜
⎜ V peak
⎝
−
2π Fline
I bulk ,rms = 0.70
⎞
⎟⎟
⎠ = 3 ms
2
− 1 = 1.3 A
3 × 50 × 3m
Pbulk = 350m × 1.32 = 0.59 W
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Vpeak= 120 V
Vmin= 70 V
tc
Diode Bridge Losses
I
‰ KBU4K
‰ From datasheet curves: VT0 = 0.70 V , Rd = 70 mΩ
Rd
‰ There are two diodes conducting at the same time.
V
‰ Two diodes always conduct during half a cycle:
Pdiodes
VT0
I in ,mean
⎛
⎞
= 2 ⎜ VT 0
+ Rd I d ,rms 2 ⎟ = 2 × 0.7 × 0.35 + 70m ×1.042 = 640 mW
2
⎝
⎠
I in ,mean
0.70
I d ,rms =
=
= 1.04 A
3 Flinetc
3 × 50 × 3m
(
)
‰ As two diodes always conduct, over a cycle, the bridge power is:
PKBU 4K = 2 Pdiodes = 1.28W
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RCD Clamp Losses
‰ Power losses in clamping resistor:
PRclamp =
Vclamp
2
Vds,max
Rclamp
Vos
Vclamp
‰ Rclamp can be calculated with:
Rclamp
Rclamp
⎛
Vout + V f
2Vclamp ⎜ Vclamp −
⎜
N ps
⎝
=
Fsw Lleak I peak 2
⎞
⎟⎟
⎠
19 + 0.8 ⎞
⎛
2 ×120 ⎜120 −
⎟
0.25 ⎠
⎝
=
= 7 k Ω ⇒ Rclamp = 7.3 k Ω
2
45k × 2.8µ × 3.32
PRclamp
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Vbulk,max
1202
=
≈ 2W
7.3k
Inductor Losses
P Rpri = R pri ,dc I in ,mean + R pri ,ac I pri ,ac
2
PRsec = Rsec , dc I out 2 + Rsec ,ac I sec ,ac 2
2
Lleak2
Lleak1
R pri
Rac
Rdc
.
Lm
Rc
R sec
.
Core losses:
Determined from data provided by
the manufacturer
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29
Losses Summary for the 19 V / 60 W Adapter
2.6 W
2W
.
1.28 W
OUT
0.15 W
.
2.32 W
GND
0.59 W
1.9 W
0.33 W
‰ Total losses:
Ploss = 11.14 W
‰ Estimated efficiency:
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η=
Pout
60
=
≈ 84.4 %
Pout + Ploss 60 + 11.14
Comparison with Real Adapter
C1
10n
R4
12k
T1:
R11
18k
Nps = 1 : 0.25
Npaux = 1 : 0.18
Lp=290 µH
Rx
10
-
+
R18
10k
.
D5
1N4937
X18
KBU4K
IN
R6
340k
D6
1N4148
C5b
1.2mF
C6
22p
C9
220nF
X2
1
8
2
7
3
6
4
5
Gnd
25V
C15
2.2nF
Type = Y1
T1
Gnd
R5
27k
R9
1k
C13
100u
D4
1N967
C7
100uF
35V
NCP1380
18 mH
2A
L1
C5a
1.2mF
35V
R1
1.3MEG
C18
100nF
D2
MBR20200
.
D1
1N4937
C14
100u
.
Vout
L3
2.2u
Vdrain
D7
1N4148
M1
SPP07N60
R16
10
R29
1k
R15
1k
R7
39k
C10
47n
D3
1N4148
R2
1k
C5
1n
C8
220p
C3
100n
X6
NTC
C11
4.7u
Q1
BC857
R3
47k
R26
0.47
R27
0.47
C20
100n
Gnd
‰ Efficiency measured after the EMI filter at 85 Vrms (120 Vdc)
Measured
Pout = 60.1 W
Pin = 70.9 W
η = 84.8%
Calculated
Pout = 60 W
Pin = 71.14 W
η = 84.4%
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31
X5
TL431_G
R8
10k
Agenda
1. Quasi-Resonant (QR) Generalities
2. Limiting the free-running frequency
3. Calculating the QR inductor
4. Choosing the Power Components
5. Predicting the Losses of a QR Power Supply
6. Synchronous Rectification
7. Loop Compensation
8. NCP1380, our future QR controller
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32
Synchronous Rectification
‰ High rms currents in secondary side Æ increased losses in the output
diode.
‰ Replace the diode with a MOSFET featuring a very low RDS(on).
+
-
Increased efficiency
Degraded standby power
Vout
.
Cout
.
Q sync
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33
Gnd
Synchronous Rectification Basics
‰ During (t2-t1), current flows into the body diode
‰ Minimize (t2-t1) duration to reduce body diode conduction.
Vout
.
Cout
.
Q sync
Gnd
‰ Body diode conducts before the MOSFET is turned-on.
No switching losses
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34
Rload
Losses in the Sync. Rect. Switch
PQsync = PON + PQdiode
‰ Body diode conduction losses
Body diode and MOS conduction
losses for the 19 V/65 W adapter
PQdiode = V f I out Fswtdelay
1
PON = RDS ( on )120 I sec ,rms
2
Ploss (W)
Low if tdelay small
‰ MOSFET conduction losses
PON
0.8
0.6
0.4
0.2
PQdiode
0
200
Vin (V)
300
‰ Losses in the Sync. Rect. switch are mainly conduction losses.
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Choosing the Sync. Rect. MOSFET
‰ Target around 1 W conduction losses in Sync. Rect. switch to avoid
using an heatsink.
RDSon120 =
Vout = 19 V
Fsw,min = 45 kHz
Universal mains
1W
I sec , RMS 2
RDSon120 = 70 mΩ
Ploss (W)
6
MBR20200
RDSon120 = 50 mΩ
4
RDSon120 = 30 mΩ
2
0
1
2
3
4
Iout (A)
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36
5
6
60 W QR Sync. Rect. Calculations
‰ Body diode losses:
PQdiode = V f I out Fswtdelay = 0.7 × 3.2 × 45000 × 70n
PQdiode = 7 mW
‰ MOSFET losses:
PON = RDS ( on )120 I sec ,rms 2 = 30m × 5.82
PON = 1W
‰ Total Sync. Rect switch losses: PQsync = 1 + 0.007 ≈ 1W
‰ Losses into the MBR20200 diode: 2.6 W
Power loss saving: 1.6 W
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Using NCP4302
NCP4302
CS input connected to
the drain of the MOSFET
Trigger input for CCM.
Connect it to Gnd if not
used.
1
Sync
Vcc 8
7
DRV
3
2
Trig
4
5
Dlyadj
Adjust:
- minimum on-time of the Sync. MOSFET
- the minimum off-time of the Sync. MOSFET
to be immune to drain ringing of the primary
switch.
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Gnd 6
TL431 Cathode
TL431 VREF input
Measured Efficiency with Sync. Rect.
Vout
L7
2.2u
T1
.
C5ax
1.2mF
.
C5bx
1.2mF
35V
M2
C19
100uF
35V
Gnd
25V
IRFS4320
D²PAK
Gnd
R31
10
R24
1k
R10
75
D8
1N4148
X8
DIP4302
R25
1k
1
Sync
7
DRV
3
2
Trig
4
5
Dlyadj
6
R33
15k
Vcc
R17
27k
C3
47n
8
R30
110k
R19
39k
R20
10k
Gnd
‰ Efficiency measured after the EMI filter at 85 Vrms
Measured
Pout = 60.1 W
Pin = 69.25 W
η = 86.8%
Calculated
Pout = 60 W
Pin = 69.54 W
η = 86.3%
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Measured efficiency with Diode and Sync. Rect.
Efficiency vs Output Power ( 1 W to 0.5 W)
Efficiency vs Output Power (60 W to 6 W)
90
68
87
86
Efficiency (%)
Efficiency (%)
Sync.Rect. 230 V
Diode 230 V
Sync.Rect 110 V
Diode 110 V
70
89
88
85
84
83
Sync.Rect. 230 V
Diode 230 V
Sync.Rect 110 V
Diode 110 V
82
81
15
25
35
45
55
64
62
60
58
56
80
5
66
65
0
0.2
230 Vrms
Standby power
85 Vrms
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0.6
0.8
1
Pout (W)
Pout (W)
40
0.4
Diode
Pin = 110 mW
Sync. Rect.
Pin = 140 mW
Diode
Pin = 90 mW
Sync. Rect.
Pin = 122 mW
1.2
Agenda
1. Quasi-Resonant (QR) Generalities
2. Limiting the free-running frequency
3. Calculating the QR inductor
4. Choosing the Power Components
5. Predicting the Losses of a QR Power Supply
6. Synchronous Rectification
7. Loop Compensation
8. NCP1380, our future QR controller
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41
Power Stage
‰ Borderline Conduction Mode Approximation.
‰ Neglect the high frequency Right Half Plane Zero (RHPZ)
Open loop transfer function of power stage
⎛
⎞
ηVIN Rload
RESR Cout s + 1
v$ out ( s )
= H (s) =
⎜⎜
⎟⎟
$v FB ( s )
2α Rsense ( 2Vout + N psVIN ) ⎝ ( Req + RESR )Cout s + 1 ⎠
N ps
Vout
R ESR
Lp
Vin
R load
C out
QR
Controller
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42
2Vout + N psVIN
Gnd
α: internal dividing ratio
R sense
VFB
Req = Rload
Vout + N psVIN
between FB and CS from
datasheet (typically 3 or 4)
The Optocoupler Pole
‰ Parasitic capacitance of optocoupler Î opto pole
Vdd
sopto =
1
1 + sR pullup Copto
Vout
R pullup
R LED
a
c
C opto
Optocoupler
characterization reveals
a pole at 5 kHz
k
e
‰ If fopto close to fc (Rpullup high) Î phase margin degradation
Include the optocoupler pole in the power stage to calculate the phase shift
at the crossover frequency.
H (s) =
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ηVIN Rload
( RESRCout s + 1)
2α Rsense ( 2Vout + N psVIN ) ( ( Req + RESR )Cout s + 1)( R pullup Copto s + 1)
Compensating the QR with TL431
Vout
R LED
Vdd
R upper
R pullup
C zero
VFB
TL431
R lower
C pole
Gnd
Low frequency zero
R pullup
VFB ( s )
G(s) =
= −CTR
Vout ( s )
RLED
Mid-band gain
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44
⎛ sRupper C zero + 1 ⎞ ⎛
1
⎜⎜
⎟⎟ ⎜⎜
⎝ sRupper C zero ⎠ ⎝ 1 + sR pullup C pole
Pole at the origin
⎞
⎟⎟
⎠
High frequency pole
Compensating the QR Converter
‰ Calculate fc according to specified Vout undershoot for an output step load.
ΔI out
fc ≈
ΔVout Cout 2π
‰ Calculate RLED to boost the gain at crossover.
60
10
−
H ( fc )
20
fc
30
|H(f)| (dB)
RLED = CTR
R pullup
)
0
− 30
− 60
1
10
100
3
1×10
f
frequency
(Hz)
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45
1×10
4
1×10
5
K Factor Method
‰ Needed phase boost:
Selected phase
margin
Power stage
phase shift
⎛ Boost
⎞
k = tan⎜
+ 45 ⎟
⎝ 2
⎠
-101°
− 60
− 90
− 120
Selected
cross over
frequency
− 150
− 180
1
10
100
1×10
3
1×10
frequency (Hz)
‰ Place the zero at frequency: fc/k
C zero =
‰ Place the pole at frequency: k*fc
C pole =
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46
PS
− 30
Arg [H(f)] (°)
Boost = PM − PS − 90
0
1
2π Rupper
fc
k
1
2π R pullup kf c
4
1×10
5
Loop Compensation Example
‰ Specification: ΔVout = 230 mV for ΔIout = 2.8 A
ΔI out
2.8
=
⇒ f c = 800 Hz
ΔVout Cout 2π 230m × 2.4m × 2π
RLED = CTR
R pullup
10
− H ( fc )
20
18k
= 0.6
10
22
20
≈ 1 kΩ
‰ Needed Phase Boost:
Boost = PM − PS − 90 = 70 − (−101) − 90 = 81°
Gain (dB)
‰ Calculated mid-band gain: 18.6 dB
)
60
200
48
160
36
120
24
80
12
0
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0
a
− 12
− 40
− 24
− 80
− 36
− 120
− 48
− 160
− 60
⎛ 81
⎞
10
k = tan ⎜ + 45 ⎟ 12.5
⎝ 2
⎠
1
1
C zero =
=
= 38 nF ⇒ C zero = 47 nF
fc
800
2π × 66k ×
2π Rupper
12.5
k
1
1
C pole =
=
= 0.8 nF ⇒ C pole = 1 nF
2π R pullup kf c 2π × 18k × 12.5 × 800
47
40
PM
100
3
1×10
Frequency (Hz)
4
1×10
− 200
5
1×10
Phase (°)
fc ≈
G( f ) H ( f )
Measurement versus Calculation
‰ Power stage gain and phase
-- Measured gain
-- Measured phase
-- Calculated gain
-- Calculated phase
The RHPZ is around 20 kHz.
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Measurement versus Calculation
‰ Loop gain and phase
-- Measured gain
PM
-- Measured phase
-- Calculated gain
-- Calculated phase
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Agenda
1. Quasi-Resonant (QR) Generalities
2. Limiting the free-running frequency
3. Calculating the QR inductor
4. Choosing the Power Components
5. Predicting the Losses of a QR Power Supply
6. Synchronous Rectification
7. Loop Compensation
8. NCP1380, our future QR controller
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NCP1380 Features
‰ Operating modes:
– QR current-mode with valley lockout for noise immunity
– VCO mode in light load for improved efficiency
HV-bulk
‰ Protections
FB
2
CS
3
GND
4
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NCP1380 C/D
Rstart
1
‰ Sampling date: end of January 09
‰ Mass production: end of Feb. 09
51
Ct
ZCD / OPP
8
Dovp
OVP/BO
7
Vcc
6
DRV
5
Czcd
Over power protection
Soft-start
Short circuit protection
Over voltage protection
Over temperature protection
Brown-Out
Rbou
Rzcd2
–
–
–
–
–
–
Rzcd1
Rbol
Ct
Cvcc
Control Topology Comparison
Fixed Fsw
Quasi Resonant
Fixed On Time
(FOT)(NCP1351)
Variable
(max power
at max Fsw)
Best
Frequency
Fixed
Light load
efficiencies
Normal
(with skip mode
or freq foldback)
Normal
Variable
(max power
at min Fsw)
Valley jumping
problem (noise)
Max Fsw at min Pout
Variable
(min Pout at
min Fsw)
Best
Best
Normal
Best
BCM (Borderline)
CCM/DCM
BCM/DCM
Transformer size Normal
Larger
Normal
Normal
EMI
Smaller
Normal
Smaller
Full load
efficiencies
Operating mode
CCM/DCM
Normal
QR-FOT
(NCP1380)
QR-FOT: your key to improve standby (FOT) and optimize both
efficiency and EMI (QR) for a wide output power range !!!
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QR Mode with Valley Lockout
‰ As the load decreases, the controller changes valley (1st to 4th valley)
‰ The controller stays locked in a valley until the output power changes
significantly.
¾ No valley jumping noise
¾ Natural switching frequency limitation
80000
SWITCHING FREQUENCY (Hz)
70000
60000
50000
4th
3rd
2nd
1st
40000
30000
20000
QR operation
10000
0
0
10
VCO mode
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20
30
OUTPUT POWER (W)
40
50
60
VCO Mode
‰ Occurs when VFB < 0.8 V (Pout decreasing) or VFB < 1.6 V (Pout increasing)
‰ Fixed peak current (17.5% of Ipk,max), variable frequency set by the FB loop.
Ipk max
Constant peak current (17.5% of Ipk max)
Fsw1 @ Pout1
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54
Fsw2 @ Pout2
Pout1 > Pout2
OPP: How does it Work?
‰ Laux with flyback polarity swings to –NVIN during the on time.
‰ Adjust amount of OPP voltage with Ropu // Ropl.
‰ VCS,max = 0.8 V + VOPP
Ropu
Peak current
set point
CS
ZCD/OPP
OPP
IpFlag
1
Aux
Ropl
ESD
protection
100%
V ILIMIT
60%
+
-
Demag
Vth
leakage blanking
DRV
Tblank
Non dissipative OPP !
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55
370
VIN (V)
NCP1380 Versions
‰ 4 versions of NCP1380: A, B, C and D
OTP
OVP
NCP1380 /
A
X
X
NCP1380 /
B
X
X
Auto-Recovery
Latched
Over current protection
Over current protection
X
X
NCP1380 /
C
X
X
NCP1380 /
D
X
X
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BO
X
X
Short-Circuit Protection
‰ Internal 80-ms timer for short-circuit validation.
‰ Additional CS comparator with reduced LEB to detect winding short-circuit.
‰ VCS(stop) = 1.5 * VILIMIT
S
Q
DRV
Q
R
CS
LEB1
Rsense
+
FB/4
PWMreset
-
Down
Up
OPP
Reset
V ILIMIT
grand
reset
Laux
LEB2
+
-
V CS(stop)
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TIMER
IpFlag
ZCD/OPP
CsStop
Stop controller
Short-Circuit Protection (A and C Versions)
‰ A and C versions: the fault is latched.
¾ VCC is pulled down to 5 V and waits for ac removal.
S
DRV
Q
Q
Vdd
R
aux
Vcc
latch
VCC
management
CSstop
fault
CS after LEB1
+
FB/4
+
V ILIMIT
grand
reset
PWMreset
Down
Up
IpFlag
TIMER
Reset
-
+
V OPP
S
Q
+
CS after LEB2
CSstop
Q
-
VCS(stop)
t LEB2 < t LEB1
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58
R
grand
reset
VCCstop
SCR delatches
when
ICC < ICCLATCH
Short Circuit Protection (B and D)
‰ Auto-recovery short circuit protection: the controller tries to restart
‰ Auto-recovery imposes a low burst in fault mode.
Low average input power in fault condition
S
Q
to DRV stage
Vdd
aux
Q
R
Vcc
VCC
management
fault
CS after LEB1
+
FB/4
+
V ILIMIT
grand
reset
VCCstop
Down
Up
IpFlag
TIMER
VCC
Reset
-
+
V OPP
grand
reset
+
CS after LEB2
-
VCS(stop)
t LEB2 < t LEB1
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PWMreset
CSstop
VDS
OVP / OTP (A & B Versions)
‰ OVP and OTP detection are achieved by reading the voltage on the pin 7.
‰ If the temperature increases, the NTC resistor reduces and VFault decreases.
When VFault < VOTP Î the controller is latched.
‰ If VCC increases, the zener diode injects current in the clamp circuit.
When VFault > VOVP Î the controller is latched.
Vcc
Vdd
VOVP
noise delay
-
Dz
IOTP(REF)
+
OVPcomp
Fault
7
S
Q
Rclamp
Clamp
-
Vclamp
VOTP
R
OTPcomp
SS end
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60
Q
+
NTC
noise delay
grand
reset
Latch
BO / OVP (C & D Versions)
¾ If Vpin7 > BO threshold & VCC > VCCon, the controller starts pulsing.
¾ The hysteresis current source is ON when Vpin7 > BO threshold.
BO
HV-Bulk
noise delay
Vcc
+
S
S
Dz
VOVP
Rbou
DRV
Q
-
Q
Q
Latch
Q
OVP/BO
R
7
Vdd
R
IBO
grand
reset
Rbol
noise delay
Rclamp
Clamp
+
BO reset
Vclamp
OVP
VBO
¾ If VCC > BVDz, the zener diode injects current inside the clamp resistor.
¾ When Vpin7 reaches the OVP threshold, the controller is latched.
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61
CS comp
Conclusion
‰ Changing valley as the load decreases is a way to limit the maximum
switching frequency in QR power supplies.
‰ Lots of equations to predict the efficiency of the power supply, but good
matching between calculations and the measurement.
‰ Synchronous rectification increases the efficiency of the QR power
supply but increases also the power consumption in standby.
‰ Friendly compensation for QR power supply (DCM: 1st order system)
‰ NCP1380 features:
• QR current-mode with valley lockout for noise immunity for high load.
• VCO mode in light load for improved efficiency.
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For More Information
•
View the extensive portfolio of power management products from ON
Semiconductor at www.onsemi.com
•
View reference designs, design notes, and other material supporting
the design of highly efficient power supplies at
www.onsemi.com/powersupplies
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