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Design Methodology © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies The Design Productivity Challenge 100,000,000 10,000,000 100,000 10,000 58%/Yr. compound 1,000,000 Complexity growth rate 100,000 10,000 1,000 100 1,000 Productivity growth rate 10 100 21%/Yr. compound 2009 2005 Produc 2001 1993 Logic Transistors per Chip (K) Productivity (Trans./Staff-Month) 10,000,000 1981 Logic Transistors per Chip (K) 1,000,000 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005 2007 2009 A growing gap between design complexity and design productivity Source: ITRS’97 © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies The Custom Approach Intel 4004 © Digital Integrated Circuits2nd and F. BrewerCourtesy 2003 Intel Design Methodologies Transition to Automation and Regular Structures Intel 4004 (‘71) Intel 8080 Intel 80286 © Digital Integrated Circuits2nd and F. BrewerCourtesy 2003 Intel Intel 8085 Intel 80486 Design Methodologies Automating Design Exploitation By Algorithms Regular Structures Logic Synthesis Regularization of Connection Floorplanning (Localization of function) System Level Performance/Power/Cost Allocation of Physical Resources Communication/Interconnect Hierarchy based on Sensitivity to Latency Wires to Link Protocols © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies A System-on-a-Chip: Example Courtesy: Philips © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies Design Methodology • Design process traverses iteratively between three abstractions: behavior, structure, and geometry • More and more automation for each of these steps © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies Floorplanning A Protocol Processor for Wireless © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies Implementation Choices Digital Circuit Implementation Approaches Custom Semicustom Cell-based Standard Cells Compiled Cells Macro Cells © Digital Integrated Circuits2nd and F. Brewer 2003 Array-based Pre-diffused (Gate Arrays) Pre-wired (FPGA's) Design Methodologies None 1-10 Embedded microprocessor Configurable/Parameterizable 10-100 Hardwired custom Energy Efficiency (in MOPS/mW) 100-1000 Domain-specific processor (e.g. DSP) Impact of Implementation Choices 0.1-1 Somewhat flexible © Digital Integrated Circuits2nd and F. Brewer 2003 Fully flexible Flexibility (or application scope) Design Methodologies Implementation Strategies PLA Technology confined in cell macros (tiling) Cell based logic Technology confined to cells (area) Both 1-d and 2-d solutions Transistor Arrays (Gate arrays) Technology confined to layers (Below M1 fixed) © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies PLA: Programmable Logic Array Product terms x0 x1 x2 AND plane OR plane f0 x0 x1 f1 x2 © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies Two-Level Logic Every logic function can be expressed in sum-of-products format (AND-OR) minterm Inverting format (NORNOR) more effective © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies PLA Layout – Exploiting Regularity V DD And-Plane x0 x0 x1 x1 x2 x2 Pull-up devices © Digital Integrated Circuits2nd and F. Brewer 2003 Or-Plane f GND f0 f1 Pull-up devices Design Methodologies Breathing Some New Life in PLAs River PLAs BUFFER PRE-CHARGE A cascade of multiple-output PLAs. Adjacent PLAs are connected via river routing. PRE-CHARGE BUFFER PRECHARGE BUFFER PRE-CHARGE BUFFER PRE-CHARGE BUFFER PRE-CHARGE BUFFER PRECHARGE BUFFER BUFFER PRE-CHARGE • No placement and routing needed. • Output buffers and the input buffers of the next stage are shared. © Digital Integrated Circuits2nd and F. BrewerCourtesy 2003 B. Brayton Design Methodologies Area: RPLAs (2 layers) 1.23 SCs (3 layers) 1.00, NPLAs (4 layers) 1.31 Delay RPLAs 1.04 SCs 1.00 NPLAs 1.09 Synthesis time: for RPLA , synthesis time equals design time; SCs and NPLAs still need P&R. delay Experimental Results 1.4 1 0.6 Also: RPLAs are regular and predictable 0.2 0 Layout of C2670 Standard cell, 2 layers channel routing 2 SC Standard cell, 3 layers OTC Network of PLAs, 4 layers OTC © Digital Integrated Circuits2nd and F. Brewer 2003 4 NPLA 6 area RPLA River PLA, 2 layers no additional routing Design Methodologies 2-d Cell Based: “Hard” Modules 25632 (or 8192 bit) SRAM Generated by hard-macro module generator © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies 1-d Cell-based Design (standard cells) Feedthrough cell Logic cell Routing channel Rows of cells Functional module (RAM, multiplier, ) © Digital Integrated Circuits2nd and F. Brewer 2003 Routing channel requirements are reduced by presence of more interconnect layers Design Methodologies Standard Cell — Example [Brodersen92] © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies Standard Cell – The New Generation Cell-structure hidden under interconnect layers © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies Standard Cell - Example 3-input NAND cell (from ST Microelectronics): C = Load capacitance T = input rise/fall time © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies “Soft” MacroModules Synopsys © Digital Integrated Circuits2nd and F. Brewer 2003 DesignCompiler Design Methodologies The “Design Closure” Problem Iterative Removal of Timing Violations (white lines) Courtesy © Digital Integrated Circuits2nd and F. Brewer 2003 Synopsys Design Methodologies Gate Array — Sea-of-gates polysilicon VD D rows of uncommitted cells metal possible contact GND In1 In2 Uncommited Cell In3 In4 routing channel Committed Cell (4-input NOR) Out © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies Sea-of-gate Primitive Cells Oxide-isolation PMOS PMOS NMOS NMOS NMOS Using oxide-isolation © Digital Integrated Circuits2nd and F. Brewer 2003 Using gate-isolation Design Methodologies Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA300K (0.6 mm CMOS) © Digital Integrated Circuits2nd and F. Brewer 2003 LSI Logic Courtesy Design Methodologies The return of gate arrays? Via programmable gate array (VPGA) Via-programmable cross-point metal-5 metal-6 programmable via Exploits regularity of interconnect © Digital Integrated Circuits2nd and F. Brewer 2003[Pileggi02] Design Methodologies Pre-wired Arrays: Classification of prewired arrays (or fieldprogrammable devices): Based on Programming Technique Fuse-based (program-once) Non-volatile EPROM based RAM based Programmable Logic Style Array-Based Look-up Table Programmable Interconnect Style Channel-routing Mesh networks © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies Fuse-Based FPGA antifuse polysilicon ONO dielectric n+ antifuse diffusion 2l Open by default, closed by applying current pulse © Digital Integrated Circuits2nd and F. Brewer 2003 From Smith’97 Design Methodologies Array-Based Programmable Logic I5 I4 I3 I2 I1 I0 Programmable OR array Programmable AND array I3 I2 I1 I0 Programmable OR array Fixed AND array PLA (flexible – sizing) I4 I3 I2 I1 I0 Fixed OR array Programmable AND array O3O2O1O0 O 3O 2O 1O 0 I5 PROM (dense) O 3O 2O 1O 0 PAL (uniform load) Indicates programmable connection Indicates fixed connection © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies Programming a PROM 1 X2 X1 X0 : programmed node NA NA f 1 f 0 © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies 2-input mux as programmable logic block Configuration A 0 F B 1 S © Digital Integrated Circuits2nd and F. Brewer 2003 A B S F= 0 0 0 0 X Y Y 1 1 1 0 X Y Y 0 0 1 0 0 1 0 1 1 X Y X X X Y 1 0 X Y XY XY XY X +Y X Y 1 Design Methodologies Logic Cell of Actel Fuse-Based FPGA A B 1 SA 1 Y C D 1 SB S0 S1 © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies LUT-Based Logic Cell C1....C4 4 H1 H2 H0 EC S/R control D4 D3 Logic function D2 F D1 Din F’ G’ H’ Logic function H D SD Q F3 F2 G YQ EC RD G’ H’ 1 F4 Logic function Bypass Y S/R control Din F’ G’ H’ D SD Q Bypass XQ F1 clock Xilinx 4000 Series EC RD H’ F’ 1 X Multiplexer Controlled by Configuration Program © Digital Integrated Circuits2nd and F. BrewerCourtesy 2003 Xilinx Design Methodologies Array-Based Programmable Wiring M Interconnect Point Programmed interconnection Input/output pin Cell Horizontal tracks Vertical tracks © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies Mesh-based Interconnect Network Switch Box Connect Box Interconnect Point © Digital Integrated Circuits2nd and F.Courtesy Brewer 2003 Dehon and Wawrzyniek Design Methodologies Transistor Implementation of Mesh © Digital Integrated Circuits2nd and F.Courtesy Brewer 2003 Dehon and Wawrzyniek Design Methodologies Hierarchical Mesh Network Use overlayed mesh to support longer connections Reduced fanout and reduced resistance © Digital Integrated Circuits2nd and F.Courtesy Brewer 2003 Dehon and Wawrzyniek Design Methodologies Altera MAX © Digital Integrated Circuits2nd and F. Brewer 2003 From Smith97 Design Methodologies Altera MAX Interconnect Architecture column channel row channel t PIA LAB1 LAB2 LAB PIA t PIA LAB6 Array-based (MAX 3000-7000) Mesh-based (MAX 9000) © Digital Integrated Circuits2nd and F. BrewerCourtesy 2003 Altera Design Methodologies Field-Programmable Gate Arrays Fuse-based I/O Buffers Program/Test/Diagnostics Vertical routes I/O Buffers I/O Buffers Standard-cell like floorplan Rows of logic modules Routing channels I/O Buffers © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies Xilinx 4000 Interconnect Architecture CLB 12 Quad 8 Single 4 Double 3 Long 2 3 12 4 4 8 Quad Long Global Long Clock 4 8 4 Double Single Global Direct Connect Long 2 Carry Direct Clock Chain Connect © Digital Integrated Circuits2nd and F. BrewerCourtesy 2003 Xilinx Design Methodologies RAM-based FPGA Xilinx XC4000ex © Digital Integrated Circuits2nd and F. BrewerCourtesy 2003 Xilinx Design Methodologies Design at a crossroad 500 k Gates FPGA MultiSpectral + 1 Gbit DRAM RAM Imager Preprocessing 64 SIMD Processor Array + SRAM Image Conditioning 100 GOPS Analog System-on-a-Chip mC system +2 Gbit DRAM Embedded applications: cost, performance, and energy are the issues! DSP and control intensive Mixed-mode Software design is crucial Recognition © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies Addressing the Design Complexity Issue Architecture Reuse Reuse comes in generations Generation Reuse element Status 1st Standard cells Well established 2nd IP blocks Established- marginal 3rd Architecture Need for Standards 4th IC Marketing Hype 5th Software Current Practice © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies Heterogeneous Programmable Platforms FPGA Fabric Embedded memories Embedded PowerPc Hardwired multipliers Xilinx Vertex-II Pro Courtesy: Xilinx © Digital Integrated Circuits2nd and F. Brewer 2003 High-speed I/O Design Methodologies Summary Design Choice forced by System Tradeoffs Deep Sub-micron Challenges Regularity (Design flexibility at smallest scales) Power consumption! Interconnection Parasitics Nanoscopic Devices/Modules New circuit solutions are bound to emerge Who can afford design in the years to come? © Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies