Download Impact of Supply Voltage Biasing - UVA ECE Wiki

Supply Voltage
Biasing
Andy Whetzel and Elena Weinberg
University of Virginia
Agenda
• Background
o FinFET technology
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Problem and approach
Our design
Implementation
Results
Discussion
Conclusion
Background
FinFET Technology
• Scalable
• Higher drive strength per unit silicon
Image from:
Image from:
http://www.ece.uc.edu/~kroenker/Research/Research%20Project%20S http://www.siliconsemiconductor.net/images/news/i
ummaries/FINFET_image004.jpg
mage-76523-2012-12-12.jpg
Problem
Body biasing does not work on FinFETs
• MOSFET vs. FinFET:
https://www.semiwiki.com/forum/content/attachments/5665d1355855218-planar-vs.-3d-finfet.jpg
Approach
Supply voltage biasing with FreePDK
Contributions:
1. Our design for supply voltage biasing
2. A new knob
3. A new technique for decreasing delay in
integrated circuits (ICs) implementing FinFET
technology
Supply Biased Inverter
Gate
Ring Oscillator
• 11 Inverters
• Swept bias voltage
from -0.1 V to 0.1 V
o 1.1 V nominal
• Measured frequency,
active power, and
static power vs. bias
voltage
Ring Oscillator Results
Active Power vs. Supply Bias
Frequency vs. Supply Bias
2
Normalized Power
1
0.8
0.6
0.4
0.2
0
-0.15
-0.1
-0.05
0
0.05
1.5
1
0.5
0
-0.15
0.1
-0.1
-0.05
Bias (V)
60
50
40
30
20
10
0
-0.15
0
Bias (V)
Static Power vs. Supply Bias
Normalized Power
Normalized Freq.
1.2
-0.1
-0.05
0
Bias (V)
0.05
0.1
0.15
0.05
0.1
0.15
NAND and NOR Gates
• Designed similarly to supply biased inverter
o Double the transistors, one high and one low output
• Setup in ring oscillator configuration such that high
output is tied to NMOS and low output is tied to
PMOS in subsequent gate
• Results were similar, therefore we obtained the
motivation to pursue combinational logic other
than a ring oscillator
Full Adder
8 Bit Ripple Carry Adder
Delay vs. Supply bias
Switching Power vs. Supply Bias
2.5
Normalized Power
Normalized Delay
1.5
1
0.5
0
-150
-100
-50
0
50
100
150
2.0
1.5
1.0
0.5
0.0
-150
-100
-50
Bias (mV)
Normalized Static Power
Normalized Static Power
1.0
0.8
0.6
0.4
0.2
0.0
-80
-60
Bias (mV)
100
150
Static Power vs. Supply Bias
1.2
-100
50
Bias (mV)
Static Power vs. Reverse Supply
Bias
-120
0
-40
-20
0
70
60
50
40
30
20
10
0
-150
-100
-50
0
Bias (mV)
50
100
150
Discussion
• Our design shows potential to reduce delay in ICs
Trade-offs:
• Area
• Power
Conclusion
• We successfully designed and implemented a new knob
• Our design decreases delay in ICs implementing FinFET
technology
• Area and power trade-offs
Future Work
• Further investigation of static and switching power in
FinFETs under supply bias
• Explore accuracy of gate induced drain leakage (GIDL)
• Generating bias voltages
Questions?
Image from: http://www.synopsys.com/Company/Publications/SynopsysInsight/Pages/Art2-finfet-challenges-ip-IssQ3-12.aspx