Download Soft lithography fabrication of all-organic bottom

APPLIED PHYSICS LETTERS 88, 023506 共2006兲
Soft lithography fabrication of all-organic bottom-contact and top-contact
field effect transistors
P. Cosseddu and A. Bonfiglio
INFM-University of Cagliari, Department of Electric and Electronic Engineering, Piazzo d’ Armi, 09123
Cagliari, Italy and INFM-S3 NanoStructures and BioSystems at Surfaces, Modena, Italy
共Received 5 April 2005; accepted 22 November 2005; published online 13 January 2006兲
All-organic field effect transistors on flexible plastic substrates have been fabricated. A thin Mylar®
foil acts both as substrate and gate dielectric. The contacts have been fabricated with
poly共ethylene-dioxythiophene兲/polystyrene sulfonate 共PEDT/PSS兲 by means of soft lithography.
The active layer 共pentacene兲 is vacuum sublimed on the prepatterned film in case of bottom-contact
devices or, in case of top-contact devices, the active layer sublimation is made in advance. On the
opposite side of the foil, a thin PEDT/PSS film, acting as gate electrode, is spin coated. The
comparison between top-contact and bottom-contact devices shows interesting characteristics as a
marked difference in the ID versus VD curve that can be mainly attributed to a different quality of
PEDT/PSS-semiconductor contact. The flexibility of the obtained structure and the easy scalability
of the technological process open the way for economic production of high resolution organic
devices. © 2006 American Institute of Physics. 关DOI: 10.1063/1.2166487兴
Organic materials, based on conjugated organic small
molecules and polymers, offer the opportunity to produce
devices on large-area low-cost plastic substrates,1 A fundamental issue in device fabrication concerns the availability of
suitable materials not only for the active semiconductor layer
but also for contacts that so far, have been mainly fabricated
with metals. Metals show several problems: first, though deposited in very thin layers, they are not mechanically flexible, and this could compromise the overall robustness of
devices; secondly, organic semiconductors offer the possibility of employing very simple and low cost techniques2 for
device assembly, as printing, spin coating, etc., that cannot
be applied to metals. Therefore, in an industrial perspective,
it would be desirable to employ a unique, easy technique to
obtain each layer of the device. Printing contacts with conductive polymers3,4 is one possibility, but it has several limits, as the spatial resolution of the printed pattern, and the
compatibility between the employed “ink” and the printing
hardware.5 Furthermore, the realization of top-contact devices is very critical, as the solvents employed for contact
printing may affect the underlying semiconductor.
Soft lithography6 represents a step forward to obtain low
dimension structures through a reliable, low cost, easy, and
reproducible method. It has been successfully applied to organic materials and devices, with very interesting results
concerning the lamination of metal contacts7 or the transfer
of metal contacts mediated by surface chemistry treatments.8
These findings are attractive as they open a possibility
to fabricate flexible and efficient devices with very low
dimensions.
In this letter, we report about the application of a
soft lithographic technique to obtain all-organic field effect
devices in a very simple and efficient way. In these devices,
source, drain, and gate contacts have been realized
with poly共ethylene-dioxythiophene兲/polystyrene sulfonate
共PEDT/PSS兲 that has been applied by means of a polydimethylsiloxane 共PDMS兲 stamp and by spin coating. It is
worthwhile noting that both top-contact 共T-C兲 and bottomcontact 共B-C兲 devices can be easily obtained with this
technique. In the following, we propose a comparison be-
tween the two structures that puts in light, in particular, the
role of the electrode/semiconductor interface in the device
performances.
Pentacene films have been considered as active material
because of their high hole field effect transistor 共FET兲
mobility 共up to 0.1 cm2 / Vs兲.9
Figure 1 shows the possible structures for the device. A
1.9 ␮m thick Mylar® sheet 共Du Pont兲, adapted to a plastic
frame 共not visualized in the figure兲, has been employed as
substrate and gate insulator 共dielectric constant of 3.0兲. The
sheet has a dielectric rigidity of 105 V / cm allowing one to
apply a gate bias sufficiently high to induce a field-effect in
the organic semiconductor. Completely flexible devices, such
as organic thin-film transistors 共OTFTs兲 and field effect
chemosensors, can be realized by employing this kind of
film.10,11 As it can be seen in Fig. 1共a兲, B-C PEDT/PSS
source and drain electrodes have been patterned on one side
of the dielectric using a soft lithographic technique followed
by the thermal evaporation of the organic semiconductor. In
Fig. 1共b兲, a T-C device is shown, where the two contacts
have been deposited with the same technique after thermal
evaporation of the organic semiconductor. In both cases, the
FIG. 1. Structure of the devices. The pentacene layer was patterned on B-C
devices in order to leave an uncovered area on both source and drain for
gold tips contact.
0003-6951/2006/88共2兲/023506/3/$23.00
88, 023506-1
© 2006 American Institute of Physics
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023506-2
Appl. Phys. Lett. 88, 023506 共2006兲
P. Cosseddu and A. Bonfiglio
FIG. 2. ID-VD curves of B-C 共a兲 and T-C 共b兲 devices.
gate electrode has been obtained by spin coating a PEDT/
PSS thin film on the opposite side of the insulator. Electrodes
with W / L = 200 共W and L are the channel width and length,
respectively兲, with L = 25 ␮m, have been used, but the dimension of the contacts can be much lower because the only
limit for soft lithography is due to the relief dimensions in
the master used for the stamp fabrication. Fabrication of
masters for soft lithography with feature size of less than
1 ␮m is pretty common.12 Prior to deposition, the substrate
has been cleaned with ethanol, isopropanol, and dried in N2
flux. Pentacene 共Sigma Aldrich, 98%兲 has been used as received. Pentacene films with a nominal thickness of 50 nm
have been grown by vacuum-sublimation at a nominal deposition flux of about 0.5–1 Å / s. Such a deposition rate has
resulted to be optimal for obtaining homogeneous films of
Pentacene on Mylar®. A pentacene layer was patterned during deposition by interposing a mask between the pentacene
crucible and the sample. This was done, both for T-C and for
B-C devices, with the aim of leaving a portion of electrode
area, not superposed to the semiconductor, where probe tips
were put during the electrical measurements. In this way, any
risk of a direct contact between the tips and the semiconductor is prevented. Source and drain definition by soft lithography required a very careful processing. First the stamp was
put, with the relieves exposed upwards, on the basis of a spin
coater and a small amount of PEDT/PSS 共Baytron CPP
D105兲 was dropped on its surface. After a resting time of
about 10 min, in order to allow solvent evaporation and to
help adhesion between the ink and the PDMS substrate, the
stamp was spun for 2 min at 1000 rpm in order to obtain a
uniform layer of PEDT/PSS on the surface of the stamp. As
Mylar® does not tolerate thermal treatment over 40 °C, no
annealing step was performed on the PEDT/PSS thin film
after deposition, a step generally made to increase PEDT to
PSS ratio.13 Indeed, a predeposition annealing was realized
at 120 °C, producing an increase of PEDT/PSS conductivity
by a factor of 2 with respect to untreated PEDT/PSS films.
After the stamp preparation, contacts were transferred on
the substrate 共directly on Mylar® in the case of B-C devices,
or on the surface of a pentacene layer, in the case of T-C
devices兲 by realizing a conformal contact between stamp and
substrate, without any external pressure, for about 10 min.
After this time, the stamp was carefully removed resulting in
a transfer of contacts with a pretty high yield 共90%兲. The
contacts so formed were left dry in vacuum for at least 1 h, to
eliminate any solvent trace. Different substrates 共as glass or
silicon wafers兲 for PEDT/PSS stamping can be used with a
similar procedure.
Drain-source current 共Ids兲 measurements have been carried out at room temperature in air. An Agilent HP 4155
Semiconductor Parameter Analyzer provided with gold tip
for contacting the sample has been used to control the gate
voltage 共Vgs兲 and the drain-source voltage 共Vds兲 and to measure Ids 共the source being the common ground兲. In order to
avoid any ageing effect due to pentacene degradation in contact with atmosphere,14,15 all measurements have been performed immediately after pentacene deposition. Atomic
Force Microscopy 共AFM兲 images were obtained by means of
a SPM SOLVER PRO by NT-MDT in semicontact mode.
Figure 2共a兲 shows an example of the output characteristics of a B-C device biased as a p-channel FET working in
accumulation mode, while Fig. 2共b兲 shows the same curve
recorded on a T-C device, with the same geometry, assembled on the same Mylar® film, next to the B-C device. In
this way, the same organic semiconductor is deposited on
both devices and this allows to have the same thickness and
quality of the semiconductor in the channel of each device.
As can be seen, the current recorded in T-C devices is almost
one order of magnitude higher than in B-C devices. To shed
light on this phenomenon, we have taken into account an
equivalent circuit model suggested by Horowitz,16 where a
resistance is inserted in series with the device channel. According to this model, both mobility and series resistance
values have been derived from the output curves. This is
particularly meaningful in this case because the two structures have similar channel characteristics 共so they should
have similar mobility values兲 but differ for the way in which
the contact-semiconductor interface has been formed. In B-C
devices, pentacene is deposited on the PEDT/PSS layer, so
there is a direct carrier injection from the electrode to the
device channel 共according to the idea that the channel is a
very thin layer at the interface between semiconductor and
insulator17,18兲 while in T-C devices, the current injected from
the electrodes must vertically travel through the pentacene
layer before reaching the channel, and this implies that the
effective voltage across the channel is lower than the voltage
applied between source and drain by a quantity RSID, where
ID is the drain current and RS is the equivalent resistance of
the vertical current path in the pentacene layer. In addition, a
contribution to RS may be derived from the contact between
electrodes and semiconductor 共different in the two cases兲.
So, together, these two phenomena 共difference in current
path and a different electrode-semiconductor contact兲 should
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023506-3
Appl. Phys. Lett. 88, 023506 共2006兲
P. Cosseddu and A. Bonfiglio
FIG. 3. Comparison between the RS vs VG curves of a T-C device and a B-C
device.
produce in the electrical curve the effect of a resistance in
series with the device channel and the value of this resistance
can be estimated from the curves as well as carrier mobility.
As a matter of fact, there is a very meaningful difference
in the RS versus VG curve recorded on the two devices: As
can be noticed in Fig. 3, for the B-C device there is a strong
dependence of RS on the gate voltage, while RS is almost
constant with VG 共and substantially lower than in B-C
devices兲 in T-C devices.
These trends are reproducible over tens of devices. On
the other hand, also the recorded mobility is different in the
two cases 共for example, in the case shown in Fig. 2, the
pentacene mobility is, respectively, 9 ⫻ 10−3 cm2 / Vs for the
B-C device and 2 ⫻ 10−2 for the T-C device, values that are
similar to those derived from similar gold-contact devices兲.
Indeed, in all our measurements, the recorded mobility is
always higher in T-C OFETs. It must be noticed that, if the
mobility is calculated from ID versus VG curves in saturation,
without taking into account a resistance effect, the difference
in the mobility recorded in the two devices is much higher
共one order of magnitude兲 and that, when the calculation is
performed with the Horowitz method, the difference between
the two values correctly reduces. Nevertheless, it should be
zero and it is not. This nonzero difference indicates that a
simple model which includes only one parasitic series resistance cannot explain all the characteristics recorded from the
experiments. Furthermore, RS in T-C devices is also almost
independent of the gate voltage. This seems in agreement
with the idea of a resistance effect mainly dependent on the
electrode-semiconductor interface, rather than on the current
path inside the semiconductor. Infact, it is reasonable 共and
already pointed out by other authors兲19 that the carrier injection barrier between the electrode and the semiconductor
could be affected by the carrier density in the semiconductor,
in turn determined by the gate voltage.
In order to check the quality of contacts, we have
performed AFM measurements on our devices. Figure 4
shows the AFM image taken on a B-C device. The pentacene
layer has been observed in different areas: in the channel
center 关Fig. 4共a兲兴, over a PEDT/PSS contact 关Fig. 4共b兲兴, and
at the boundary between the channel and the contact in a
bottom-contact device 关Fig. 4共c兲兴.
As can be seen, there is a relevant difference in the morphology of the pentacene film deposited on the different device regions and an abrupt transition between the channel
and the contact. In particular, the morphology is everywhere
granular, but the grain size is sensibly different in the two
zones. This difference obviously does not exist in T-C devices where no discontinuity exists in the pentacene layer
between the channel area and the under-contact zone. As a
consequence, the interface between the contact and the semiconductor layer in T-C devices is much more uniform and
not affected by border discontinuities.
In summary, B-C and T-C OFET devices with source
and drain contacts made by PEDT/PSS have shown electrical
characteristics 共carrier mobility and resistance in series with
the channel兲 comparable to those of traditional metal/
semiconductor interfaces,20 and, as also observed by other
authors with different assembly techniques,21 T-C devices
perform better than B-C devices. More important, our results
demonstrate that it is possible to obtain T-C devices thanks to
soft lithography in a simple way and without the dimension
limits imposed by shadow masks. Taking advantage of the
possibility of fabricating high-resolution masters for soft lithography, attractive developments of this device structure
can be envisaged. Indeed, very low dimensions of contacts
can be obtained either for B-C or for T-C devices with such
a simple and low-cost technique that can be a valuable alternative to printing for the production of all polymers devices.
The authors acknowledge the Italian Ministry for
Research program under project FIRB.
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