Download Efficiency improvement of crystalline silicon solar cells

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and processes for energy: communicating current research and technological developments (A. Méndez-Vilas, Ed.)
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Efficiency improvement of crystalline silicon solar cells
M. Al-Amin1 and A. Assi*2
1
2
Microsol International LL FZE, Fujairah, United Arab Emirates
Department of Electrical and Electronic Engineering, Lebanese International University, Beirut – Lebanon
To increase the efficiency and reduce the production cost of crystalline silicon (c-Si) solar cells, efforts in the photovoltaic
industry are currently put on the process optimization of the cell. Sodium hydroxide/Potassium hydroxide (NaOH/KOH)
and isopropyl alcohol (IPA) are widely used in the standard alkaline texturization of mono crystalline silicon (mc-Si)
wafers for enhancing the optical efficiency, where IPA promotes the formation of pyramidal structure but unfortunately
leads to unstable process. In this work, carbohydrates are investigated as an additive in the etchant solution; its capability
to replace IPA as texturing solution is discussed. A pre-texture cleaning agent is introduced to remove the organic residue
from the textured surface. Moreover, uniform phosphorus diffusion process for B2B (back to back) diffusion is
investigated with single and multiple temperature plateaus. Impact of a pre-oxygen step on the phosphorus diffusion is
investigated where number of inactive phosphorus at the PSG (phosphosilicate glass)-Si interface is reduced. Anti
reflection coating (ARC) of the silicon nitride (SiNx) dielectric layer and sintering process are also optimized to improve
the passivation and reduction of series resistance (Rs). A batch of 156mm2 pseudo square (PSQ) mc-Si cells was fabricated
using the above mentioned suggestions. The estimated average efficiencies is 18%-18.25%, compared to the standard
process it is higher by ~0.75-1.0 %. For the improved process, surface morphology, reflectance factor (RF), sheet
resistance(SR) uniformity, carrier effective life time (τeff), open circuit voltage (Voc), short circuit current (Isc), fill factor
(FF), shunt resistance (Rsh), peak power (Ppk) and efficiency(η) are given and compared with the standard process of solar
cells.
Keywords:Solar cells; Sodium hydroxide; isopropyl alcohol; reflectance factor; cell efficiency; standard process.
1. Introduction
In order to reduce the process cost, most of PV industries use the fundamental fabrication process shown in Fig. 1. An
automated advanced technology increases the efficiency of solar cells, but unfortunately increases significantly the
process cost due to higher equipment and maintenance additional costs. Recent surveys indicate that the commercial PV
cell price varies in the range of 0.4-0.5 $/Wp where the wafer cost is 65% of the total cost [1]. To reduce the material
cost, the wafer substrate is cut with 150-200 µm thickness whereas further decrease in the wafer thickness increases the
possibilities of breaking wafers and therefore lowers their production yield. Recently, considerable efforts were made
in the process of optimization to increase cell efficiency without adding extra cost to the process. For the mc-Si solar
cells, typical efficiencies lie between 17-18 % which need to be increased to make it competitive with conventional
energy forms [2]. Current status of mc-Si solar cell processing and attempts to achieve high efficiencies will be
described in the following sections of this paper.
Texturization
Phosphorus
Diffusion
Edge
Isolation
AR
Coating
Metallization
Sintering
Character
-ization
Fig 1. Standard process sequence in single crystalline silicon solar cell fabrication.
2. Standard Process of mc-Si Solar Cells
2.1 Silicon substrate
In general, silicon wafers produced using Czochralski (CZ) method are classified according to their crystal orientation,
doping type, resistivity, thickness, concentration of oxygen, and carbon [3, 4]. The mc-Si wafers has <100> crystal
orientation with PSQ geometry (i.e. cylinders are shaped as squares with rounded off corners). The geometry and
crystal orientation have strong influence on the optical and electrical performance of solar cells; this will be detailed in
later sections [5]. Most of the PV industries today use mc-Si wafers, the mc-Si have lower defects compared to other
types of wafers, mc-Si solar cells are used to maximize the power density in the PV module and to reduce the cost per
unit energy. However, the wafer’s size and thickness are limited to the ability to handle the wafer during cell
processing. Recently continuous efforts have been put on multi-wire saw technology to cut thinner wafers and reduce
material consumption. A wafer with 120-150 µm thickness produced with an advanced technology is feasible and
thickness is expected to decrease further in the coming years [6] but it requires an automated handling process to
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increase the yield of solar cell processing. Furthermore, reducing the wafer thickness affects the electrical performance,
of solar cells, and a compromise in-between material consumption and power output is needed [5].
The concentration of foreign particles such as oxygen, carbon, and metallic impurity during the wafer processing is
an important factor that limits the efficiency of solar cells [7]. Due to the presence of carbon-oxygen(C-O) complex
particles, a dark ring known as swirl defect appears which degrades the cell performance [8]. In addition, precipitation
metal during wafer processing affect the p-n junction behaviour, which needs a gettering process to improve the wafer
quality [9]. The minority τeff is considered a key parameter to evaluate the wafer quality as well as the whole process
performance. The bulk resistivity which determines the base doping concentration, carrier recombination and metallic
defect concentration strongly affects the cell performance [3, 4].
Most of industrial solar cells are based on p-type wafers and n-type diffused emitter. It is well known that power is
degraded in p-type cell by 3-5 % due to minority carrier life time degradation which is a result of boron-oxygen related
metastable defect under illumination [10, 11]. On the other hand, n-type wafer having very high τeff and long diffusion
length, is getting more and more attention for solar cell production. Moreover, n-type solar cells are not prone to LID
(light induced degradation) and less sensitive to chemical and mechanical impurities. The highest efficiency with back
contact technology has been reported by Sunpower and Sanyo but wafer price still needs to be reduced to make it
competitive [11].
2.2 Etching and texturization
Silicon substrates contain surface saw damage that needs to be etched off at the beginning of the process by several
microns on both sides. Usually aqueous alkali solution of NaOH or KOH with >5 % concentration is heated to 80-90 ˚C
are used for the first removal of saw damage, electrically inactive or dead layer, for the as-cut wafer. The overall
chemical reaction generally accepted are summarized in equation 1- 4 [12]. The etching rate of silicon depends on the
product of hydroxide ions ([OH]-) and free water concentration ([H2O]) [13]. Recently ingot cutting technology has
been significantly improved which reduced the importance of having an etching process [6]. We note here that mirror
polished wafer is not suitable for higher wetability and therefore leads to non-uniform nucleation of pyramid. After the
etching process, the surface of produced solar cells becomes shiny and the average reflectance factor is more than 35 %
[14].
Na /K + OH
NaOH/KOH
Si + 4OH → Si(OH)
Si(OH) + 2OH → SiO (OH)
4H O + 4e → 4OH + 2H
(1)
(2)
(3)
(4)
+ 2H O
The absorption of incident light by the solar cell is increased by applying a geometrical surface texture to the front
surface which increases the coupling of reflected rays and therefore the average reflection reduces to less than 10 %
[14]. Among the various texturization methods used: mechanical, plasma, and chemical, the chemical method is well
established in the PV industries. The mechanism of texturization for mc-Si is explained in the following sections.
2.2.1 Alkaline texturization of mc-Si solar cells
For mc-Si solar cells, an anisotropic texturization is applied using alkaline solution, KOH/NaOH, at 70-80˚C and
1-2 wt %. To control the etching rate an appropriate additive, IPA, is added to the etchant solution. The added IPA
removes the hydrogen bubbles from the surface and increases the substrate wetability. The OH- group of IPA sticks at
the surface and acts as etching blocker; which nucleates the pyramid formation and controls the pyramid density and
shape [15]. It has been reported in [16, 17] that the etching rate of <100> oriented crystal is higher than the <111>
which leads to pyramid formation. In order to get uniform texturization, the surface preparation, process temperature,
solution concentration, dosing rate and evaporation rate of IPA are key parameters to be controlled. The surface
morphology of the textured wafer is presented in Figs. 2a and 2b, where the pyramid height is 3-5 µm. The average RF
is decreased from 35 % to ~10 %. To optimize the texturization process, several methods have been examined and the
results have been reported in [13, 18, 19]. However, recent studies have revealed that due to the reduction of wafer
cost, the material quality of CZ-Si wafers differ significantly [20]. It is obvious that minor defects can limit the cell
performance, especially for high efficiency solar cell concept, above 20 % [21]. New wafer cleaning solutions; NaOCl
and KOH, have been introduced to improve the process performance, and will be explained in section 3.1. Another
additive, carbohydrates, has been introduced to eliminate the high evaporation rate of IPA (boiling point 82.4 °C)
during the texture process; the results will be discussed and compared in section 3.2.
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(a)
(b)
Fig. 2 Surface morphology of mc-Si wafer after anisotropic texturization a) top view b) side view.
2.3 Diffusion
In solar cell fabrication, the emitter is formed by using the following methods: ion implantation, epitaxial growth, and
inversion layer [22]. P-type silicon wafers are widely used in PV industries, and therefore diffusion technologies have
been developed to deposit n-type doping elements to create the p-n junction. Along with nitrogen (N2) and oxygen (O2)
gases, phosphorus oxy chloride (POCl3), a source of phosphorus, is also widely used in the standard diffusion process of
solar cells [23, 24]. Due to its low boiling temperature (105.8 ˚C) [25], at temperatures between 850-900 ˚C in the
diffusion chamber, POCl3 is decomposed into simple phosphorus compounds like P4, P8, P2O5, etc. In parallel,
phosphorus compounds react with O2 and create phosphosilicate glass (PSG) [SiO2:P2O5)x] layer on the Si surface. The
phosphorus atoms formed at the PSG-Si interface penetrate through the silicon wafer [22] and can be simplified with
the following reaction equations:
(5)
4POCl + 3O → 2P O + 6Cl ↑
(6)
2P O + 5Si → 4P + 5SiO
In case of infinite doping source, the doping concentration profile leads to an Error function whereas it is Gaussian
function for finite source [22]. In PV industries, doping profiles are being made using a combination of Erf and
Gaussian profile [26]. Comparison between the solid solubility (the maximum number of active phosphorus atoms) at
different temperature and actual doping profile provides the presence of dead layer (inactive phosphorus) and emitter
recombination [27, 28].
The uniformity of phosphorus atom formation is influenced by the characteristic of PSG-Si interface. In general, any
defect in the surface morphology leads to non-uniform phosphorus deposition and therefore improper p-n junction
formation and higher metal induced defect at or near the p-n junction [29]. Non-uniform phosphorus deposition may
cause junction shunting, which can be explained by the metal concentration profile and the p-n junction depth under
metallization, this increases the parasitic losses and lowers FF. Furthermore, non-homogenous phosphorus
concentration distorts the silicon lattice and leads to enhanced defect-assisted recombination [22]. The typical emitter
SR for screen printing metallization process is 60 to 80 Ω/sq where the metallization pattern (front electrode) needs to
be optimized for different SR [30].
2.4 Edge isolation and PSG removal
After the standard batch diffusion process, the phosphorus doped layer (n+) covers the entire surface including edges. It
is extremely important to disconnect the front emitter from the back contact through etching the edge of the cell.
Several inline and batch processes are successfully established; namely chemical etching, plasma etching, laser cutting,
mechanical sawing, grinding with sandpaper, single side etching [31, 32, 33]. Single side etching in PV industries is
widely used. This type of etching has lower parasitic loss and therefore higher FF compared to plasma or laser isolation
processes [32].
In the diffusion process, a glass, known as phosphosilicate glass, of phosphorus pentaoxide (P2O5) and silicon
dioxide (SiO2) are formed due to the uncontrolled amount of dopant and irregular diffusion at the silicon surface. If the
phosphorus concentration exceeds the solid solubility then it precipitates on the surface and leads to PSG layer
formation [34]. The thickness of PSG layer is ~0.03 µm that can be removed by a wet chemical dip by using diluted
hydrofluoric acid (HF) [35].
2.5 Anti reflection coating
Silicon nitride layer (SiNx: H), deposited on the silicon surface using plasma-enhanced chemical vapor deposition, is
used to reduce optical losses and passivate the surface as well as the bulk. [36, 37] Generally two process gases,
ammonia (NH3) and silane (SiH4), are ionized by direct plasma where refractive index (RI) and absorption coefficients
depend on Si/N ratio. The dissociation and formation reactions of the process gases can be summarized as follows [36].
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NH3 + e → NH2 + H + e
SiH4 + e → SiH3 + H + e
SiH4 + e → SiH2 + 2H + e
(7)
(8)
(9)
The process parameters affect only the growth rate of SiNx:H and passivation [5, 36]. Hydrogen atoms in SiNx
saturate the dangling bonds and bulk defects acting as recombination centres [38]. A well passivated surface
significantly reduces the emitter saturation current (Joe) and therefore leads to a higher short circuit current [5]. The
passivation is characterized by measuring the Si-H and N-H concentrations in the SiNx layer [39, 40]. In case of optical
efficiency, SiNx layer with higher RI gives higher extinction coefficient (k) which increases the light absorption by the
layer itself [41]. Moreover, RI needs to be optimized to reduce the potential induced degradation (PID) and optical
losses in the PV module [41, 42].
2.6 Metallization and sintering
In industrial mass production of solar cells the screen printing technology is used to obtain high resolution printing
which is achievable by optimizing and combining the effect of different parameters such as mesh number, wire
diameter, emulsion thickness, tension of the screen, opening of the screen, viscosity of paste, paste temperature,
printing speed and pressure [43].
To form the back surface field via Al-Si alloy, aluminium is usually used to cover the entire back surface of wafer.
Recently a significant progress in paste manufacturing was reported which reduces the bowing of thin Si wafers [44]. In
case of front electrode, printing narrow finger using silver paste (<60 µm), the higher aspect ratio is one of the major
challenges to reduce shading loss without increasing the series resistance [45]. The metallization architecture needs to
be designed according to the characteristics of the diffused emitter [30].
The firing process is done using four steps process in infrared lamp heated belt furnace. First, lower temperature is
applied to dry the paste where all the solvent are evaporated. Improper drying process causes gas bubbles and results in
finger interruption and very high Rs. The second step is known as burn-out in which all the organic binders burn to
gaseous exhaust [43]. It is very important that any presence of carbon particle diffuses through the p-n junction at
higher temperature and results in a higher parasitic loss [43]. After that, the solar cell is fired at temperature range 750850 ˚C where Ag-Si alloy is formed and penetrates through the wafer surface. In order to protect the junction shunting
and reduce Rs, the belt speed and peak temperature need to be optimized [46]. Finally the cell is cooled by forced air
cooling system. The ramp up and down should be maintained preciously to avoid micro crack and crystal defects [47].
3. Improving the efficiency of mc-Si solar cells
Several process optimization techniques such as surface cleaning before texturization, stable texturization, uniform and
lower defect emitter formation, improved surface passivation by optimized SiNx ARC, and lowering the Rs using an
optimized sintering, have been evaluated and explained in details in the following sub-sections. The results were
summarized and compared with the standard process. Finally all the optimized process steps were integrated to fabricate
a mc-Si solar cell in which more than 18.2 % average cell efficiency is observed at industrial scale production.
a)
b)
Fig. 3 a) and b) Surface morphology of textured c-Si wafer with organic residue using SEM for the STD (NaOH-IPA) process
without pre-cleaning
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a)
b)
c)
Fig. 4 a), b) Surface morphology of textured c-Si with residues and micro-holes using SEM for the STD (NaOH-IPA) process
without pre cleaning c) STD (NaOH-IPA) texturization process with NaOCl-KOH pre-cleaning.
12
10
8
6
4
2
0
Pre Cleaning + STD Texture
STD Texture
Texture Process ID
a)
18
16
14
12
10
8
6
4
2
0
100%
Amount of Additive (%)
STD Texture
Etching Depth (micron)
Etching Depth (micron)
Pre Cleaning
14
1.7/5
1.7/7
2/8.5
NaOH (%)/ Carbohydrate
(%)
IPA
Carbohydrate
80%
60%
40%
20%
0%
0
30
60
90
120 150
Process Time (min)
b)
c)
Fig. 5 Comparison a) etching depth of STD texture process with and without pre-cleaning b) etching depth solution with different
concentrations of NaOH and carbohydrate c) % of additive present in the texturization solution
3.1 Optimizing the surface morphology through texture pre-cleaning
The standard (STD) texture process cannot entirely remove the organic particles deposited on the textured surface
which degrades the optical and electrical properties of the solar cell. A significant number of pre-cleaning solutions has
been investigated in solar cell processes such as standard clean (SC1 and SC2) and IPA [48, 49, 50], which increases
the process complexity and therefore reduces the production throughput and increases the fabrication cost. In this work
a new cleaning solution of NaOCl and KOH has been introduced and the effects on the surface contamination, the
optical properties have been investigated.
The surface morphology of a textured c-Si wafer for STD texturization without pre-cleaning is presented in Fig. 3a
and 3b. Since the absorption of incident light on textured surface of solar cell depends on the pyramid structure such as
height and edges, pyramid density, cleanliness of surface [17], a discontinuous layer of micro organic residues degrades
the optical performance. Furthermore, octagonal pyramidal structures are observed in the STD texture process without
pre-cleaning where the relationship between residues and pyramid structure needs to be examined and investigated.
The presence of organic residues on the surface leads to improper pyramid formation. In Fig. 4a, surface morphology
of the textured surface where the peaks of pyramids are covered by residues. Furthermore, micro-holes are formed on
the pyramid’s surface as shown in Fig. 4b. Since micro defects on the surface result in uneven p-n junction formation,
the STD texturization leads to higher parasitic loss [51]. The cleaning solution of NaOCl and KOH removes the
residues from the surface as shown in Fig. 4c where the cleaning mechanism can be explained by equations 10 and 11.
NaOCl decomposes to sodium chlorate and sodium chloride under heat where the presence of KOH delays the
decomposition. The hypochlorous acid acts as a cleaning agent and eliminates residues from the wafer surface. It is
clear that the textured surface has no residues leading to a free surface contamination.
(10)
3 NaOCl → NaClO3 + 2 NaCl
(11)
4 NaOCl + 2 H2O → HOCl +NaOH
To analyze the effect of the pre-textured cleaning process, the comparison of etching depth is presented in Fig. 5a.
The etching depth with pre-cleaning solution is 0.5 to 1.0 µm which is insignificant compared to the STD texturization
which is 12-15 µm. Furthermore, it indicates the presence of enough surface roughness which is one of the key factors
for the pyramid nucleation.
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3.2 Stable alkaline texturization process
IPA evaporates at very high rate due to its lower boiling point (82.4 ˚C), and results in an unstable texture process.
Furthermore, flammable IPA vapor mixes with hydrogen gas (reaction product of Si and alkaline solution) and pollutes
the working environment. Carbohydrates have been examined as an additive and compared to IPA. The advantages of
carbohydrates are (i) improves process stability (ii) less hazardous process environment (iii) reduces process time (iv)
equal or lower reflectivity (v) lower consumption of additive.
Since the etching rate of silicon depends on the product [OH]- and [H2O] [13], a lower concentration of
carbohydrates gives higher etching rate. As the carbohydrate and NaOH concentration increases, [H2O]x[OH]–
decreases and lowers the etching rate. The average wafer thickness loss of different batches with various NaOH and
carbohydrate concentration is presented in Fig.5b. In case of process stability, it is observed that IPA is evaporated by
75-80 % after 60 min process, as illustrated in Fig. 5c, which requires continuous addition of IPA (i.e. increases the
consumption of IPA) during the process and results in a complex control system. In contrast, the evaporation loss of
carbohydrate additives is almost 0 % and results in a more stable process.
Usually light absorption by the silicon wafer mainly depends on the pyramid structure and its uniformity. In case of
low concentration carbohydrate-NaOH texture process, random pyramidal hillocks are observed as presented in Fig. 6a,
which can be attributed to a poor wetability and higher etching rate. Like IPA-NaOH, uniform pyramid structure
(3-5 µm height) has been observed as shown in Fig.6b with higher carbohydrate-NaOH concentration. Compared to the
standard texturization process with IPA, the reflectance factor at different wavelength for different concentration of
carbohydrates additive is shown in Fig. 6c. The reflectance factor for carbohydrate -NaOH is 1 % lower compared to
IPA which is not significant in mass production.
3.3 Improving the emitter characteristic
Reflectance Factor (%)
The phosphorus diffused emitter with low Joe, depends on the junction depth and the uniformity of doping
concentrations (doping concentrations of emitter and base are equal), which is an important factor for high η solar cells.
Increasing the distance between two consecutive wafers (batch process in tube furnace) leads to a uniform deposition of
phosphorus, but this significantly limits the throughput. Loading two wafers in a single slot, known as B2B, increases
the distance between the wafers without reducing the throughput. Furthermore, the introduction of an oxidation step
before injection of phosphorus reduces the un-reacted phosphorus compounds at the PSG and Si interface and leads to a
uniform carrier concentration and junction depth. The comparison of SR is shown in Fig. 7a in which the non
uniformity of the improved process is ±2 Ω/sq compared to ±10 Ω/sq for the STD process.
The τeff for different diffusion processes is presented in Fig. 7b. Compared to the STD diffusion process, τeff is lower
by 10 µs for B2B single temperature plateau which can be attributed to high Joe. Changing the temperature profile to
multiple plateaus reduces Joe and results in 5µs higher life time compared to the STD process. To examine the
correlation between SR and the emitter characteristics, Joe and τeff are compared at different SR values as shown in Fig.
7c. It is observed that 80 Ω/sq SR has 35 fA/cm2 Joe which is lower by ~200 fA/cm2 compared to the case where SR =
50 Ω/sq. This can be attributed to a shallow junction depth and lower phosphorus concentration. However, the high SR
increases Rs and lowers FF; which can be compensated by an emitter with lower SR using lower concentration and
higher junction depth as reported [30]. In contrast with Joe, τeff is increased with SR; it is observed that τeff is 20 µs for
SR = 50 Ω/sq, which increases to ~50 µs for SR=80 Ω/sq.
35,0
30,0
25,0
20,0
15,0
10,0
5,0
0,0
NaOH-IPA
NaOH-Carbohydrates
300
a)
b)
500
700
900
Wavelength (nm)
1100
c)
Fig.6 SEM picture of textured silicon wafer surface using NaOH-carbohydrate, H2O solution. a) 1.7% NaOH – 5.0% carbohydrate b)
2%NaOH - 8.5% Carbohydrate c)comparison of reflectance factor of textured silicon surface for conventional (NaOH-IPA) and
NaOH-carbohydrate process
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Fig. 7 a) The uniformity of sheet resistance for different diffusion process in mc-Si fabrication process b) comparison of effective life
time with standard error bar for different diffusion process c) the comparison of carrier life time and emitter saturation current density
for different SR values.
Short Circuit Current (A)
Open Circuit Voltage
(mV)
622
CT 800Å
CT900Å
CT 1000Å
621
620
619
618
617
616
2,00
2,05
2,10
2,15
Refractive Index
8,80
CT 800Å
CT900Å
CT 1000Å
8,70
8,60
8,50
8,40
8,30
2,20
2,00
a)
2,05
2,10
2,15
Refractive Index
2,20
b)
FF
80,0
Junction saturation
current (nA/cm2)
Fill factor (%)
81,0
79,0
78,0
77,0
76,0
550
600
650 700 750 800
Belt Speed (cm/min)
850
900
J02
Voc
100
640
630
620
610
600
590
10
Open circuit voltage
(mV)
Fig. 8 Comparison of a) Voc b) with different coating thickness and refractive index of SiNx:H ARC.
550 600 650 700 750 800 850 900
a)
Belt Speed (cm/min)
b)
Fig. 9 Comparison of a) FF b) J02 and Voc at constant peak temperature in Datapaq profile as a function of belt speed in a sintering
process.
3.4 Passivation using silicon nitride
To optimize the SiNx characteristics, process parameters are varied for maintaining different coating thickness (CT) and
RI. Fig. 8a and 8b show the variation of Voc and Isc for mc-Si solar cells with different CT and RI of SiNx:H layer.
Irrespective of the CT, Voc is decreased with increasing RI due to a higher porosity. At higher RI, hydrogen atoms
released from Si-H bond instead of passivation and form H2 gas. For RI = 2.00, Voc varies between 618 and 621 mV,
while it varies between 617 and 619 mV at 2.2 RI. It is also observed that, in case of 800Å CT, Voc is lower by 2-3 mV
compared to 1000 Å, which can be attributed to insufficient density of hydrogen atoms.
Compared to CT, the RI has greater impact on the variation of Isc. In general, the k becomes higher at SiNx layer with
higher RI, which increases the absorption of incident light by solar cells [41]. The experimental results show that Isc is
higher by 250-300 mA for RI = 2.0 compared to the case when RI = 2.2. In addition, a thicker SiNx coating has higher
Isc which can be attributed to a better hydrogen passivation and lower Joe of the emitter and the surface.
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3.5 Improving the fill factor using rapid sintering
In the firing furnace, the impact of belt speed on FF, Voc, and J02 at certain peak temperatures (from Datapaq profile) is
presented in Figs. 9a and 9b. It is observed that FF can be increased to 79.6 % with 803 cm/min belt speed which can be
explained by a lower value of J02. A degradation in FF is observed at 876 cm/min belt speed which could be attributed
to higher contact resistance between Ag metal and emitter. In addition to that the junction shunting problem is reduced
significantly at higher belt speed due to lower concentration of Ag at or near the p-n junction. Since higher belt speed
significantly reduces J02 and the damage in the emitter, Voc is increased to 630 mV compared to the case where
Voc = 625 mV in STD process. We note here that the optimum belt speed could be different for different Ag paste in the
front electrode.
4. Summary of the obtained electrical performance
Current (A)
The electrical performance (also known as I-V characteristic) has been evaluated for the standard and the optimized
processes as shown in Fig. 10. Values for Isc, Voc, FF, Ppk and η are summarized in Table 1. It is observed that Voc is
higher by 8 mV due to the improved passivation and lower recombination in the emitter. Isc is increase by 150 mA
because of a uniform texturization. FF is higher by 1 % absolute which can be attributed to a lower metal precipitation
near the p-n junction at quick firing process and lower Rs. In general, compared to the STD, the average cell η is higher
by 0.75-1.0 % absolute for the improved process.
10
9
8
7
6
5
4
3
2
1
0
Improved Process
STD Process
0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
Voltage (V)
Fig 10 Comparison of electrical performance in between improved and standard process.
Table 1 The summary of electrical performance for the improved and STD process
Process
Open Circuit
Short Circuit
Fill Factor,
ID
Voltage,Voc(V)
Current, Isc(A)
FF(%)
Standard Process
0.624
8.60
78.5
Optimized Process
0.632
8.75
79.6
Maximum Power,
Ppk(W)
4.21
4.40
Efficiency,
η (%)
17.63
18.42
5. Conclusions
In this research work, fabrication, characterization, and analysis are presented for large scale production of mc-Si solar
cells. The experimental results showed that pre-texture cleaning process removes external particles and promote free
defects pyramid formation. By changing the additive of the alkaline texture solution, process stability is significantly
increased without degrading the optical efficiency.
The effective life time and junction saturation current are significantly increased in the new diffusion process but it
requires optimum metallization. The electrical performance can be also improved through the optimization of coating
thickness and RI of ARC . The optimum sintering process of metallization improved the emitter quality and
consequently the solar cell’s performance. Compared to the STD, the solar cell’s efficiency is higher by 0.75-1 % abs
for the overall optimization of the fabrication process.
The composition of contamination during the texturization process, and the source of such contamination needs to be
examined. In addition, the doping concentration profile in the emitter and the metal concentration profile under metal
electrodes need to be measured for further investigation of the junction depth and its relation with the electrical
performance. These issues will be considered in as subsequent research work that we have initiated at Microsol.
©FORMATEX 2013
29
Materials
and processes for energy: communicating current research and technological developments (A. Méndez-Vilas, Ed.)
____________________________________________________________________________________________________
Acknowledgement The authors wish to acknowledge Microsol International, University of UAE, and Masdar Institute of
Technology for providing the fabrication and test facilities in this research work.
Nomenclature
mc-Si
CZ
PSQ
IPA
NaOH
KOH
RF
B2B
SR
τeff
Joe
PSG
HF
ARC
SiNx
RI
k
Rs
Rsh
Voc
Isc
FF
Ppk
η
Wp
Mono crystalline silicon
Czochralski
Pseudo square
Isopropyl alcohol
Sodium hydroxide
Potassium hydroxide
Reflectance factor
Back to back
Sheet Resistance
Effective carrier life time
Emitter saturation current
Phosphosilicate glass
Hydrofluoric acid
Anti reflection coating
Silicon Nitride
Refractive index
Extinction co-efficient
Series resistance
Shunt resistance
Open circuit voltage
Short circuit current
Fill factor
Peak power
Efficiency
Watt peak
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