Download CLK - Vlad Niculescu

High Speed Data Acquisition
Techniques
Vlad NICULESCU
Politehnica University of Bucharest
Why do we need a data acquisition system?
• We use a data acquisition chain whenever we want to
analyze an analog signal.
• This problem becomes very challenging when we deal with
high frequency signals. In that case, a high speed A/D
converter is required, as well, in order to satisfy the
Nyquist Theorem.
• Consequently, a high performance processing block will be
necessary. This represents a problem, because a 50MSPS
ADC will require a very powerful microcontroller, so a
classical acquisition chain will not be very efficient. In
order to obtain a better resource management, some
techniques will be presented as follows.
What type of device containing a High Speed
ADC can you build?
• Using some additional electronic components, high speed
acquisition devices can be designed using basic
microcontrollers.
• Examples:
 Energy meters
 Digital oscilloscopes
 Other systems for analyzing fast changing processes
Basic
acquisition
system
A data acquisition chain
Anti aliasing
filter
Analog
Circuit
ADC
uC
However, this talk will be focused on the
two highlighted blocks
Protocol
converter
• The
entire process
by the
clock
In a cycle,
a sampleinissynchronized
stored and sent
to computer
• On every positive edge of the clock, the microcontroller
goes into an interrupt routine
D1
D3
ADC
D4
D5
D6
D7
CLK
D8
Clock source
Digital port
D2
Interrupt pin
uC
So, the microcontroller has to do
the following in one cycle:
1. Store the sample
2. Send it to the computer
Store
Send
Store
Send
Store
Send
TOO SLOW, especially if the microcontroller uses a UART
peripheral to communicate with the computer. Only high
performance microcontrollers have an USB peripheral.
Store a
sample
Send it
to PC
Store a
sample
Send it
to PC
Store a fixed number of samples
Store a
sample
Send it
to PC
Send it to PC
In a cycle,
a sampleinissynchronized
stored in the by
buffer
• The
entire process
the clock
• On every positive edge of the clock, the microcontroller
calls an interrupt routine
D1
D3
ADC
D4
D5
D6
D7
CLK
D8
Clock source
Digital port
D2
Interrupt pin
uC
Buffer
Improvements
•
•
•
•
As the send operation is not performed during the acquisition process, the
transmission speed will not affect the sampling rate
Consequently, the microcontroller just has to process one sample in a cycle
The transmission rate between the data acquisition system and the computer will
impose just the refresh rate.
Thus, frames of high frequency signals can be recorded, but a slow
communication with the computer will make the entire process update quite
slowly
Disadvantages
•
•
•
Even if the process is a faster one now, the steps that must be executed in one
cycle are more complex than they look like.
In order to respond to an interrupt, go in the interrupt function, store the sample
and increment the index, it requires at least 30 assembly instructions, so at least
30 cycles (an assembly line can be executed in more than a cycle).
Example: Using a 40Mhz microcontroller, we can acquire samples with the
40𝑀ℎ𝑧
following rate: 𝐹𝑠 <
= 1.33𝑀𝑆𝑃𝑆
30
Personal Project
•
•
•
•
1MSPS Oscilloscope
2048 samples buffer length
800ms refresh rate
C# GUI
Basic
acquisition
system
A better
approach
• As we concluded in the previous case, the main limit is the processing
speed of the microcontroller
• In order to fix that problem, an additional storage will be included
• In this way, an intermediary SRAM will solve the problem, because it has
a very small memory access time, so it will store samples very quickly
• Even a very basic and cheap SRAM has a memory access time equal to
10 ns
Store a number of samples in
SRAM at high frequency
Download the data from
SRAM to microcontroller
at lower speed
Send the package
to PC
For simplicity, we will consider M=8 and N=17, so a 8 bit data
bus and a 16 bit address bus
Clock bus
Data bus
Clock is generated from the PWM peripheral
of the microcontroller
Address bus
Data bus
ADC
uC
M bit
CLK
CLK INT2
INT1
Out[N-1]
write
SRAM
CLK
Address bus
N-1 bit
N bit
counter
Out[N-2:0]
Step 1: The SRAM is filled with samples from ADC
•
•
•
On
stored into SRAM
Theevery
clock clock
signalcycle,
is setatosample
a high is
value
and
the counter
its output,
so,chosen
along
A particular
valueincrements
equal to 50Mhz
will be
with
it, the
current
address
SRAM
is set
to write
mode in order to point to the
next location
Data bus
ADC
uC
8 bit
CLK
50 Mhz
CLK INT2
INT1
Out[16]
write
SRAM
CLK
Address bus
16 bit
17 bit
counter
Out[15:0]
• When the first 16 bits of the counter are 1, the memory is full.
• The next increment of the counter will switch its MSB to 1,
and will trigger the INT1 interrupt
• Now, the process goes in the second step
Data bus
ADC
uC
8 bit
CLK
50 Mhz
CLK INT2
INT1
Out[16]
write
SRAM
-full-
CLK
Address=65536
17 bit
counter
Out[15:0]
Step 2: Samples are downloaded from SRAM to uC
• Now, the ADC’s output becomes HI-Z, and
the converter is not involved
• SRAM is put on read mode
Data bus
ADC
hi-Z
uC
8 bit
CLK
CLK INT2
INT1
100 khz
Out[16]
write
read
SRAM
-full-
CLK
Address bus
17 bit
counter
Out[15:0]
Step 2: Samples are downloaded from SRAM to uC
•
•
The clock frequency is also set to a lower value (1001000 kHz)
On every clock cycle, INT2 is triggered and a sample is
stored in uC until 65536 (216 ) samples are transferred
Data bus
ADC
uC
8 bit
CLK
CLK INT2
INT1
100 khz
Out[16]
write
SRAM
-empty-
CLK
Address bus
17 bit
counter
Out[15:0]
Step 3: Samples are packed and sent to PC
Using a serial communication, samples are sent in order to be displayed in GUI.
Usually, the protocol is USB or UART(via FTDI).
Data bus
ADC
uC
8 bit
CLK
CLK INT2
INT1
100 khz
Out[16]
write
SRAM
-empty-
CLK
Address bus
17 bit
counter
Out[15:0]
Performance:
• Because
When it comes
Arduino
to does
sampling
not have
rate, enough
the onlyinternal
factor that
memory,
influences
two solutions
it is the
can
performance
be adopted:
of the SRAM (memory access time)
1.
• That
Use is
a smaller
why even
buffer
a low performance microcontroller can deal with this
2. application
Download data from SRAM in two stages
• Anyway, despite this fact, the refresh rate will be the main disadvantage.
Download
the first 1K
from SRAM
Send it to
PC
Download
the second
1K from
SRAM
Send it to
PC
• Lets consider a very popular development board based on an 8 bit uC
• Assuming that we want to use an Arduino Uno, and we choose a buffer
length of 2048 samples and a transmission rate equal to 115200 baud, the
refresh time will be:
𝑡𝑟𝑒𝑓𝑟𝑒𝑠ℎ ≅ 𝑡𝑑𝑜𝑤𝑛𝑙𝑜𝑎𝑑 + 𝑡𝑠𝑒𝑛𝑑
1
𝑡𝑑𝑜𝑤𝑛𝑙𝑜𝑎𝑑 = 2048 ∙
100𝑘𝐻𝑧
8
𝑡𝑠𝑒𝑛𝑑 = 2048 ∙
115200
𝑡𝑟𝑒𝑓𝑟𝑒𝑠ℎ = 20𝑚𝑠 + 142𝑚𝑠
Personal Project: Portable USB Oscilloscope
•
•
•
•
•
•
•
•
Based on
PIC32MZ
Despite
the
fact that (200Mhz
it is not clock)
50 powerful
MSPS sampling
rate
as
as a laboratory
100ms refreshit rate
oscilloscope,
meets the
65536 buffer length
requirements
of a wide range
8 bit
resolution
of
applications
±25V input swing
Powered from USB
Dimensions: 3.4inch x 2inch
Smaller than a smartphone
Basic
acquisition
system
A better
approach
A FPGA
makes the
difference
The FPGA
• By using a FPGA, all the digital part can be included in a single entity
• The behavior of this entity can be easily designed using a hardware
description language
• Lets consider the previous block schematic
Data bus
ADC
uC
M bit
CLK
CLK INT2
INT1
Out[N-1]
write
SRAM
CLK
Address bus
N-1 bit
N bit
counter
Out[N-2:0]
All the digital discreet components
can be described as modules
ADC
The FPGA
Other modules
CLK
As all the digital part is encapsulated
in a single chip, there will not be so
many interconnection wires. This will
prevent the signal integrity to be
altered, so the system will afford to
work with faster clock signals.
SRAM
N bit
counter
Advantages of a FPGA
•
•
•
•
Possibility of working at higher clock frequencies (hundreds of Mhz)
Possibility of parallelization of processes.
A changeable circuit structure
Signal processing features: Easy to describe FFT cores and
Digital Filters
• Lets see a possible implementation of an Oscilloscope + Spectrum
Analyzer.
A
D
C
FPGA
blocks
R
A
M
re
F
F
T im
S
e
n
d
^2
+
^2
R
A
M
R
A
M
√
Personal Project
Plug-in module for Digilent
Nexys board
• 100MSPS
• FFT capabilities
• If you already have a Nexys Board, this is definitely the
easiest way to build your own oscilloscope
The
TheLabview
modulesschematic
100Mhz
The oscilloscope
clk_200
ADC_mux
ADC_config module
clk_50
pll_loop_core
Sequential blocks
clk
(sysyem clock)
decoder
S2
[9:0]
FFT_core
S4
[9:0]
S5
[19:0]
S7
[20:0]
S8
[20:0]
ram_fft_20bit
√
Root Square
S6
[19:0]
mux_ram3
ram_adc
sq_re
^2
sq_re
^2
mux_ram1
decoder
S1
[9:0]
S3
[9:0]
Combinational blocks
S9 [9:0]
UART
ram_fft_10bit
receiver
S0
[9:0]
transmitter
ADC_clock
Data
bus
100MSPS ADC
PC
S10 [9:0]
The Labview GUI
Basic
acquisition
system
A better
approach
A FPGA
makes the
difference
Trigger, time
base and
input circuit
Trigger level
• In order to analyze a periodical signal, it has to be synchronized
• In other words, the acquisition process has to start from the
same voltage level (and also same slope)
• Without a trigger adjustment, the signal will seem to be in a
continuous movement
That is how an unsynchronized signal
looks like
Implementing a triggering mechanism
• On the microcontroller based approach
Input signal
(same with the one from
ADC’s input)
Connected to
an interrupt pin
The trigger level
As soon as the input signal equals the reference voltage (the trigger level), a
comparator notifies the microcontroller by switching its output
• On the FPGA based approach
This situation is much easier: a digital comparator module can be implemented to
compare the converted value (the digital one) with a certain binary number (trigger level)
The analog circuit
Any data acquisition system requires an input analog circuit to:
•
•
Amplify low amplitude signals (especially if the converter’s resolution is small)
Provide a high input impedance
Input buffer:
Provides high
impedance
ADC driver
The MOS transmission gates
adjusts the resistance in the
feedback network in order to set
the amplification
The time base
A time base adjustment is mandatory, especially when we
use a high speed data acquisition board to acquire a low
frequency signal
Examples
The number of samples/period is the following:
𝑠𝑎𝑚𝑝𝑙𝑒𝑠
𝑠𝑖𝑔𝑛𝑎𝑙 ′ 𝑠 𝑝𝑒𝑟𝑖𝑜𝑑
𝑠𝑎𝑚𝑝𝑙𝑖𝑛𝑔 𝑟𝑎𝑡𝑒
=
=
𝑝𝑒𝑟𝑖𝑜𝑑
𝑠𝑎𝑚𝑝𝑙𝑖𝑛𝑔 𝑝𝑒𝑟𝑖𝑜𝑑 𝑠𝑖𝑔𝑛𝑎𝑙 ′ 𝑠 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦
So, if the sampling rate is much higher than the
signal’s frequency, a huge number of samples will
result even for a single period.
4 𝑠𝑎𝑚𝑝𝑙𝑒𝑠
The time base
- stored sample
- ignored sample
• So, in order to acquire low frequency signals, the sampling rate should be
adjusted
• For the microcontroller approach, the counter’s clock can be modified from
microcontroller (using the PWM peripheral). Consequently, the counter will
increment its output slower. The ADC’s clock remains the same, because
high speed ADCs can’t operate with low frequency clock signals.
• As a conclusion, the time base is directly dependent on the sampling rate
• For the FPGA approach, a clock divider can be implemented (PLL or counter)
• Thus, the system stores just a few samples that ADC outputs.
1
1
1
1
1
1
1
1
Divide by 1
1
2
3
4
1
2
3
4
Divide by 4
1
2
3
4
5
6
7
8
Divide by 8
Conclusions
• My talk covered some implementations of data acquisition
systems, starting with applications based on low performance
systems to high speed digital systems.
• As the domain of data acquisitions is encountered in a wide
range of activities, from hobby to research, it is very important to
know as many approaches as possible in order to find the most
suitable one.
• Depending on needs and available resources, probably one of
the mentioned solutions will meet your requirements.
• Dealing with high speed applications using low performance
processing environments is very important because quite often
the consumption can be a strict limit.